Circuit hypergraph determination method, device, computer equipment and storage medium

Abstract

The present invention relates to the field of FPGA technology, and discloses a circuit hypergraph determination method, device, computer equipment and storage medium, the method comprising: obtaining a topological diagram of an original circuit designed for an FPGA chip, and determining the topological order corresponding to each logic unit in the original circuit based on the topological diagram; determining at least one heterogeneous resource in the original circuit; determining the connection information between the logic units in each heterogeneous resource based on the topological order, and constructing a hypergraph of each heterogeneous resource according to the logic units and the connection information, so as to obtain a hypergraph collection corresponding to the original circuit. The present invention reduces the complexity of the hypergraph when solving by a layout algorithm, and at the same time reduces the constraints and reduces the difficulty of solving the layout algorithm. In addition, since there is no coupling relationship between the hypergraphs corresponding to different types of heterogeneous resources, the hypergraph collection can be operated in parallel, which further improves the solution efficiency and improves the solution quality.

Description

Technical Field

[0001] The present invention relates to the field of FPGA technology, and in particular to a circuit hypergraph determination method, device, computer equipment and storage medium. Background Art

[0002] FPGA (Field Programmable Gate Array) chip is a chip that can be configured with circuit functions after manufacturing. Configuring the circuit functions of FPGA chips requires a series of processes such as synthesis, layout, and routing. Layout refers to the process of mapping the basic logic units in the original circuit to the corresponding components on the FPGA chip.

[0003] In the layout stage, considering that the logic units in the original circuit are usually set with corresponding constraints during layout, such as position constraints, connection relationship constraints, etc., the constraints need to be met when mapping the original circuit to the FPGA chip so that the circuit function can operate normally. Therefore, before mapping, the original circuit must first be modeled into a hypergraph (the hyperedges in the hypergraph are allowed to pass through multiple vertices, which can better describe the connection relationship between the logic units in the original circuit), and the hypergraph is solved by the layout algorithm to obtain a solution that meets the constraints of the original circuit. However, in the relevant technical solutions, since the hypergraph obtained by modeling the original circuit is often more complex and has more constraints, the difficulty of solving the layout algorithm is significantly increased, which reduces the efficiency of solving and reduces the quality of the solution obtained. Summary of the invention

[0004] In view of this, the present invention provides a circuit hypergraph determination method, apparatus, computer equipment and storage medium to solve the problem in related technical solutions that the difficulty of solving is significantly increased and the efficiency of solving is reduced due to the large number of layout algorithm constraints.

[0005] In a first aspect, the present invention provides a method for determining a circuit hypergraph, the method comprising:

[0006] Obtain a topological diagram of an original circuit designed for an FPGA chip, and based on the topological diagram, determine a topological order corresponding to each logic unit in the original circuit;

[0007] Determine at least one heterogeneous resource in the original circuit, wherein each of the heterogeneous resources includes logic units with the same function;

[0008] Based on the topological order, the connection information between the logic units in each of the heterogeneous resources is determined, and a hypergraph of each of the heterogeneous resources is constructed according to the logic units and the connection information to obtain a collection of hypergraphs corresponding to the original circuit.

[0009] The circuit hypergraph determination method provided in this embodiment can first obtain the topology map of the original circuit designed for the FPGA chip, and determine the topological order corresponding to each logic unit in the original circuit based on the topological map. Then, at least one heterogeneous resource can be determined in the original circuit, and the connection information between the logic units in each heterogeneous resource can be determined based on the above topological order, and the hypergraph of each heterogeneous resource can be constructed according to the logic unit and the connection information to obtain the hypergraph collection corresponding to the original circuit, thereby reducing the complexity of each hypergraph. At the same time, it should be understood that when the layout algorithm is solving, different types of heterogeneous resources are usually solved separately. Therefore, in this embodiment, a hypergraph of each heterogeneous resource can be constructed separately, thereby reducing the constraints when solving each hypergraph, and reducing the difficulty of solving the layout algorithm. In addition, since there is no coupling relationship between the hypergraphs corresponding to different types of heterogeneous resources, the hypergraph collection can be operated in parallel, which further improves the solution efficiency and improves the solution quality.

[0010] In an optional implementation, the determining of connection information between logical units in each heterogeneous resource based on the topological order includes:

[0011] Determining a hyperedge between logic units in each heterogeneous resource, wherein the hyperedge is an edge connecting the logic units;

[0012] Determine the weight of the hyperedge based on the topological order of the logical units corresponding to the hyperedge;

[0013] The connection information is determined according to the hyperedge of the logic unit and the weight corresponding to the hyperedge.

[0014] In this embodiment, the weight of the hyperedge can be determined based on the topological order corresponding to the hyperedge, and the connection information can be determined according to the hyperedge of the logical unit and the weight corresponding to the hyperedge, so that the path length between the logical units can be obtained based on the weight, which is convenient for subsequent solution through the layout algorithm.

[0015] In an optional implementation, the determining the weight of the hyperedge based on the topological order of the logical units corresponding to the hyperedge includes:

[0016] Determine a first difference between the logical layers corresponding to the logical unit corresponding to the hyperedge in the topological order, and determine the first difference as the weight of the hyperedge, wherein the logical layer number is used to indicate the depth value of the logical unit in the topological map;

[0017] Alternatively, when there are multiple paths between the logic units corresponding to the hyperedge in the topological graph, a shortest path is determined among the multiple paths, and the length value of the shortest path is determined as the weight of the hyperedge.

[0018] In this embodiment, the weight of the hyperedge can be determined by the first difference between the number of logical layers of the logical units corresponding to the hyperedge, so that when solving the layout algorithm according to the hypergraph, the length of the path corresponding to the hyperedge is obtained based on the weight to meet the requirements of the calculation constraints.

[0019] In an optional implementation, the above method further includes:

[0020] After determining the weight of the hyperedge, determining a maximum layer value among the logical layers corresponding to the topological order;

[0021] Based on a second difference between the maximum layer value and the weight, the weight of the hyperedge is adjusted.

[0022] In this embodiment, considering that in some layout algorithms, the weight of the hyperedge is required to be inversely proportional to the distance between logic units, the weight of the hyperedge can be adjusted after being determined to meet the requirements of the layout algorithm, thereby improving the scope of application of this embodiment.

[0023] In an optional implementation manner, the step of determining the hyperedges between the logic units in each heterogeneous resource includes:

[0024] Based on the topology graph, determining the to-be-confirmed hyperedges corresponding to the adjacent logical units in the heterogeneous resources;

[0025] A deduplication operation is performed on the hyperedges to be confirmed that have passed through the preset logic unit in the hyperedges to be confirmed, so as to obtain the hyperedges corresponding to the adjacent logic unit.

[0026] In this embodiment, considering that in actual usage scenarios, the structure of the topological graph is often more complex, when determining the hypergraph based on the topological graph, there may be multiple repeated hyperedges to be confirmed between the vertices of the vertex group. Based on this, the hyperedges to be confirmed can be deduplicated to simplify the structure of the hypergraph and reduce the difficulty of solving the subsequent layout algorithm based on the hypergraph.

[0027] In an optional implementation, the preset logic unit includes at least one of the following: a logic unit of the same type as the adjacent logic unit, and a logic unit at a determined position in the original circuit.

[0028] In an optional implementation, the determining of the topological order corresponding to each logic unit in the original circuit based on the topological graph includes:

[0029] Determine a starting node that meets the in-degree condition in the topology map, and set the logical layer number of the starting node to a starting value, wherein the logical layer number is used to indicate a depth value of a logical unit in the topology map;

[0030] Based on the difference between the depth value of the corresponding node of each logic unit in the original circuit in the topological map and the starting value, the topological order corresponding to each logic node is set.

[0031] In this embodiment, the starting node can be first determined in the topological map and a starting value can be set for the starting node. Then, the difference between the depth value of each node and the starting value can be calculated to obtain the topological order corresponding to each node, thereby providing a basis for an embodiment of determining the connection information between logical units in each heterogeneous resource based on the topological order.

[0032] In a second aspect, the present invention provides a circuit hypergraph determination device, the device comprising:

[0033] A first determination module is used to obtain a topology diagram of an original circuit designed for an FPGA chip, and determine a topology order corresponding to each logic unit in the original circuit based on the topology diagram;

[0034] A second determination module is used to determine at least one heterogeneous resource in the original circuit, wherein each of the heterogeneous resources includes logic units with the same function;

[0035] The hypergraph construction module is used to determine the connection information between the logic units in each of the heterogeneous resources based on the topological order, and to construct the hypergraph of each of the heterogeneous resources according to the logic units and the connection information to obtain a collection of hypergraphs corresponding to the original circuit.

[0036] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the circuit hypergraph determination method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0037] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the circuit hypergraph determination method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 Shown is a schematic diagram of the FPGA chip structure;

[0040] Figure 2 FIG. 2 is a schematic diagram of a flow chart of a method for determining a circuit hypergraph according to an embodiment of the present invention;

[0041] Figure 3 Shown is a schematic diagram of the circuit diagram corresponding to the original circuit;

[0042] Figure 4a Schematic diagram of the hypergraph corresponding to heterogeneous resource A;

[0043] Figure 4b Schematic diagram of the hypergraph corresponding to heterogeneous resource B;

[0044] Figure 4c Schematic diagram of the hypergraph corresponding to heterogeneous resources C;

[0045] Figure 5 is a flow chart of another circuit hypergraph determination method according to an embodiment of the present invention;

[0046] Figure 6 is a flow chart of another circuit hypergraph determination method according to an embodiment of the present invention;

[0047] Figure 7 is a structural block diagram of a circuit hypergraph determination device according to an embodiment of the present invention;

[0048] Figure 8 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0050] In conjunction with the application scenarios on which the execution of the circuit hypergraph determination method depends, the application scenarios are described herein.

[0051] FPGA (Field Programmable Gate Array) chip is a chip that can be configured with circuit functions after manufacturing. Configuring the circuit functions of FPGA chips requires a series of processes such as synthesis, layout, and routing. Among them, layout refers to the process of mapping the basic logic units in the original circuit to the corresponding components on the FPGA chip.

[0052] In the layout stage, considering that the logic units in the original circuit are usually set with corresponding constraints during layout, such as position constraints, connection relationship constraints, etc., the constraints need to be met when mapping the original circuit to the FPGA chip so that the circuit function can operate normally. Therefore, before mapping, the original circuit must first be modeled into a hypergraph (the hyperedges in the hypergraph are allowed to pass through multiple vertices, which can better describe the connection relationship between the logic units in the original circuit), and the hypergraph is solved by the layout algorithm to obtain a solution that meets the constraints of the original circuit. However, in the relevant technical solutions, since the hypergraph obtained by modeling the original circuit is often more complex and has more constraints, the difficulty of solving the layout algorithm is significantly increased, which reduces the efficiency of solving and reduces the quality of the solution.

[0053] It should be understood that if Figure 1 The schematic diagram of the FPGA chip structure is shown, wherein the FPGA chip includes a plurality of heterogeneous resources (for example, resource A, resource B, and resource C), each heterogeneous resource includes a plurality of resource modules, and each resource module includes a plurality of logic units with the same function (specifically, the internal structure of each resource module Figure 1 It should be understood that different types of logic units are also heterogeneous, and logic units with different functions can be composed of different components. Based on this, when designing the original circuit, the logic units in the original circuit can be represented by heterogeneous resources, and the types of these heterogeneous resources correspond one-to-one to the heterogeneous resources in the FPGA chip.

[0054] According to an embodiment of the present invention, a circuit hypergraph determination method embodiment is provided. In the embodiment of the present invention, first, a topological diagram of the original circuit designed for an FPGA chip can be obtained, and based on the topological diagram, the topological order corresponding to each logic unit in the original circuit can be determined. Then, at least one heterogeneous resource can be determined in the original circuit, and based on the above topological order, the connection information between the logic units in each heterogeneous resource can be determined, and a hypergraph of each heterogeneous resource can be constructed according to the logic unit and the connection information to obtain a hypergraph collection corresponding to the original circuit, thereby reducing the complexity of each hypergraph, while reducing the constraints and reducing the difficulty of solving the layout algorithm. In addition, since there is no coupling relationship between the hypergraphs corresponding to different types of heterogeneous resources, the hypergraph collection can be operated in parallel, which further improves the solution efficiency and improves the solution quality.

[0055] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0056] In this embodiment, a circuit hypergraph determination method is provided, which can be used in the above-mentioned computer device. Figure 2 is a flow chart of a method for determining a circuit hypergraph according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0057] Step S201, obtaining a topology diagram of an original circuit designed for an FPGA chip, and determining a topology order corresponding to each logic unit in the original circuit based on the topology diagram.

[0058] In this embodiment, the original circuit designed for the FPGA chip can be first obtained, and a corresponding topology diagram can be established based on the original circuit. Specifically, the original circuit can be abstracted to obtain a topology diagram consisting of only branches and nodes. In the topology diagram, the nodes can be logic units in the original circuit, and the branches can be connection relationships between logic units, wherein the branches can be directed edges, that is, they can indicate the specific wiring direction between logic units.

[0059] After determining the above topological graph, the topological order of each logic unit in the original circuit can be determined based on the topological graph. Here, all nodes in the topological graph can be topologically sorted to obtain the topological order of each logic unit in the logic circuit.

[0060] Specifically, when performing topological sorting, we can first calculate the in-degree of each node in the topological graph, that is, the number of directed edges pointing to the node, and find the node with in-degree 0. Here, a node with in-degree 0 means that there is no directed edge pointing to it, so it can be the starting node of the topological sorting. Then, we can set the current topological order to 0, and reduce the in-degree of the node in the next layer adjacent to the starting node by 1, and increase the current topological order by 1.

[0061] Next, you can continue to search for the node with the current in-degree of 0, and set the node with in-degree 0 as the starting node, and at the same time reduce the in-degree of the node in the next layer adjacent to the starting node by 1, and increase the current topological order by 1. Here, you can repeat the above topological sorting steps until all nodes in the topological graph are topologically sorted.

[0062] In addition, during the topological sorting process, if no node with in-degree 0 is found, and there are still nodes without topological order, it means that there is a loop in the topological graph (that is, the directed edges between several nodes are connected end to end), so topological sorting cannot be performed. At this time, you can delete all the directed edges with loops in the topological graph, and continue to search for nodes with in-degree 0 to repeat the above topological sorting steps.

[0063] For example, if Figure 3The circuit diagram corresponding to the original circuit is shown, wherein the original circuit includes an input unit, heterogeneous resources A (specifically including resources A1-A3 in the figure), heterogeneous resources B (specifically including resources B1-B6 in the figure), heterogeneous resources C (specifically including resources C1-C2 in the figure) and an output unit. The specific method of establishing the corresponding topology diagram for the original circuit diagram is not described here.

[0064] After determining the corresponding topological graph, the topological order of the nodes and the logical layer number of each node can be determined based on the topological graph, where the logical layer number can be used to indicate the depth of each node in the topological graph. For example, the logical layer number corresponding to the input unit can be 0, the logical layer number corresponding to resources A1-A3 can be 1, the logical layer number corresponding to resources B1-B3 can be 2, the logical layer number corresponding to resource C1 can be 3, the logical layer number corresponding to resources B4-B6 can be 4, the logical layer number corresponding to resource C2 can be 5, and the logical layer number corresponding to the output unit can be 6.

[0065] Step S202: determining at least one heterogeneous resource in the original circuit, wherein each of the heterogeneous resources includes logic units with the same functions.

[0066] In this embodiment, the same type of heterogeneous resources include logic units with the same functions, for example, the logic units may be CLBs (Configurable Logic Blocks), DSPs (Digital Signal Processors), etc. Figure 1 It can be seen that the FPGA chip contains a variety of heterogeneous resources. Therefore, when designing the original circuit, it can also be set with heterogeneous resources as the basic component unit. For example, the schematic diagram of the original circuit can be as shown above. Figure 3 shown.

[0067] Step S203, based on the topological order, determining the connection information between the logic units in each of the heterogeneous resources, and constructing a hypergraph of each of the heterogeneous resources according to the logic units and the connection information, so as to obtain a collection of hypergraphs corresponding to the original circuit.

[0068] In this embodiment, the connection information may include a hyperedge in a hypergraph and a weight corresponding to each hyperedge, wherein the hyperedge may be used to connect multiple heterogeneous resources. Here, the heterogeneous resources in the original circuit may be first classified to obtain multiple heterogeneous resources. Figure 3 Taking the original circuit in as an example, after classifying the heterogeneous resources, heterogeneous resources A, heterogeneous resources B, heterogeneous resources C and fixed resources (specifically including input units and output units) can be obtained respectively.

[0069] Next, hypergraphs corresponding to various heterogeneous resources can be constructed separately. It should be understood that there is no need to construct a hypergraph for fixed resources separately. Specifically, when constructing a hypergraph, each heterogeneous resource in each heterogeneous resource can be first determined as a vertex, and the hyperedges between the vertices can be determined according to the corresponding connection mode of each vertex in the original circuit.

[0070] If for the above Figure 3 The hypergraph is constructed by splitting the original circuit in Figure 4a-4c The hypergraph shown in Figure 1, where Figure 4a is the hypergraph corresponding to heterogeneous resource A, Figure 4b is the hypergraph corresponding to heterogeneous resource B, Figure 4c is the hypergraph corresponding to the heterogeneous resource C. It should be understood that when constructing a hypergraph, the weight corresponding to each hyperedge can be determined separately. Specifically, the weight of the hyperedge can be calculated based on the difference in the number of logical layers between the vertices corresponding to the hyperedge. Figure 4a Taking the hypergraph in as an example, when calculating the weight of the hyperedge between the input vertex and the A1 vertex, the difference in the number of logical layers between the input vertex and the A1 vertex can be calculated, and the difference in the number of logical layers can be determined as the weight of the hyperedge.

[0071] The circuit hypergraph determination method provided in this embodiment can first obtain the topology map of the original circuit designed for the FPGA chip, and determine the topological order corresponding to each logic unit in the original circuit based on the topological map. Then, at least one heterogeneous resource can be determined in the original circuit, and the connection information between the logic units in each heterogeneous resource can be determined based on the above topological order, and the hypergraph of each heterogeneous resource can be constructed according to the logic unit and the connection information to obtain the hypergraph collection corresponding to the original circuit, thereby reducing the complexity of each hypergraph. At the same time, it should be understood that when the layout algorithm is solving, different types of heterogeneous resources are usually solved separately. Therefore, in this embodiment, a hypergraph of each heterogeneous resource can be constructed separately, thereby reducing the constraints when solving each hypergraph, and reducing the difficulty of solving the layout algorithm. In addition, since there is no coupling relationship between the hypergraphs corresponding to different types of heterogeneous resources, the hypergraph collection can be operated in parallel, which further improves the solution efficiency and improves the solution quality.

[0072] In this embodiment, another circuit hypergraph determination method is provided, which can be used in the above-mentioned computer device. Figure 5 is a flow chart of a method for determining a circuit hypergraph according to an embodiment of the present invention. Figure 5 As shown, the process includes the following steps:

[0073] Step S501, obtaining a topology diagram of an original circuit designed for an FPGA chip, and determining a topology order corresponding to each logic unit in the original circuit based on the topology diagram.

[0074] Specifically, the above step S501 includes:

[0075] Step S5011, determining a starting node that meets an in-degree condition in the topology map, and setting the logical layer number of the starting node to a starting value, wherein the logical layer number is used to indicate a depth value of a logical unit in the topology map.

[0076] In this embodiment, as described above Figure 2 In the embodiment corresponding to step S201, the in-degree condition may be that the in-degree is 0, and the starting value may be set to 0. It should be understood that the starting value may be the number of logical layers of the starting node, and may also be adjusted according to actual use requirements.

[0077] Step S5012: setting a topological order corresponding to each logic node in the original circuit based on a difference between a depth value of a corresponding node in the topological graph and the starting value.

[0078] In this embodiment, the above-mentioned depth value can be used to indicate the number of layers of each node in the topological map corresponding to the original circuit. When determining the depth value, the BFS (Breadth-First Search) algorithm can be used to traverse the topological map layer by layer, and mark the number of layers corresponding to each node until all nodes in the topological map are traversed. It should be understood that the number of layers of each node in the topological map can also be determined by other methods, such as the DFS (Depth-First Search) algorithm.

[0079] For each node in the above topological graph, the logical level of the node can be determined based on the difference between the depth value and the starting value of the node, so as to set the topological order corresponding to the node based on the logical level. For example, the topological order of the node with a small logical level is also smaller than that of the node with a large logical level. Figure 3 Taking the original circuit in as an example, the topological order corresponding to the nodes A1-A3 with a logical level of 1 is 2, 3, and 4, respectively, and the topological order corresponding to the nodes B1-B3 with a logical level of 2 is 5, 6, and 7, respectively.

[0080] In this embodiment, the starting node can be first determined in the topological graph and a starting value can be set for the starting node. Then, the difference between the depth value of each node and the starting value can be calculated to obtain the topological order corresponding to each node, thereby providing a basis for an embodiment of determining the connection information between logical units in each heterogeneous resource based on the topological order.

[0081] Step S502: Determine at least one heterogeneous resource in the original circuit, wherein each heterogeneous resource includes logic units with the same functions. Figure 2 Step S202 of the illustrated embodiment will not be described in detail here.

[0082] Step S503: Based on the topological order, determine the connection information between the logical units in each of the heterogeneous resources, and construct a hypergraph of each of the heterogeneous resources according to the logical units and the connection information to obtain a hypergraph collection corresponding to the original circuit. Figure 2 Step S203 of the illustrated embodiment will not be described in detail here.

[0083] In this embodiment, another circuit hypergraph determination method is provided, which can be used in the above-mentioned computer device. Figure 6 is a flow chart of a method for determining a circuit hypergraph according to an embodiment of the present invention. Figure 6 As shown, the process includes the following steps:

[0084] Step S601, obtain a topology diagram of the original circuit designed for the FPGA chip, and determine the topology order corresponding to each logic unit in the original circuit based on the topology diagram. Figure 2 Step S201 of the illustrated embodiment will not be described in detail here.

[0085] Step S602: Determine at least one heterogeneous resource in the original circuit, wherein each heterogeneous resource includes logic units with the same functions. Figure 2 Step S202 of the illustrated embodiment will not be described in detail here.

[0086] Step S603, based on the topological order, determine the connection information between the logic units in each of the heterogeneous resources, and construct a hypergraph of each of the heterogeneous resources according to the logic units and the connection information, so as to obtain a collection of hypergraphs corresponding to the original circuit.

[0087] Specifically, the above step S603 includes:

[0088] Step S6031, determining a hyperedge between logical units in each heterogeneous resource, wherein the hyperedge is an edge connecting the logical units.

[0089] In some optional implementations, the above step S6031 includes:

[0090] Step a1: based on the topology graph, determine the hyperedges to be confirmed corresponding to the adjacent logical units in the heterogeneous resources.

[0091] Step a2: performing a deduplication operation on the hyperedges to be confirmed that pass through the preset logic unit in the hyperedges to be confirmed, and obtaining the hyperedges corresponding to the adjacent logic unit.

[0092] In this embodiment, when corresponding hypergraphs are established for various heterogeneous resources, the path between the vertex groups can be searched in the topology graph through a preset search strategy to obtain the hyperedge to be confirmed corresponding to the vertex group. Here, the adjacent vertices are the adjacent logical units mentioned above. The specific preset search strategies include the following search methods:

[0093] Method 1: DFS algorithm.

[0094] In this embodiment, adjacent vertices can be first determined as vertex groups, and all nodes in the topological graph are traversed one by one in order from small to large according to the above topological order, so as to obtain several paths from the starting node to the ending node, and the paths between the vertex groups to be found are determined according to the traversal results, until all paths between nodes corresponding to the same heterogeneous resources are found, so as to obtain the above-mentioned hyperedge to be confirmed. Figure 4a Taking the hypergraph corresponding to the heterogeneous resource A in as an example, all paths of the nodes corresponding to the heterogeneous resource A include: input-A1-output, input-A2-output, input-A3-output.

[0095] Method 2: BFS algorithm.

[0096] In this embodiment, the vertices in the above vertex group can be used as the starting nodes, and all nodes in the topological graph can be traversed layer by layer in the order of topological order from small to large. Figure 4b Take the hypergraph corresponding to the heterogeneous resource B in the topology graph corresponding to the original circuit as an example. In the topology graph corresponding to the original circuit, if B1 is used as the starting node, the nodes in the topology graph can be traversed layer by layer until all paths between nodes corresponding to the same heterogeneous resources are found, so as to obtain the hyperedge to be confirmed. For example, first find the path between the node with a logical layer difference of 1 with B1 and B1, that is, nodes A1, A2, A3 and C1. Then, the path between the nodes with a logical layer difference of 2, 3, 4, etc. with B1 can be found in turn, until all paths between the nodes corresponding to the heterogeneous resource B in the topology graph are found.

[0097] It should be understood that in actual use scenarios, the method 1 or the method 2 can be used to determine the hyperedge to be confirmed according to specific use requirements, and the present disclosure does not make specific limitations. For example, when there are many nodes in the topology graph, the method 2 can be used to improve accuracy, and the method 1 can be used to save computing time.

[0098] Considering that in actual usage scenarios, the structure of the topological graph is often complex, therefore, after determining the hyperedges to be confirmed, the hyperedges to be confirmed can be deduplicated according to the above vertex groups. Specifically, all the hyperedges to be confirmed corresponding to each pair of vertex groups can be deduplicated to remove the hyperedges to be confirmed that have passed through the preset logic unit.

[0099] Specifically, the preset logic unit may include at least one of the following: a logic unit of the same type as the adjacent logic unit, and a logic unit at a determined position in the original circuit.

[0100] In this embodiment, the logical unit of the same type as the adjacent logical unit is a heterogeneous resource of the same type as the adjacent logical unit. For example, if the adjacent logical unit is Figure 4b If B1 and B4 are present in the adjacent logical unit, the heterogeneous resource corresponding to the logical unit of the same type as the adjacent logical unit may be resource B. Here, if the path between vertex B2 and output includes vertex B2', the hyperedge B2-output to be confirmed may be deleted.

[0101] In addition, the logic unit for determining the position in the original circuit may be the fixed resource, that is, the input unit and the output resource. For example, if the vertex corresponding to the adjacent logic unit is Figure 4b B1 and B4 in , if the path between vertices B2 and B4 includes a fixed resource vertex F1, then the unconfirmed hyperedge passes through the fixed resource and needs to be deleted.

[0102] In this embodiment, considering that in actual usage scenarios, the structure of the topological graph is often more complex, when determining the hypergraph based on the topological graph, there may be multiple repeated hyperedges to be confirmed between the vertices of the vertex group. Based on this, the hyperedges to be confirmed can be deduplicated to simplify the structure of the hypergraph and reduce the difficulty of solving the subsequent layout algorithm based on the hypergraph.

[0103] Step S6032: Determine the weight of the hyperedge based on the topological order of the logical units corresponding to the hyperedge.

[0104] In some optional implementations, the above step S6032 includes the following implementations:

[0105] Method 1: Determine a first difference between the logical layers corresponding to the topological order of the logical units corresponding to the hyperedge, and determine the first difference as the weight of the hyperedge, wherein the logical layer number is used to indicate the depth value of the logical unit in the topological graph.

[0106] Method 2: When there are multiple paths between the logic units corresponding to the hyperedge in the topology graph, the shortest path is determined among the multiple paths, and the length value of the shortest path is determined as the weight of the hyperedge.

[0107] In this embodiment, the weight of the hyperedge can be used to indicate the distance between adjacent vertices corresponding to the hyperedge (vertices in the hypergraph correspond to logic units in the original circuit), and the number of logical layers can be used to indicate the number of layers of the node in the topology graph. Based on this, the first difference in the number of logical layers between adjacent vertices can be determined as the weight of the hyperedge between the adjacent vertices.

[0108] In addition, considering that in actual use scenarios, the structure of the topological graph is often complex, there may be multiple paths between the adjacent vertices. Since different paths may pass through different vertices, the path length values ​​of different paths may be different. In this case, the shortest path can be determined from the multiple paths, and the length value of the shortest path is determined as the weight of the hyperedge.

[0109] In this embodiment, weights may be set for hyperedges in the hypergraph, so that when solving a layout algorithm based on the hypergraph, the length of the path corresponding to the hyperedge is obtained based on the weights to meet the requirements of the computational constraints.

[0110] Step S6032: determine the connection information according to the hyperedge of the logic unit and the weight corresponding to the hyperedge.

[0111] In this embodiment, after determining the weight of the hyperedge, the step S603 further includes:

[0112] Step b1, determining a maximum level value among the logical levels corresponding to the topological order.

[0113] Step b2: adjusting the weight of the hyperedge based on the second difference between the maximum layer value and the weight.

[0114] In this embodiment, it is considered that the greater the distance between the logic units represented by the hyperedge, the greater the first difference, that is, the weight of the hyperedge is proportional to the distance between the logic units, while in some layout algorithms, the weight of the hyperedge is required to be inversely proportional to the distance between the logic units.

[0115] Based on this, the node with the largest number of logical layers among all nodes in the topological graph can be determined, and the number of logical layers of the node can be determined as the maximum layer value. Then, the second difference between the maximum layer value and the current weight of the hyperedge can be calculated, and the second difference can be updated as the weight of the hyperedge, so that the weight of the hyperedge is inversely proportional to the distance between the logical units.

[0116] For example, if the original weight of hyperedge 1 is 3, the original weight of hyperedge 2 is 5, and the determined maximum layer value is 7, then the updated weight of hyperedge 1 is 4, and the weight of hyperedge 2 is 2. At this time, the updated weight of the hyperedge is inversely proportional to the distance between the logical units.

[0117] In this embodiment, considering that in some layout algorithms, the weight of the hyperedge is required to be inversely proportional to the distance between logic units, the weight of the hyperedge can be adjusted after being determined to meet the requirements of the layout algorithm, thereby improving the scope of application of this embodiment.

[0118] In summary, in this embodiment, first, the topology map of the original circuit designed for the FPGA chip can be obtained, and based on the topology map, the topological order corresponding to each logic unit in the original circuit can be determined. Then, at least one heterogeneous resource can be determined in the original circuit, and based on the above topological order, the connection information between the logic units in each heterogeneous resource can be determined, and the hypergraph of each heterogeneous resource can be constructed according to the logic unit and the connection information to obtain the hypergraph collection corresponding to the original circuit, thereby reducing the complexity of each hypergraph. At the same time, it should be understood that when the layout algorithm is solving, different types of heterogeneous resources are usually solved separately. Therefore, in this embodiment, a hypergraph of each heterogeneous resource can be constructed separately, thereby reducing the constraints when solving each hypergraph, and reducing the difficulty of solving the layout algorithm. In addition, since there is no coupling relationship between the hypergraphs corresponding to different types of heterogeneous resources, the hypergraph collection can be operated in parallel, which further improves the solution efficiency and improves the solution quality.

[0119] In this embodiment, a circuit hypergraph determination device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0120] This embodiment provides a circuit hypergraph determination device, such as Figure 7 As shown, including:

[0121] The first determination module 701 is used to obtain a topology diagram of an original circuit designed for an FPGA chip, and determine a topology sequence corresponding to each logic unit in the original circuit based on the topology diagram;

[0122] A second determination module 702 is used to determine at least one heterogeneous resource in the original circuit, wherein each of the heterogeneous resources includes logic units with the same function;

[0123] The hypergraph construction module 703 is used to determine the connection information between the logical units in each of the heterogeneous resources based on the topological order, and to construct the hypergraph of each of the heterogeneous resources according to the logical units and the connection information to obtain a hypergraph collection corresponding to the original circuit.

[0124] In some optional implementations, the hypergraph construction module 703 includes:

[0125] A first determining unit, configured to determine a hyperedge between logic units in each heterogeneous resource, wherein the hyperedge is an edge connecting the logic units;

[0126] A second determining unit, configured to determine a weight of the hyperedge based on a topological order of logical units corresponding to the hyperedge;

[0127] The third determining unit is used to determine the connection information according to the hyperedge of the logic unit and the weight corresponding to the hyperedge.

[0128] In some optional implementations, the second determining unit includes:

[0129] The first determination subunit is used to determine a first difference between the logical layers corresponding to the logical unit corresponding to the hyperedge in the topological order, and determine the first difference as the weight of the hyperedge, wherein the logical layer number is used to indicate the depth value of the logical unit in the topological map.

[0130] The second determining subunit is used to determine the shortest path among the multiple paths when there are multiple paths between the logic units corresponding to the hyperedge in the topology graph, and determine the length value of the shortest path as the weight of the hyperedge.

[0131] In some optional implementations, the hypergraph construction module 703 is further configured to:

[0132] After determining the weight of the hyperedge, determine the maximum layer value among the logical layers corresponding to the topological order;

[0133] Based on a second difference between the maximum layer value and the weight, the weight of the hyperedge is adjusted.

[0134] In some optional implementations, the first determining unit includes:

[0135] A third determination subunit is used to determine, based on the topology graph, the to-be-confirmed hyperedges corresponding to the adjacent logical units in the heterogeneous resources;

[0136] The deduplication subunit is used to perform a deduplication operation on the to-be-confirmed hyperedges that have passed through the preset logic unit in the to-be-confirmed hyperedges to obtain the hyperedges corresponding to the adjacent logic unit.

[0137] In some optional implementations, the preset logic unit includes at least one of the following: a logic unit of the same type as the adjacent logic unit, and a logic unit at a determined position in the original circuit.

[0138] In some optional implementations, the first determining module 701 includes:

[0139] A fourth determining unit is used to determine a starting node that meets the in-degree condition in the topological map, and set the number of logical layers of the starting node to a starting value, wherein the number of logical layers is used to indicate a depth value of a logical unit in the topological map;

[0140] The fifth determining unit is used to set the topological order corresponding to each of the logic nodes in the original circuit based on the difference between the depth value of the corresponding node in the topological map and the starting value.

[0141] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0142] The circuit hypergraph determination device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0143] The embodiment of the present invention also provides a computer device having the above Figure 7 The circuit hypergraph determination device shown.

[0144] See also Figure 8 , Figure 8 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 8 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 8 A processor 10 is taken as an example.

[0145] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0146] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0147] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0148] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0149] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0150] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for determining a circuit hypergraph, characterized in that: The method comprises: Obtaining a topological diagram of an original circuit designed for an FPGA chip, and determining a topological order corresponding to each logic unit in the original circuit based on the topological diagram; Determining at least one heterogeneous resource in the original circuit, wherein each of the heterogeneous resources includes logic units with the same function; Based on the topological order, connection information between logical units in each of the heterogeneous resources is determined, and a hypergraph of each of the heterogeneous resources is constructed according to the logical units and the connection information to obtain a collection of hypergraphs corresponding to the original circuit, wherein the determining the connection information between logical units in each of the heterogeneous resources based on the topological order includes: Determining a hyperedge between logic units in each of the heterogeneous resources, wherein the hyperedge is an edge connecting the logic units; Determining the weight of the hyperedge based on the topological order of the logical units corresponding to the hyperedge, wherein determining the weight of the hyperedge based on the topological order of the logical units corresponding to the hyperedge includes: Determine a first difference between the logical layers corresponding to the logical unit corresponding to the hyperedge and the topological order, and determine the first difference as the weight of the hyperedge, wherein the logical layer number is used to indicate the depth value of the logical unit in the topological map; Alternatively, when there are multiple paths between the logic units corresponding to the hyperedge in the topological graph, a shortest path is determined among the multiple paths, and a length value of the shortest path is determined as the weight of the hyperedge; The connection information is determined according to the hyperedges of the logic unit and the weights corresponding to the hyperedges.

2. The method according to claim 1, characterized in that The method further comprises: After determining the weight of the hyperedge, determining a maximum layer value among the logical layers corresponding to the topological order; Based on a second difference between the maximum layer value and the weight, the weight of the hyperedge is adjusted.

3. The method according to claim 1, characterized in that The step of determining the hyperedges between the logic units in each of the heterogeneous resources includes: Based on the topology graph, determining the to-be-confirmed hyperedges corresponding to the adjacent logical units in the heterogeneous resources; A deduplication operation is performed on the hyperedges to be confirmed that have passed through the preset logic unit in the hyperedges to be confirmed, so as to obtain the hyperedges corresponding to the adjacent logic unit.

4. The method according to claim 3, characterized in that The preset logic unit includes at least one of the following: a logic unit of the same type as the adjacent logic unit, and a logic unit at a determined position in the original circuit.

5. The method according to claim 1, characterized in that The determining, based on the topological graph, a topological order corresponding to each logic unit in the original circuit includes: Determine a starting node that meets an in-degree condition in the topology map, and set the logical layer number of the starting node to a starting value, wherein the logical layer number is used to indicate a depth value of a logical unit in the topology map; Based on the difference between the depth value of the corresponding node of each logic unit in the original circuit in the topological graph and the starting value, the topological order corresponding to each logic unit is set.

6. A circuit hypergraph determination device, characterized in that: The device comprises: A first determination module is used to obtain a topology diagram of an original circuit designed for an FPGA chip, and determine a topology order corresponding to each logic unit in the original circuit based on the topology diagram; A second determination module is used to determine at least one heterogeneous resource in the original circuit, wherein each of the heterogeneous resources includes logic units with the same function; A hypergraph construction module is used to determine the connection information between the logic units in each of the heterogeneous resources based on the topological order, and construct a hypergraph of each of the heterogeneous resources according to the logic units and the connection information, so as to obtain a hypergraph collection corresponding to the original circuit, wherein the connection information between the logic units in each of the heterogeneous resources is determined based on the topological order, including: determining a hyperedge between the logic units in each of the heterogeneous resources, wherein the hyperedge is an edge connecting the logic units; determining the weight of the hyperedge based on the topological order of the logic units corresponding to the hyperedge, wherein the hypergraph based on the hypergraph The topological order of the logical units corresponding to the edge, determining the weight of the hyperedge, including: determining a first difference between the logical layers corresponding to the logical units corresponding to the hyperedge in the topological order, and determining the first difference as the weight of the hyperedge, wherein the logical layer is used to indicate the depth value of the logical unit in the topological graph; or, when there are multiple paths between the logical units corresponding to the hyperedge in the topological graph, determining the shortest path among the multiple paths, and determining the length value of the shortest path as the weight of the hyperedge; determining the connection information according to the hyperedge of the logical unit and the weight corresponding to the hyperedge.

7. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the circuit hypergraph determination method according to any one of claims 1 to 5 by executing the computer instructions.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the circuit hypergraph determination method according to any one of claims 1 to 5.

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