Memory and control method thereof, circuit board, electronic device

Abstract

The application provides a memory and a control method and circuit thereof, a circuit board and an electronic device, and relates to the technical field of storage. The memory can use a wire for transmitting a first signal to the memory instead of a plurality of existing wires for transmitting commands. The memory comprises a recovered clock receiver, a command decoder, a plurality of storage units and a first command interface. The recovered clock receiver is configured to receive a first signal transmitted by a control circuit through the first command interface under the triggering of a first clock signal, and transmit the first signal to the command decoder. The clock frequency of the first clock signal is the same as the clock frequency of a second clock signal in the control circuit for triggering the output of the first signal. The command decoder determines a first command matched with the received first signal, and transmits the first command to at least part of the storage units. At least part of the storage units receive the first command and perform an operation matched with the first command.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a memory, a control method and circuit thereof, a circuit board and an electronic device. BACKGROUND

[0002] In recent years, with the rapid development of the field of artificial intelligence (AI) and the field of computing, there is a higher requirement for the capacity of the memory. The requirement for the capacity of the memory can be met by increasing the number of memories in the electronic device.

[0003] However, the increase in the number of memories inevitably leads to an increase in the wiring resources on the circuit board for integrating the memories, and further leads to an increase in the board-level space resources of the circuit board. SUMMARY

[0004] To solve the above technical problems, the present application provides a memory, a control method and circuit thereof, a circuit board and an electronic device, which can use the wiring for transmitting the first signal from the control circuit to the memory to replace the existing multiple wirings for transmitting the command.

[0005] In a first aspect, the present application provides a memory, which comprises a recovered clock receiver, a command decoder, a plurality of memory units and a first command interface. The recovered clock receiver is configured to receive a first signal transmitted by a control circuit through the first command interface under the triggering of a first clock signal, and transmit the first signal to the command decoder. The clock frequency of the first clock signal is the same as the clock frequency of a second clock signal in the control circuit for triggering the output of the first signal. The command decoder determines a first command matched with the received first signal, and transmits the first command to at least part of the memory units in response to the received first signal. The at least part of the memory units execute an operation matched with the first command after receiving the first command.

[0006] In the present application, since the clock frequency of the first clock signal is the same as the clock frequency of the second clock signal in the control circuit for triggering the output of the first signal, the control circuit transmits a high level (digital signal "1") to the first recovered clock receiver under the triggering of the second clock signal, and the first recovered clock receiver also receives the corresponding high level (digital signal "1") under the triggering of the first clock signal with the same clock frequency; or the control circuit transmits a low level (digital signal "0") to the first recovered clock receiver under the triggering of the second clock signal, and the first recovered clock receiver also receives the corresponding low level (digital signal "0") under the triggering of the first clock signal with the same clock frequency.

[0007] The first command can be a write command, a read command, a chip select command, an activate command, a precharge command, a refresh command, a low power operation command, or the like sent by the control circuit to the memory. In this way, the first signal sent by the control circuit to the memory can also replace the address lines (A0-A17, BG[1:0], BA[1:0], etc.), the chip select line CS, the activate line ACT_n, and the like. In combination with the foregoing omitted clock lines CK_t / c and clock enable lines CKE, the number of lines on the circuit board is greatly reduced, the utilization rate of the first line is improved, and the board-level space resources and bandwidth of the circuit board are saved.

[0008] In some possible implementations, the first command can act on different storage units in different cases, and the first command can further include a first address. At least part of the storage units that need to execute the first command can be specified according to the first address, so that the operation matched with the first command is executed by the specified at least part of the storage units. Specifically, the memory further includes a multiplexer. A command decoder is configured to determine at least part of the storage units indicated by the first command according to the first command. The command decoder is further configured to send the first command to the at least part of the storage units through the multiplexer.

[0009] In some possible implementations, the memory further includes a data interface. In a case where the first command is a write command, the at least part of the storage units are configured to receive write data through the data interface and the multiplexer. Alternatively, in a case where the first command is a read command, the at least part of the storage units are further configured to read out read data through the multiplexer and the data interface.

[0010] On this basis, the number of data interfaces is multiple, and the memory further includes a data transmission unit.

[0011] In a case where the first command is a write command, the data transmission unit is configured to receive, under the triggering of a third clock signal, multiple groups of first data sent by the control circuit through the multiple data interfaces in parallel, convert the multiple groups of first data in parallel into write data in series, and send the write data in series to the at least part of the storage units through the multiplexer. The clock frequency of the third clock signal is the same as that of a fourth clock signal used to trigger the output of the multiple groups of first data in the control circuit. Because the clock frequency of the third clock signal is the same as that of the fourth clock signal, under the triggering of the fourth clock signal, the control circuit sends a high level (digital signal "1") to the data transmission unit, and under the triggering of the third clock signal with the same clock frequency, the data transmission unit also receives a corresponding high level (digital signal "1"). Alternatively, under the triggering of the fourth clock signal, the data transmission unit sends a low level (digital signal "0") to the data transmission unit, and under the triggering of the third clock signal with the same clock frequency, the data transmission unit also receives a corresponding low level (digital signal "0").

[0012] For example, the first data is transmitted to the data interface through the second wires, the number of the second wires is 16, and each 16-bit write data constitutes an effective write data. After the first recovery clock receiver receives the first signal for indicating the write command, the data transmission unit receives 16 first data in parallel through the 16 second wires. The data transmission unit converts the 16 first data in parallel into 16-bit write data in series, and writes the 16-bit write data in series as the effective write data into the at least part of the storage units.

[0013] Alternatively, the first command is a read command; the data transmission unit is further configured to receive serial read data sent by the at least part of the storage units through the multiplexer, convert the serial read data into a plurality of groups of second data in parallel, and input the plurality of groups of second data in parallel to the control circuit through the plurality of data interfaces under the triggering of the fifth clock signal; the clock frequency of the fifth clock signal is the same as the clock frequency of a sixth clock signal for triggering the control circuit to receive the plurality of groups of second data. Since the clock frequency of the fifth clock signal is the same as the clock frequency of the sixth clock signal, under the triggering of the fifth clock signal, the data transmission unit sends a high level (digital signal "1") to the control circuit, and the control circuit also receives the corresponding high level (digital signal "1") under the triggering of the sixth clock signal with the same clock frequency; or under the triggering of the fifth clock signal, the data transmission unit sends a low level (digital signal "0") to the control circuit, and the control circuit also receives the corresponding low level (digital signal "0") under the triggering of the sixth clock signal with the same clock frequency.

[0014] For example, the data interface outputs the second data through the second wires, the number of the second wires is 16, and each 16-bit read data constitutes an effective read data. After the first recovery clock receiver receives the first signal for indicating the read command, the at least part of the storage units serially sends 16 read data to the data transmission unit through the multiplexer. The data transmission unit converts the 16 read data in series into 16 second data in parallel, and outputs the 16 second data in parallel through the 16 second wires.

[0015] In some possible implementation manners, the clock frequency of the third clock signal is the same as the clock frequency of the fifth clock signal. In this way, the frequency of writing the write data into the at least part of the storage units is the same as the frequency of reading the read data from the at least part of the storage units.

[0016] In some possible implementation manners, the recovery clock receiver includes a first clock generation circuit, and the first clock generation circuit is configured to generate the first clock signal, the third clock signal, and the fifth clock signal. On this basis, the control circuit includes a third clock generation circuit, and the third clock generation circuit is configured to generate the second clock signal.

[0017] The application can generate the first clock signal by the first clock generation circuit and generate the second clock signal by the third clock generation circuit, so that the second clock signal for triggering the first signal output does not need to be provided to the control circuit by the external circuit through the wire, and the first clock signal for triggering the first signal does not need to be provided to the memory by the external circuit through the wire. Thus, the clock line CK_t / c and the clock enable line CKE are omitted, the number of wires on the circuit board is reduced, and the board-level space resources and bandwidth of the circuit board are saved.

[0018] When the first command is a write command, the first clock generation circuit generates the third clock signal, so that the data line receiving clock TDQS[2:0]t / c can be saved; when the first command is a read command, the first clock generation circuit generates the fifth clock signal, so that the data line sending clock DQS[2:0]t / c can be saved. Thus, the number of wires on the circuit board is greatly reduced, the utilization rate of the first wire and the second wire is improved, and the board-level space resources and bandwidth of the circuit board are saved.

[0019] In some possible implementation manners, in the case that the first command is a first chip select command, the memory is configured to start working under the control of the first chip select command and keep a non-working state under the control of a second chip select command; the first chip select command is different from the second chip select command. Assuming that the memory includes a first memory and a second memory, the first memory and the second memory are both in a non-working state. If the control circuit needs to interact with the first memory, the first chip select command can be sent to the first memory and the second memory, and the first chip select command can be used as a chip select enable of the first memory, so that the first memory starts working. When the first memory receives the second chip select command different from the first chip select command, the first memory is still in the non-working state. For the second memory, even if the first chip select command is received, the second memory is still in the non-working state. In this way, the chip select line CS can also be saved, the number of wires on the circuit board is reduced, the utilization rate of the first wire is improved, and the board-level space resources and bandwidth of the circuit board are saved.

[0020] In some possible implementation manners, the number of first command interfaces is multiple. The recovery clock receiver is configured to receive, in parallel through the multiple first command interfaces, multiple groups of first sub-signals sent by the control circuit under the triggering of the first clock signal, so that the transmission efficiency of the first signal can be improved. The recovery clock receiver is further configured to convert the multiple groups of first sub-signals transmitted in parallel into a serial first signal. Taking the first command as a write command or a read command as an example, the number of first wires and the number of first commands are multiple, so that the first signal is input into the memory before write data corresponding to the first signal, or the first signal is input into the memory first, and read data corresponding to the first signal is sent from the memory unit to the control circuit.

[0021] In some possible implementation manners, the memory further includes a recovery clock generator and a second command interface. The at least part of the storage unit is further configured to send a second command to the command decoder. The command decoder is further configured to, in response to the received second command, determine a second signal matched with the second command, and send the second signal to the recovery clock generator. The recovery clock generator is configured to send the second signal to the control circuit through the second command interface under triggering of a seventh clock signal, and a clock frequency of the seventh clock signal is the same as a clock frequency of an eighth clock signal used for triggering the control circuit to receive the second signal.

[0022] For example, the second command includes at least one of an alert command and a data inversion command. The alert line ALERT_n and the data inversion line DMI are omitted, the number of wirings on the circuit board is reduced, the utilization rates of the first wiring, the second wiring, and the third wiring are improved, and the board-level space resources and bandwidth of the circuit board are saved.

[0023] In some possible implementation manners, the number of the second command interfaces is multiple. The recovery clock generator is configured to convert the serial second signal into multiple groups of parallel second sub-signals, so as to improve the transmission rate of the second signal, and avoid that the data sent by the storage unit to the control circuit is output earlier than the second signal. The recovery clock generator is further configured to send the multiple groups of second sub-signals to the control circuit in parallel through the multiple second command interfaces under triggering of the seventh clock signal.

[0024] In some possible implementation manners, the recovery clock generator includes a second clock generation circuit, and the second clock generation circuit is configured to generate the seventh clock signal. On this basis, the control circuit includes a fourth clock generation circuit, and the fourth clock generation circuit generates the eighth clock signal.

[0025] Since the memory can generate the seventh clock signal and the control circuit can generate the eighth clock signal, the seventh clock signal used for triggering the second signal output does not need to be provided to the memory by an external circuit through a wiring, and the eighth clock signal used for receiving the second signal does not need to be provided to the control circuit by the external circuit through a wiring. Therefore, the clock line CK_t / c and the clock enable line CKE can be omitted, the number of wirings on the circuit board is reduced, and the board-level space resources and bandwidth of the circuit board are saved.

[0026] In a second aspect, the present application provides a circuit board, which includes the control circuit and the memory in the first aspect. The control circuit is configured to send a first signal to the memory under triggering of a second clock signal.

[0027] In the present application, since the clock frequency of the first clock signal received by the first recovery clock receiver is the same as the clock frequency of the second clock signal in the control circuit for triggering the output of the first signal, the control circuit sends a high level (digital signal "1") to the first recovery clock receiver under the triggering of the second clock signal, and the first recovery clock receiver also receives the corresponding high level (digital signal "1") under the triggering of the first clock signal with the same clock frequency; or the control circuit sends a low level (digital signal "0") to the first recovery clock receiver under the triggering of the second clock signal, and the first recovery clock receiver also receives the corresponding low level (digital signal "0") under the triggering of the first clock signal with the same clock frequency.

[0028] The first command can be a write command, a read command, a chip select command, an activate command, a precharge command, a refresh command, a low power operation command, and the like sent by the control circuit to the memory. In this way, the first signal sent by the control circuit to the memory can also replace the address lines (A0-A17, BG[1:0], BA[1:0], and the like), the chip select line CS, the activate line ACT_n, and the like. In combination with the foregoing omitted clock line CK_t / c and clock enable line CKE, the number of lines on the circuit board is greatly reduced, the utilization rate of the first line is improved, and the board-level space resources and bandwidth of the circuit board are saved.

[0029] In a third aspect, the present application provides an electronic device, which comprises one or more computer programs and the circuit board of the second aspect; the one or more computer programs are stored in the memory on the circuit board.

[0030] The third aspect and any one of the implementation manners of the third aspect correspond to the first aspect and any one of the implementation manners of the first aspect respectively. The technical effects corresponding to the third aspect and any one of the implementation manners of the third aspect can be referred to the technical effects corresponding to the first aspect and any one of the implementation manners of the first aspect, which will not be described here.

[0031] In a fourth aspect, the present application provides a control method of a memory, which comprises a first command interface. The control method of the memory comprises: receiving a first signal sent by a control circuit under the triggering of a first clock signal through the first command interface; the clock frequency of the first clock signal is the same as the clock frequency of a second clock signal in the control circuit for triggering the output of the first signal. In response to the received first signal, determining a first command matched with the first signal. Performing an operation matched with the first command.

[0032] In some possible implementation manners, the memory further includes a data interface. The first command is a write command; and the operation matched with the first command includes: receiving write data through the data interface; or the first command is a read command; and the operation matched with the first command includes: reading read data through the data interface.

[0033] In some possible implementation manners, the number of data interfaces is multiple, the first command is a write command; and the receiving write data through the data interface includes: receiving multiple groups of first data sent by the control circuit in parallel through the multiple data interfaces under the triggering of a third clock signal; the clock frequency of the third clock signal is the same as the clock frequency of a fourth clock signal used for triggering the output of the multiple groups of first data in the control circuit; and the multiple groups of first data in parallel are converted into serial write data; and the serial write data is written.

[0034] In some possible implementation manners, the number of data interfaces is multiple, the first command is a read command; and the reading read data through the data interface includes: converting serial read data into multiple groups of second data in parallel; and inputting the multiple groups of second data in parallel to the control circuit through the multiple data interfaces under the triggering of a fifth clock signal; the clock frequency of the fifth clock signal is the same as the clock frequency of a sixth clock signal used for triggering the control circuit to receive the multiple groups of second data.

[0035] In some possible implementation manners, the first command is a first chip select command; and the operation matched with the first command includes: starting to work under the control of the first chip select command and keeping a non-working state under the control of a second chip select command; and the first chip select command is different from the second chip select command.

[0036] In some possible implementation manners, the number of first command interfaces is multiple; and the receiving the first signal sent by the control circuit through the first command interface under the triggering of a first clock signal includes: receiving multiple groups of first sub-signals sent by the control circuit in parallel through the multiple first command interfaces under the triggering of the first clock signal; and converting the multiple groups of first sub-signals transmitted in parallel into serial first signals.

[0037] In some possible implementation manners, the memory further includes a second command interface. A second command is generated, and a second signal matched with the second command is determined; and the second signal is sent to the control circuit through the second command interface under the triggering of a seventh clock signal; and the clock frequency of the seventh clock signal is the same as the clock frequency of an eighth clock signal used for triggering the control circuit to receive the second signal.

[0038] In some possible implementation manners, the number of the second command interfaces is multiple. The second signal is sent to the control circuit through the second command interfaces under triggering of the seventh clock signal, including: converting the serial second signal into parallel multiple groups of second sub-signals; and the multiple groups of second sub-signals are sent to the control circuit in parallel through the multiple second command interfaces under triggering of the seventh clock signal.

[0039] The fourth aspect and any one of the implementation manners of the fourth aspect correspond to the first aspect and any one of the implementation manners of the first aspect respectively. For details of the technical effects of the fourth aspect and any one of the implementation manners of the fourth aspect, refer to the technical effects of the first aspect and any one of the implementation manners of the first aspect, which will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1a An interaction diagram of a control circuit and a memory provided by an embodiment of the present application;

[0041] Figure 1b A connection relationship diagram of a memory and various wirings provided by the related art;

[0042] Figure 2a A connection relationship diagram of a memory and a control circuit provided by an embodiment of the present application;

[0043] Figure 2b Another connection relationship diagram of a memory and a control circuit provided by an embodiment of the present application;

[0044] Figure 2c Still another connection relationship diagram of a memory and a control circuit provided by an embodiment of the present application;

[0045] Figure 3a A connection relationship diagram of a memory and a control circuit provided by an embodiment of the present application;

[0046] Figure 3b Another connection relationship diagram of a memory and a control circuit provided by an embodiment of the present application;

[0047] Figure 4a A timing diagram of writing write data into a storage unit provided by an embodiment of the present application;

[0048] Figure 4b A timing diagram of reading read data from a storage unit provided by an embodiment of the present application;

[0049] Figure 5 An interaction diagram of a second recovery clock generator and multiple memories provided by an embodiment of the present application;

[0050] Figure 6a Still another connection relationship diagram of a memory and a control circuit provided by an embodiment of the present application;

[0051] Figure 6b Another connection relationship diagram of a memory and a control circuit provided by an embodiment of the present application;

[0052] Figure 7 A working flowchart of a memory provided by an embodiment of the present application;

[0053] Figure 8 Another working flowchart of a memory provided by an embodiment of the present application.

[0054] Reference signs:

[0055] 10 - memory; 11 - memory cell; 12 - first recovery clock receiver; 13 - command decoder; 14 - multiplexer; 15 - data transfer unit; 16 - second recovery clock generator; 20 - control circuit; 21 - first recovery clock generator; 22 - data transceiver; 23 - second recovery clock receiver. DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0057] The term "and / or" in the present application is merely used to describe an association relationship of associated objects, and means that three relationships can exist, for example, A and / or B can mean that three cases of A alone, A and B together, and B alone exist.

[0058] The terms "first" and "second" and the like in the specification and claims of the embodiments of the present application are used to distinguish different objects, and are not used to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, and are not used to describe a specific order of the target objects.

[0059] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or advantageous than other embodiments or design schemes. Rather, the use of the words "exemplary" or "for example" is intended to present relevant concepts in a specific way.

[0060] In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified. For example, a plurality of processing units refers to two or more processing units; a plurality of systems refers to two or more systems.

[0061] The electronic device can be a mobile phone, a computer, a tablet computer, a personal digital assistant (PDA), a smart wearable device, a smart home device, or the like, which has a storage function, and the embodiments of the present application are not limited thereto. For the convenience of description, a mobile phone is taken as an example in the following description.

[0062] As shown in the example, Figure 1a As an indispensable part of the mobile phone, the memory can be used to store computer executable program code, which can include instructions. The control circuit executes the instructions stored in the memory to perform various functional applications and data processing of the mobile phone. In some possible implementations, the memory can also save instructions that have been used by the control circuit or are used repeatedly. If the control circuit needs to use the instructions again, it can be directly called from the memory, avoiding repeated access and reducing the waiting time of the control circuit, thereby improving the working efficiency of the mobile phone.

[0063] The example illustrates the application of the memory in the mobile phone through the interaction process between the memory and the control circuit. Of course, the memory can also interact with other components in the mobile phone to realize other functions of the mobile phone, and the embodiments of the present application are not limited thereto.

[0064] In addition, the above-mentioned control circuit can be a system on chip (SoC) or a central processing unit (CPU), an accelerator, or the like, which has the access permission of the memory, and the embodiments of the present application are not limited thereto.

[0065] The above-mentioned memory can be any memory with a storage function, and the embodiments of the present application are not limited thereto. For example, a dual data rate SDRAM (DDR), a low power double data rate SDRAM (LPDDR), a high bandwidth memory (HBM), or the like.

[0066] In the above examples, the process in which the control circuit saves the instruction that the control circuit has just used or circulates to use, can be the process of writing write data to the memory. The process in which the control circuit calls the instruction from the memory can be the process of reading data from the memory. The operation of writing write data to the memory and reading read data from the memory can be completed by the control circuit through the address line, the control line, and the data line.

[0067] As shown in Figure 1b In the related art, the memory 10 includes a plurality of storage units 11. Taking DDR4 as an example, the control circuit integrated on the circuit board can send address information and commands through the address line (A0-A17, BG[1:0], BA[1:0], etc.) and the address interface, to send a write command or a read command to at least part of the storage units 11 specified in the memory 10. Under the control of the write command, the control circuit can write write data to the specified at least part of the storage units 11 through the data line (DQ[15:0]) and the data interface; or under the control of the read command, the control circuit can read read data from the specified at least part of the storage units 11 through the data line (DQ[15:0]) and the data interface.

[0068] Those skilled in the art should know that the address line (A0-A17, BG[1:0], BA[1:0], etc.) corresponds to the address interface one by one, and the data line (DQ[15:0]) corresponds to the data interface one by one. For example, the data line (DQ[15:0]) includes 16 data lines (DQ[15:0]), so the number of data interfaces is also 16, and the 16 data lines (DQ[15:0]) correspond to the 16 data interfaces one by one and are electrically connected.

[0069] On the basis of the above, the circuit board further integrates a chip selection line CS, a clock line CK_t / c, a clock enable line CKE, a data line transmission clock DQS[2:0]t / c, a data line reception clock TDQS[2:0]t / c, an activation line ACT_n, a data verification line PAR, a data inversion line DMI, an alarm line ALERT_n, and the like.

[0070] Taking the chip selection line CS as an example, as shown in Figure 1a The number of memories 10 in the mobile phone can be multiple, and when the control circuit interacts with one of the memories 10, an enable signal needs to be transmitted to one or more memories 10 through the chip selection line CS to select one or more memories 10 to interact with the control circuit.

[0071] Taking the clock line CK_t / c and the clock enable line CKE as an example, the first clock circuit can generate a clock enable signal and transmit the clock enable signal to the second clock circuit through the clock enable line CKE to trigger the second clock circuit to work. Under the triggering of the clock enable signal, the second clock circuit can generate a command clock signal and transmit the command clock signal to the command generation circuit through the clock line CK_t / c. Under the triggering of the command clock signal, the command generation circuit transmits an address and a command to the specified at least part of the storage units 11 through the address lines (A0-A17, BG[1:0], BA[1:0], etc.).

[0072] All the above-mentioned wirings are independently integrated in the circuit board, and each wiring independently occupies the space resources of the circuit board. Especially, with the increase of the number of the storage units 10, the number of the wirings also increases exponentially, resulting in the increase of the board-level space resources of the circuit board.

[0073] For this problem, the inventor finds that the utilization rate of part of the above-mentioned wirings is very low, but still occupies the space resources of the circuit board and the bandwidth. Based on this, the present application changes the internal modules of the storage units 10 and the connection relationship to save part of the wirings with low utilization rate, thereby saving the board-level space resources of the circuit board and the bandwidth.

[0074] As shown in Figure 2a The storage unit 10 includes a recovery clock receiver 12, a command decoder 13, a plurality of storage units 11, and a first command interface.

[0075] The recovery clock receiver is configured to receive the first signal sent by the control circuit 20 through the first command interface under the triggering of the first clock signal, and send the first signal to the command decoder 13. The clock frequency of the first clock signal is the same as the clock frequency of the second clock signal in the control circuit 20 for triggering the output of the first signal. In order to distinguish the recovery clock receiver of the storage unit 10 from the recovery clock receiver of the control circuit 20 below, the recovery clock receiver of the storage unit 10 can be a first recovery clock receiver 12, and the recovery clock receiver of the control circuit 20 below can be a second recovery clock receiver.

[0076] The command decoder 13 is configured to determine a first command matched with the received first signal and send the first command to at least part of the storage units 11 in response to the received first signal.

[0077] The at least part of the storage units 11 is configured to perform an operation matched with the first command.

[0078] The above-mentioned storage unit 10 receives the first signal and performs the operation matched with the first command can be realized by the following process:

[0079] The first recovery clock receiver 12 can receive the first signal in the form of a digital signal through the first command interface triggered by the first clock signal. Since the clock frequency of the first clock signal of the first recovery clock receiver 12 is the same as the clock frequency of the second clock signal used to trigger the output of the first signal in the control circuit 20, the control circuit 20 sends a high level (digital signal "1") to the first recovery clock receiver 12 triggered by the second clock signal, and the first recovery clock receiver 12 also receives the corresponding high level (digital signal "1") triggered by the first clock signal with the same clock frequency; or the control circuit 20 sends a low level (digital signal "0") to the first recovery clock receiver 12 triggered by the second clock signal, and the first recovery clock receiver 12 also receives the corresponding low level (digital signal "0") triggered by the first clock signal with the same clock frequency.

[0080] In some possible implementations, as shown in Figure 2b The control circuit 20 can include a first recovery clock generator 21. The second clock signal can be generated by the first recovery clock generator 21, and the first recovery clock generator 21 sends the first signal to the first recovery clock receiver 12 triggered by the second clock signal.

[0081] In some possible implementations, the first recovery clock receiver 12 can include a first clock generation circuit, and the first clock generation circuit can generate the first clock signal. The first recovery clock generator 21 can include a third clock generation circuit, and the third clock generation circuit can generate the second clock signal.

[0082] Since the first clock generation circuit can generate the first clock signal and the third clock generation circuit can generate the second clock signal, the second clock signal used to trigger the output of the first signal does not need to be provided to the control circuit 20 by an external circuit through a wire, and the first clock signal used to trigger the reception of the first signal does not need to be provided to the memory 10 by an external circuit through a wire. Thus, the clock line CK_t / c and the clock enable line CKE can be omitted, the number of wires on the circuit board can be reduced, and the board-level space resources and bandwidth of the circuit board can be saved.

[0083] In some possible implementations, the circuit board can further include a first wire connecting the first recovery clock generator 21 and the first recovery clock receiver 12. The first wire and the first command interface can be one-to-one correspondence, and the number of the first wire and the first command interface can be multiple or one. The first recovery clock generator 21 can send the first signal to the first recovery clock receiver 12 through one first wire and one first command interface, or the first recovery clock generator 21 can send the first signal to the first recovery clock receiver 12 through multiple first wires and multiple first command interfaces.

[0084] Suppose the total number of bits of the first signal sent by the first recovery clock generator 21 to the first recovery clock receiver 12 is denoted as [tn-1:0], which is tn bits in total. As shown in FIG. 1, if the number of first traces and first command interfaces is one, the first trace and the first command interface are used to transmit the first signal of tn bits. Figure 2b As shown in FIG. 2, if the number of first traces and first command interfaces is two, each first trace and each first command interface is used to transmit a first sub-signal of tn / 2 bits, and the first recovery clock receiver 12 converts the two parallel first sub-signals into a serial first signal after receiving the two first sub-signals. Here, n represents that each n-bit digital signal corresponds to one first command, and t represents that the first command is repeated t times. Figure 2c

[0085] For example, the first recovery clock generator 21 can send the first signal 1001 to the first recovery clock receiver 12 through one first trace and one first command interface, and the first signal received by the first recovery clock receiver 12 is also 1001.

[0086] For another example, the first recovery clock generator 21 can send a first sub-signal to the first recovery clock receiver 12 through two first traces and two first command interfaces. One of the first traces is a high bit line, and the other is a low bit line. The first recovery clock generator 21 can send the first sub-signal to the first recovery clock receiver 12 through the low bit line, the high bit line, and the two first command interfaces at the same time. The digital signal 1 transmitted by the low bit line and the digital signal 0 transmitted by the high bit line can be sent to the first recovery clock receiver 12 first, and then the digital signal 0 transmitted by the low bit line and the digital signal 1 transmitted by the high bit line are sent to the first recovery clock receiver 12. The first recovery clock receiver 12 converts the two parallel first sub-signals into a serial first signal, and the first signal can be 1001.

[0087] Optionally, assuming that the first command is a write command or a read command, the number of first traces and the number of first commands can be multiple, so as to improve the transmission rate of the first signal, so that the first signal is input to the memory 10 before the write data corresponding to the first signal, or so that the first signal is input to the memory 10, and then the read data corresponding to the first signal is sent to the control circuit 20 from the memory unit 11.

[0088] Then, the first recovery clock receiver 12 can also send the first signal to the command decoder 13. The command decoder 13 can match the received first signal with a pre-stored command library to determine the first command matched with the first signal.

[0089] ​Here, the pre-stored command library may include a correspondence between multiple digital signals and commands. For example, digital signal 1010 corresponds to a read command, and digital signal 0101 corresponds to a write command. This example shows that every 4 digital signals correspond to one first command. In other possible implementations, the number of bits in the digital signal corresponding to a first command may be different, and this application embodiment does not limit this.

[0090] Next, after the command decoder 13 determines the first command that matches the first signal, it can also send the first command to at least a portion of the storage units 11. At least a portion of the storage units 11 can then perform the operation that matches the first command.

[0091] In some possible implementations, the first command can act on different memory units 11 under different circumstances. The first command may also include a first address, which can specify at least a portion of the memory units 11 that need to execute the first command, so that the specified at least a portion of the memory units 11 can perform the operation matching the first command.

[0092] like Figure 2c As shown, the memory 10 may further include a multiplexer 14, which can be used to apply the first command to different memory cells 11. One end of the multiplexer 14 is electrically connected to the command decoder 13, and the other end is electrically connected to the memory cells 11. After the command decoder 13 determines the specified at least some memory cells 11 according to the first command, it can also send the first command to the specified at least some memory cells 11 through the multiplexer 14.

[0093] For example, multiple storage cells 11 are arranged in an array, and the array of storage cells 11 is divided into multiple rows. Assuming that the first command is applied to the first row of storage cells 11, the command decoder 13 can send the first command to the first row of storage cells 11 through the multiplexer 14, and the first row of storage cells 11 performs the operation matching the first command.

[0094] In some possible implementations, the embodiments of this application do not limit the specific first command, as long as the first command is sent from the control circuit 20 to the memory 10.

[0095] For example, the first command can be a write command, a read command, a chip select command, an activate command, a precharge command, a refresh command, a low power operation command, and the like sent by the control circuit 20 to the memory 10. In this way, the first wire in the present application which is electrically connected with the first command can also replace the address line (A0-A17, BG[1:0], BA[1:0], and the like), the chip select line CS, the activate line ACT_n, and the like. In combination with the aforementioned omitted clock line CK_t / c and clock enable line CKE, the number of wires on the circuit board is greatly reduced, the utilization rate of the first wire is improved, and the board-level space resources and bandwidth of the circuit board are saved.

[0096] As shown in Figure 3a , taking the write command and the read command as examples of the first command, the memory 10 can further include a data interface. The control circuit 20 can write write data to at least part of the storage units 11 through the data interface and the multiplexer 14, or at least part of the storage units 11 can read read data out to the control circuit 20 through the multiplexer 14 and the data interface.

[0097] In some possible implementation manners, as shown in Figure 3a , the control circuit 20 further includes a data transceiver 22. The write data can be written to at least part of the storage units 11 by the data transceiver 22 of the control circuit 20, or the read data read out by at least part of the storage units 11 can be received.

[0098] On this basis, as shown in Figure 3b , the number of data interfaces can be multiple, and the circuit board can further include multiple second wires connecting the data transceiver 22 and the memory 10. The second wires and the data interfaces correspond one-to-one, and the data transceiver 22 and the memory 10 can transmit write data and read data through the multiple second wires and the multiple data interfaces.

[0099] Since the multiple second wires and the multiple data interfaces are parallel transmission of data, the read data read out from at least part of the storage units 11 or the write data written to at least part of the storage units 11 are serial transmission. Therefore, the memory 10 can further include a data transmission unit 15. The data transmission unit 15 can convert serial data into parallel data, or convert parallel data into serial data.

[0100] As shown in Figure 3bAs shown, if the first command is a write command, the data transmission unit 15 can, under the trigger of the third clock signal, receive multiple sets of first data sent by the data transceiver 22 in parallel through multiple data interfaces, convert the parallel sets of first data into serial write data, and write the serial write data to at least a portion of the storage units 11 through the multiplexer 14. The clock frequency of the third clock signal can be the same as the clock frequency of the fourth clock signal in the data transceiver 22 used to trigger the output of multiple sets of first data.

[0101] For example, such as Figure 4a As shown, assuming there are 16 second traces, each 16 bits of write data constitutes a valid write data. After the first recovery clock generator 21 sends a first signal indicating a write command to the memory 10, the data transceiver 22 sends 16 first data in parallel through the 16 second traces. The data transmission unit 15 converts the 16 parallel first data into serial 16-bit write data, and the serial 16-bit write data is written as valid write data into at least a portion of the memory cells 11.

[0102] The 16 first data transmitted in parallel through the 16 second lines can be sorted in order from the least significant bit to the most significant bit, so that the data transmission unit 15 can convert the received 16-bit parallel first data into serial 16-bit write data.

[0103] Since the clock frequency of the third clock signal is the same as that of the fourth clock signal, when the data transceiver 22 sends a high level (digital signal "1") to the data transmission unit 15 under the trigger of the fourth clock signal, the data transmission unit 15 will also receive the corresponding high level (digital signal "1") under the trigger of the third clock signal at the same clock frequency; or, when the data transceiver 22 sends a low level (digital signal "0") to the data transmission unit 15 under the trigger of the fourth clock signal, the data transmission unit 15 will also receive the corresponding low level (digital signal "0") under the trigger of the third clock signal at the same clock frequency.

[0104] like Figure 3b As shown, if the first command is a read command, the data transmission unit 15 can also receive at least a portion of the serial read data sent by the storage unit 11 through the multiplexer 14, convert the serial read data into multiple sets of parallel second data, and, triggered by the fifth clock signal, input the multiple sets of second data in parallel to the data transceiver 22 through multiple data interfaces. The clock frequency of the fifth clock signal can be the same as the clock frequency of the sixth clock signal used to trigger the data transceiver 22 to receive the multiple sets of second data.

[0105] For example, such as Figure 4bAs shown, assuming the number of second traces is 16, and each 16 bits of read data constitutes a valid read data. After the first recovery clock generator 21 sends the first signal for indicating the read command to the memory 10, at least part of the storage units 11 serially send 16 read data to the data transfer unit 15 through the multiplexer 14. The data transfer unit 15 converts the serial 16 read data into parallel 16 second data, and sends the parallel 16 second data to the data transceiver 22 through the 16 second traces.

[0106] In addition, since the clock frequency of the fifth clock signal is the same as the clock frequency of the sixth clock signal, under the triggering of the fifth clock signal, the data transfer unit 15 sends a high level (digital signal "1") to the data transceiver 22 every time, and under the triggering of the sixth clock signal with the same clock frequency, the data transceiver 22 also receives the corresponding high level (digital signal "1"); or under the triggering of the fifth clock signal, the data transfer unit 15 sends a low level (digital signal "0") to the data transceiver 22 every time, and under the triggering of the sixth clock signal with the same clock frequency, the data transceiver 22 also receives the corresponding low level (digital signal "0").

[0107] In some possible implementation manners, the clock frequency of the third clock signal can be the same as the clock frequency of the fifth clock signal, in which case, the frequency of writing the write data to at least part of the storage units 11 is the same as the frequency of reading the read data from at least part of the storage units 11. Of course, the clock frequency of the third clock signal can also be different from the clock frequency of the fifth clock signal, which is not limited in the embodiments of the present application.

[0108] In some possible implementation manners, the foregoing first clock generation circuit can also generate the third clock signal and the fifth clock signal required by the data transceiver 22. In this way, when the first command is a write command, the data line receiving clock TDQS[2:0]t / c can be saved; when the first command is a read command, the data line sending clock DQS[2:0]t / c can be saved, greatly reducing the number of traces on the circuit board, improving the utilization rate of the first traces and the second traces, and saving the board-level space resources and bandwidth of the circuit board.

[0109] As Figure 5As shown, taking the first command as an example of the first chip select command, it is assumed that the memory 10 includes a first memory and a second memory, and both the first memory and the second memory are in a non-working state. If the control circuit 20 needs to interact with the first memory, the first chip select command can be sent to the first memory and the second memory, and the first chip select command can be used as the chip select enable of the first memory, so that the first memory starts to work. When the first memory receives a second chip select command different from the first chip select command, the first memory is still in a non-working state. As for the second memory, even if the first chip select command is received, the second memory is still in a non-working state. In this way, the chip select line CS can also be saved, the number of lines on the circuit board is reduced, the utilization rate of the first line is improved, the board-level space resources and bandwidth of the circuit board are saved.

[0110] For example, the first chip select command is 0000, and the second chip select command is 1111. When the first command is 0000, the first memory starts to work after receiving the first command. When the first command is 1111, the first memory is still in a non-working state after receiving the first command.

[0111] Of course, the control circuit 20 can also send the first chip select command to the first memory in a targeted manner, rather than sending the first chip select command to all first memories and second memories, and the embodiments of the present application do not limit this. In some embodiments, as shown in Figure 6a and Figure 6b As shown, at least part of the storage unit 11 can feed back the second command to the control circuit 20 based on the current working condition. Based on this, the memory 10 can also include a second command interface. In order to distinguish from the first recovery clock generator 21 of the control circuit 20, the recovery clock generator of the memory 10 is described below as a second recovery clock generator 16.

[0112] At least part of the storage unit 11 is also used to send the second command to the command decoder 13.

[0113] The command decoder 13 is also used to determine the second signal matched with the second command in response to the received second command, and send the second signal to the second recovery clock generator 16.

[0114] The second recovery clock generator 16 is used to send the second signal to the control circuit 20 through the second command interface under the triggering of a seventh clock signal. The clock frequency of the seventh clock signal is the same as the clock frequency of an eighth clock signal used to trigger the control circuit 20 to receive the second signal. The operation of at least part of the storage unit 11 of the above memory 10 sending the second command to the control circuit 20 can be realized by the following process:

[0115] The at least partially storage unit 11 can send the second command to the command decoder 13 through the multiplexer 14.

[0116] In some possible implementation manners, the second command is not limited in the embodiment of the application, and any command that can be sent by the storage unit 11 to the control circuit 20 can be used as the second command.

[0117] For example, the second command includes at least one of an alarm command and a data inversion command. The alarm line ALERT_n and the data inversion line DMI are omitted, the number of lines on the circuit board is reduced, the utilization rates of the first line, the second line and the third line are improved, and the board-level space resources and bandwidth of the circuit board are saved.

[0118] Then, the command decoder 13 can match the received second command with a pre-stored command library to determine a second signal matched with the second command, and send the second signal to the second recovery clock generator 16.

[0119] For example, the second command is an error reporting command, the error reporting command corresponds to the digital signal 0001, and the second signal can be 0001.

[0120] Then, the second recovery clock generator 16 can send the second signal to the second recovery clock receiver 23 of the control circuit 20 through the second command interface under the triggering of the seventh clock signal. The second recovery clock receiver 23 can receive the second signal under the triggering of the eighth clock signal.

[0121] Since the clock frequency of the seventh clock signal is the same as the clock frequency of the eighth clock signal used for triggering the second recovery clock receiver 23 to receive the second signal, under the triggering of the seventh clock signal, the second recovery clock generator 16 outputs a high level (digital signal “1”) every time, and the second recovery clock receiver 23 also receives a corresponding high level (digital signal “1”) under the triggering of the eighth clock signal at the same clock frequency; or under the triggering of the seventh clock signal, the second recovery clock generator 16 outputs a low level (digital signal “0”) every time, and the second recovery clock receiver 23 also receives a corresponding low level (digital signal “0”) under the triggering of the eighth clock signal at the same clock frequency.

[0122] In some possible implementation manners, the second recovery clock generator 16 can include a second clock generation circuit, and the second clock generation circuit can generate the seventh clock signal. The second recovery clock receiver 23 can include a fourth clock generation circuit, and the fourth clock generation circuit can generate the eighth clock signal.

[0123] Since the second clock generating circuit can generate the seventh clock signal, and the fourth clock generating circuit can generate the eighth clock signal, the seventh clock signal for triggering the second signal output does not need to be provided to the memory 10 by the external circuit through the wire, and the eighth clock signal for triggering the second signal does not need to be provided to the control circuit 20 by the external circuit through the wire. Thus, the clock line CK_t / c and the clock enable line CKE can be omitted, the number of wires on the circuit board is reduced, and the board-level space resources and bandwidth of the circuit board are saved.

[0124] In some possible implementations, the circuit board can further include third wires connecting the second recovery clock generator 16 and the second recovery clock receiver 23. The third wires and the second command interfaces are in one-to-one correspondence, and the number of the third wires and the second command interfaces can be multiple or one. The second recovery clock generator 16 can send the second signal to the second recovery clock receiver 23 through one third wire and one second command interface, or the second recovery clock generator 16 can send the second signal to the second recovery clock receiver 23 through multiple third wires and multiple second command interfaces.

[0125] Suppose the total number of bits of the second signal sent by the second recovery clock generator 16 to the second recovery clock receiver 23 is [tn-1:0], that is, tn bits. As shown in FIG. 6, if the number of the third wires and the second command interfaces is one, the third wire and the second command interface are used to transmit the tn-bit second signal. Figure 6a As shown in FIG. 7, if the number of the third wires and the second command interfaces is two, the second recovery clock generator 16 can first convert the serial tn-bit second signal into two groups of second sub-signals in parallel, each group of second sub-signals is tn / 2 bits, and each third wire and each second command interface are used to transmit the tn / 2-bit second sub-signal. Wherein, n represents that every n-bit digital signal corresponds to one second command, and t represents that t second commands are repeatedly transmitted. Figure 6b

[0126] For example, the second recovery clock generator 16 can send the second signal 1001 to the second recovery clock receiver 23 through one third wire and one second command interface, and the second signal received by the second recovery clock receiver 23 is also 1001.

[0127] ​For example, the second recovery clock generator 16 can send a second sub-signal to the second recovery clock receiver 23 via two third lines and two second command interfaces. One of the third lines is a high-order line, and the other is a low-order line. The second recovery clock generator 16 can simultaneously send the second sub-signal to the second recovery clock receiver 23 via the low-order line, the high-order line, and the two second command interfaces. Assuming the second signal sent by the second recovery clock generator 16 to the second recovery clock receiver 23 is 1001, the digital signal 1 transmitted on the low-order line and the digital signal 0 transmitted on the high-order line can be sent to the second recovery clock receiver 23 first, and then the digital signal 0 transmitted on the low-order line and the digital signal 1 transmitted on the high-order line can be sent to the second recovery clock receiver 23.

[0128] Optionally, the number of third traces and the number of second commands can be multiple to improve the transmission rate of the second signal and avoid the second signal transmission being too slow, causing the data sent by the storage unit 11 to the control circuit 20 to be output before the second signal.

[0129] In another embodiment, such as Figure 7 As shown, this application also provides a method for controlling a memory, the memory 10 including a first command interface, and the method for controlling the memory can be implemented through the following steps:

[0130] S110, triggered by the first clock signal, receives the first signal sent by the control circuit 20 through the first command interface. The clock frequency of the first clock signal is the same as the clock frequency of the second clock signal in the control circuit 20 used to trigger the output of the first signal.

[0131] The memory 10 can receive a first signal in digital form via a first command interface when triggered by a first clock signal. Since the clock frequency of the first clock signal is the same as the clock frequency of the second clock signal used to trigger the output of the first signal, when the control circuit 20 sends a high level (digital signal "1") to the memory 10 when triggered by the second clock signal, the memory 10 will also receive a corresponding high level (digital signal "1") when triggered by the first clock signal at the same clock frequency; or, when the control circuit 20 sends a low level (digital signal "0") to the memory 10 when triggered by the second clock signal, the memory 10 will also receive a corresponding low level (digital signal "0") when triggered by the first clock signal at the same clock frequency.

[0132] In some possible implementations, memory 10 may include a first clock generation circuit that generates a first clock signal. Control circuit 20 may include a third clock generation circuit that generates a second clock signal.

[0133] Since the first clock generation circuit can generate the first clock signal and the third clock generation circuit can generate the second clock signal, there is no need for external circuitry to provide the control circuit 20 with the second clock signal for triggering the first signal output via wiring, nor is there need for external circuitry to provide the memory 10 with the first clock signal for triggering the reception of the first signal via wiring. This eliminates the need for clock lines CK_t / c and clock enable line CKE, reducing the number of traces on the circuit board and saving board-level space and bandwidth.

[0134] In some possible implementations, the circuit board may also include a first trace connecting the control circuit 20 and the memory 10. Each first trace corresponds one-to-one with a first command interface; the number of first traces and first command interfaces may be multiple or single. The control circuit 20 can send a first signal to the memory 10 via one first trace and one first command interface, or the control circuit 20 can send a first signal to the memory 10 via multiple first traces and multiple first command interfaces.

[0135] Assume the total number of bits of the first signal sent by the control circuit 20 to the memory 10 is denoted as [tn-1:0], totaling tn bits. For example... Figure 2b As shown, if the number of the first trace and the first command interface is one, then the first trace and the first command interface are used to transmit the first signal of bit tn; as Figure 2c As shown, if there are two first traces and two first command interfaces, each first trace and each first command interface is used to transmit tn / 2 bits of first sub-signals. After receiving the two sets of first sub-signals, the memory 10 converts the two parallel sets of first sub-signals into a serial first signal. Here, n represents that every n bits of digital signal corresponds to one first command, and t represents that t first commands are transmitted repeatedly.

[0136] For example, the control circuit 20 can send a first signal 1001 to the memory 10 through a first trace and a first command interface, and the memory 10 also receives a first signal of 1001.

[0137] For example, control circuit 20 can send a first sub-signal to memory 10 through two first traces and two first command interfaces. One of the first traces is a high-order line, and the other is a low-order line. Control circuit 20 can simultaneously send the first sub-signal to memory 10 through the low-order line, the high-order line, and the two first command interfaces. The digital signal 1 transmitted on the low-order line and the digital signal 0 transmitted on the high-order line can be sent to memory 10 first, and then the digital signal 0 transmitted on the low-order line and the digital signal 1 transmitted on the high-order line can be sent to memory 10. Memory 10 converts the two parallel first sub-signals into a serial first signal, which can be 1001.

[0138] Optionally, assuming the first command is a write command or a read command, the number of first traces and the number of first commands can be multiple to improve the transmission rate of the first signal, so that the first signal is input to the memory 10 before its corresponding write input, or the first signal is input to the memory 10 first, and the read data corresponding to the first signal is then sent from the memory 10 to the control circuit 20.

[0139] S120, in response to the received first signal, a first command matching the first signal is determined. The memory 10 can match the received first signal with a pre-stored command library to determine the first command matching the first signal.

[0140] Here, the pre-stored command library may include a correspondence between multiple digital signals and commands. For example, digital signal 1010 corresponds to a read command, and digital signal 0101 corresponds to a write command. This example shows that every 4 digital signals correspond to one first command. In other possible implementations, the number of bits in the digital signal corresponding to a first command may be different, and this application embodiment does not limit this.

[0141] S130, execute the operation that matches the first command.

[0142] In some possible implementations, memory 10 may include multiple storage cells 11. In different cases, the first command may act on different storage cells 11. The first command may also include a first address, which can specify at least a portion of the storage cells 11 that need to execute the first command, so that the specified at least a portion of the storage cells 11 perform the operation matching the first command.

[0143] like Figure 2c As shown, the memory 10 may also include a multiplexer 14, which can be used to apply the first command to different memory cells 11. After the memory 10 determines at least a portion of the specified memory cells 11 according to the first command, it can also send the first command to the specified at least a portion of the memory cells 11 through the multiplexer 14.

[0144] For example, multiple storage cells 11 are arranged in an array, and the array of storage cells 11 is divided into multiple rows. Assuming that the first command is applied to the first row of storage cells 11, the first command can be sent to the first row of storage cells 11 through the multiplexer 14, and the first row of storage cells 11 performs the operation matching the first command.

[0145] In some possible implementations, the embodiments of this application do not limit the specific first command, as long as the first command is sent from the control circuit 20 to the memory 10.

[0146] For example, the first command can be a write command, a read command, a chip select command, an activate command, a precharge command, a refresh command, a low power operation command, and the like sent by the control circuit 20 to the memory 10. In this way, the first wire in the application which is electrically connected with the first command can also replace the address line (A0-A17, BG[1:0], BA[1:0], etc.), the chip select line CS, the activate line ACT_n, and the like. In combination with the aforementioned omitted clock line CK_t / c and clock enable line CKE, the number of wires on the circuit board is greatly reduced, the utilization rate of the first wire is improved, and the board-level space resources and bandwidth of the circuit board are saved.

[0147] As shown in Figure 3a , taking the write command and the read command as examples of the first command, the memory 10 can further include a data interface. The control circuit 20 can write write data to at least part of the storage units 11 through the data interface and the multiplexer 14, or at least part of the storage units 11 can read read data out to the control circuit 20 through the multiplexer 14 and the data interface.

[0148] On this basis, as shown in Figure 3b , the number of data interfaces can be multiple, and the circuit board can further include multiple second wires connecting the control circuit 20 and the memory 10. The second wires and the data interfaces correspond one-to-one, and the control circuit 20 and the memory 10 can transmit write data and read data through the multiple second wires and the multiple data interfaces.

[0149] As shown in Figure 3b , if the first command is a write command, the memory 10 can receive multiple groups of first data sent by the control circuit 20 in parallel through the multiple data interfaces under the triggering of a third clock signal, convert the multiple groups of first data in parallel into write data in series, and write the write data in series to at least part of the storage units 11 through the multiplexer 14. The clock frequency of the third clock signal can be the same as the clock frequency of a fourth clock signal in the control circuit 20 for triggering the output of the multiple groups of first data.

[0150] For example, as shown in Figure 4a , assuming that the number of second wires is 16, and each 16-bit write data constitutes a valid write data. After the control circuit 20 sends a first signal to the memory 10 for indicating a write command, the control circuit 20 sends 16 first data in parallel through the 16 second wires, and the memory 10 converts the 16 first data in parallel into 16-bit write data in series, and writes the 16-bit write data in series as a valid write data into at least part of the storage units 11.

[0151] The 16 first data transmitted in parallel by the 16 second wirings can be sorted in order from low bit to high bit, so that the memory 10 converts the received 16-bit parallel first data into 16-bit serial write data.

[0152] Since the clock frequency of the third clock signal is the same as that of the fourth clock signal, when the control circuit 20 sends a high level (digital signal "1") to the memory 10 under the triggering of the fourth clock signal, the memory 10 also receives a corresponding high level (digital signal "1") under the triggering of the third clock signal with the same clock frequency; or when the control circuit 20 sends a low level (digital signal "0") to the memory 10 under the triggering of the fourth clock signal, the memory 10 also receives a corresponding low level (digital signal "0") under the triggering of the third clock signal with the same clock frequency.

[0153] As shown in Figure 3b , if the first command is a read command, the memory 10 can also receive the serial read data sent by at least part of the memory cells 11 through the multiplexer 14, convert the serial read data into multiple groups of parallel second data, and input the multiple groups of second data to the control circuit 20 in parallel through multiple data interfaces under the triggering of a fifth clock signal. The clock frequency of the fifth clock signal can be the same as that of a sixth clock signal used to trigger the control circuit 20 to receive the multiple groups of second data.

[0154] For example, as shown in Figure 4b , assuming that the number of second wirings is 16 and each 16-bit read data constitutes a valid read data, after the control circuit 20 sends the first signal to the memory 10 to indicate the read command, at least part of the memory cells 11 output serial 16 read data through the multiplexer 14. The memory 10 converts the serial 16 read data into parallel 16 second data and sends the parallel 16 second data to the control circuit 20 through the 16 second wirings.

[0155] In addition, since the clock frequency of the fifth clock signal is the same as that of the sixth clock signal, when the memory 10 sends a high level (digital signal "1") to the control circuit 20 under the triggering of the third clock signal, the control circuit 20 also receives a corresponding high level (digital signal "1") under the triggering of the sixth clock signal with the same clock frequency; or when the memory 10 sends a low level (digital signal "0") to the control circuit 20 under the triggering of the third clock signal, the control circuit 20 also receives a corresponding low level (digital signal "0") under the triggering of the sixth clock signal with the same clock frequency.

[0156] In some possible implementation manners, the clock frequency of the third clock signal can be the same as the clock frequency of the fifth clock signal, in which case, the frequency of writing the write data to the at least partial storage unit 11 is the same as the frequency of reading the read data from the at least partial storage unit 11. Of course, the clock frequency of the third clock signal can also be different from the clock frequency of the fifth clock signal, which is not limited in the embodiments of the present application.

[0157] In some possible implementation manners, the first clock generation circuit can further generate the third clock signal and the fifth clock signal required by the control circuit 20. In this way, when the first command is a write command, the data line receiving clock TDQS[2:0]t / c can be saved; when the first command is a read command, the data line sending clock DQS[2:0]t / c can be saved, greatly reducing the number of lines on the circuit board, improving the utilization rate of the first line and the second line, and saving the board-level space resources and bandwidth of the circuit board.

[0158] As shown in Figure 5 , taking the first command as a first chip select command as an example, it is assumed that the memory 10 includes a first memory and a second memory, and the first memory and the second memory are both in a non-working state. If the control circuit 20 needs to interact with the first memory, the first chip select command can be sent to the first memory and the second memory, and the first chip select command can be used as a chip select enable of the first memory, so that the first memory starts to work. When the first memory receives a second chip select command different from the first chip select command, the first memory is still in the non-working state. As for the second memory, even if the first chip select command is received, the second memory is still in the non-working state. In this way, the chip select line CS can also be saved, the number of lines on the circuit board is reduced, the utilization rate of the first line is improved, and the board-level space resources and bandwidth of the circuit board are saved.

[0159] For example, the first chip select command is 0000, and the second chip select command is 1111. When the first command is 0000, the first memory starts to work after receiving the first command. When the first command is 1111, the first memory is still in the non-working state after receiving the first command.

[0160] Of course, the control circuit 20 can also send the first chip select command to the first memory in a targeted manner, rather than sending the first chip select command to all first memories and second memories, which is not limited in the embodiments of the present application.

[0161] In some embodiments, as shown in Figure 6a and Figure 6b , the at least partial storage unit 11 can feed back the second command to the control circuit 20 based on the current working condition. Based on this, the memory 10 can further include a second command interface. As shown in Figure 8As shown, the control method of the memory can further include:

[0162] S210, generating a second command and determining a second signal matched with the second command.

[0163] In some possible implementation manners, the second command is not limited by the embodiments of the present application, and any command that can be sent by the memory 10 to the control circuit 20 can be used as the second command.

[0164] For example, the second command includes at least one of an alert command and a data inversion command. By omitting the alert line ALERT_n and the data inversion line DMI, the number of lines on the circuit board is reduced, the utilization rates of the first line, the second line and the third line are improved, and the board-level space resources and bandwidth of the circuit board are saved.

[0165] In some possible implementation manners, the memory 10 can match the generated second command with a pre-stored command library to determine the second signal matched with the second command, and send the second signal to the control circuit 20.

[0166] For example, the second command is an error reporting command, the error reporting command corresponds to the digital signal 0001, and the second signal can be 0001.

[0167] S220, under the triggering of a seventh clock signal, sending the second signal to the control circuit 20 through the second command interface. The clock frequency of the seventh clock signal is the same as the clock frequency of an eighth clock signal used for triggering the control circuit 20 to receive the second signal.

[0168] Since the clock frequency of the seventh clock signal is the same as the clock frequency of the eighth clock signal used for triggering the control circuit 20 to receive the second signal, under the triggering of the seventh clock signal, the memory 10 outputs a high level (digital signal "1") every time, and the control circuit 20 also receives the corresponding high level (digital signal "1") under the triggering of the eighth clock signal with the same clock frequency; or under the triggering of the seventh clock signal, the memory 10 outputs a low level (digital signal "0") every time, and the control circuit 20 also receives the corresponding low level (digital signal "0") under the triggering of the eighth clock signal with the same clock frequency.

[0169] In some possible implementation manners, the memory 10 can include a second clock generation circuit, and the second clock generation circuit can generate the seventh clock signal. The control circuit 20 can include a fourth clock generation circuit, and the fourth clock generation circuit can generate the eighth clock signal.

[0170] Since the second clock generation circuit can generate the seventh clock signal and the fourth clock generation circuit can generate the eighth clock signal, there is no need for external circuitry to provide the seventh clock signal for triggering the second signal output to the memory 10 via traces, nor is there a need for external circuitry to provide the eighth clock signal for triggering the reception of the second signal to the control circuit 20 via traces. This eliminates the need for clock lines CK_t / c and clock enable line CKE, reducing the number of traces on the circuit board and saving board-level space and bandwidth.

[0171] In some possible implementations, the circuit board may also include a third trace connecting the memory 10 and the control circuit 20. The third trace corresponds one-to-one with the second command interface; the number of third traces and second command interfaces may be multiple or single. The memory 10 can send a second signal to the control circuit 20 via one third trace and one second command interface, or the memory 10 can send a second signal to the control circuit 20 via multiple third traces and multiple second command interfaces.

[0172] Assume the total number of bits of the second signal sent from memory 10 to control circuit 20 is denoted as [tn-1:0], totaling tn bits. For example... Figure 6a As shown, if the number of third traces and second command interfaces is one, then the third trace and second command interface are used to transmit the tn-bit second signal; as... Figure 6b As shown, if there are two third traces and two second command interfaces, the memory 10 can first convert the serial tn-bit second signal into two parallel sets of second sub-signals, each set of second sub-signals being tn / 2 bits. Each third trace and each second command interface is used to transmit tn / 2 bits of second sub-signals. Here, n represents that every n bits of digital signal corresponds to one second command, and t represents that the second command is transmitted t times.

[0173] For example, memory 10 can send a second signal 1001 to control circuit 20 via a third trace and a second command interface, and control circuit 20 can also receive a second signal of 1001.

[0174] For example, memory 10 can send a second sub-signal to control circuit 20 via two third lines and two second command interfaces. One of the third lines is the high-order line, and the other is the low-order line. Memory 10 can simultaneously send the second sub-signal to control circuit 20 via the low-order line, the high-order line, and the two second command interfaces. Assuming the second signal sent by memory 10 to control circuit 20 is 1001, the digital signal 1 transmitted on the low-order line and the digital signal 0 transmitted on the high-order line can be sent to control circuit 20 first, and then the digital signal 0 transmitted on the low-order line and the digital signal 1 transmitted on the high-order line can be sent to control circuit 20.

[0175] Optionally, the number of the third traces and the number of the second commands can be multiple, so as to improve the transmission rate of the second signal and avoid the second signal being too slow to cause the data sent by the storage unit 11 to the control circuit 20 to be output before the second signal.

[0176] The embodiments of the present application are described above with reference to the accompanying drawings, but the present application is not limited to the specific embodiments described above, and the specific embodiments described above are only illustrative but not restrictive, and those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

Claims

1. A memory, characterized in that, Includes a recovery clock receiver, a command decoder, multiple storage units, and a first command interface; The recovery clock receiver is used to receive a first signal sent by the control circuit through a first command interface when triggered by a first clock signal, and to send the first signal to the command decoder. The clock frequency of the first clock signal is the same as the clock frequency of the second clock signal used in the control circuit to trigger the output of the first signal; The command decoder is configured to, in response to the received first signal, determine a first command that matches the first signal, and send the first command to at least a portion of the storage units; The at least part of the storage unit is used to perform an operation that matches the first command.

2. The memory according to claim 1, characterized in that, The memory also includes a multiplexer; The command decoder is configured to determine, based on the first command, the at least portion of the storage units indicated by the first command; The command decoder is also used to send the first command to the at least part of the storage unit via the multiplexer.

3. The memory according to claim 2, characterized in that, The memory also includes a data interface; The first command is a write command; the at least part of the storage unit is used to receive write data through the data interface and the multiplexer; or, The first command is a read command; the at least part of the storage unit is also used to read read data through the multiplexer and the data interface.

4. The memory according to claim 3, characterized in that, The number of data interfaces is multiple, and the memory also includes a data transmission unit; The first command is a write command; the data transmission unit is used to receive multiple sets of first data sent by the control circuit in parallel through multiple data interfaces under the trigger of the third clock signal, convert the parallel multiple sets of first data into serial write data, and serially send the serial write data to the at least part of the storage unit through the multiplexer. The clock frequency of the third clock signal is the same as the clock frequency of the fourth clock signal in the control circuit used to trigger the multiple sets of first data outputs. or, The first command is a read command; the data transmission unit is also used to receive the serial read data sent by at least some of the storage units through the multiplexer, convert the serial read data into multiple sets of parallel second data, and input the multiple sets of second data in parallel to the control circuit through multiple data interfaces under the trigger of the fifth clock signal. The clock frequency of the fifth clock signal is the same as the clock frequency of the sixth clock signal used to trigger the control circuit to receive the multiple sets of second data.

5. The memory according to claim 4, characterized in that, The clock frequency of the third clock signal is the same as the clock frequency of the fifth clock signal.

6. The memory according to claim 4 or 5, characterized in that, The recovery clock receiver includes a first clock generation circuit, which generates the first clock signal, the third clock signal, and the fifth clock signal.

7. The memory according to claim 1, characterized in that, The first command is the first chip select command; The memory is configured to start working under the control of the first chip select command and remain in a non-working state under the control of the second chip select command; the first chip select command and the second chip select command are different.

8. The memory according to any one of claims 1-7, characterized in that, There are multiple first command interfaces; The recovery clock receiver is used to receive multiple sets of first sub-signals sent by the control circuit in parallel through multiple first command interfaces when triggered by the first clock signal. The recovery clock receiver is also used to convert the multiple sets of first sub-signals transmitted in parallel into the first signal transmitted in serial form.

9. The memory according to claim 1 or 2, characterized in that, The first command also includes at least one of the following: activation command, precharge command, refresh command, and low-power operation command.

10. The memory according to claim 1, characterized in that, The memory also includes a recovery clock generator and a second command interface; The at least part of the storage unit is also used to send a second command to the command decoder; The command decoder is further configured to, in response to the received second command, determine a second signal matching the second command, and send the second signal to the recovery clock generator; The recovery clock generator is used to send the second signal to the control circuit through the second command interface when triggered by the seventh clock signal. The clock frequency of the seventh clock signal is the same as the clock frequency of the eighth clock signal used to trigger the control circuit to receive the second signal.

11. The memory according to claim 10, characterized in that, There are multiple second command interfaces; The recovery clock generator is used to convert the serial second signal into multiple sets of parallel second sub-signals; The recovery clock generator is also used to send the multiple sets of second sub-signals in parallel to the control circuit through multiple second command interfaces when triggered by the seventh clock signal.

12. The memory according to claim 10 or 11, characterized in that, The recovery clock generator includes a second clock generation circuit, which is used to generate the seventh clock signal.

13. The memory according to claim 10 or 11, characterized in that, The second command includes at least one of an alarm command and a data inversion command.

14. A circuit board, characterized in that, Includes a control circuit and a memory as described in any one of claims 1-13; The control circuit is used to send a first signal to the memory when triggered by a second clock signal.

15. An electronic device, characterized in that, It includes one or more computer programs and the circuit board of claim 14; the one or more computer programs are stored in a memory on the circuit board.

16. A method for controlling a memory, characterized in that, The memory includes a first command interface; The control method for the memory includes: Triggered by a first clock signal, a first signal sent by the control circuit is received through a first command interface; the clock frequency of the first clock signal is the same as the clock frequency of the second clock signal in the control circuit used to trigger the output of the first signal. In response to the received first signal, a first command matching the first signal is determined; Perform the operation that matches the first command.

17. The memory control method according to claim 16, characterized in that, The memory also includes a data interface; The first command is a write command; the execution of the operation matching the first command includes: Receive write data through the data interface; or... The first command is a read command; the operation matching the first command includes: Data is read through the data interface.

18. The memory control method according to claim 17, characterized in that, There are multiple data interfaces, and the first command is a write command; Receiving write data through the data interface includes: Triggered by the third clock signal, multiple sets of first data sent by the control circuit are received in parallel through multiple data interfaces; the clock frequency of the third clock signal is the same as the clock frequency of the fourth clock signal in the control circuit used to trigger the output of the multiple sets of first data. The parallel sets of first data are converted into serial write data; Write the serial data.

19. The memory control method according to claim 17, characterized in that, There are multiple data interfaces, and the first command is a read command; Reading data through the data interface includes: The serially read data is converted into multiple sets of parallel second data; Triggered by the fifth clock signal, the multiple sets of second data are input in parallel to the control circuit through multiple data interfaces; the clock frequency of the fifth clock signal is the same as the clock frequency of the sixth clock signal used to trigger the control circuit to receive the multiple sets of second data.

20. The memory control method according to claim 16, characterized in that, The first command is the first chip select command; The execution of the operation matching the first command includes: It starts working under the control of the first chip select command and remains in a non-working state under the control of the second chip select command. The first chip select command is different from the second chip select command.

21. The method for controlling a memory according to any one of claims 16-20, characterized in that, The number of the first command interfaces is multiple; the step of receiving the first signal sent by the control circuit through the first command interface under the trigger of the first clock signal includes: Triggered by the first clock signal, multiple sets of first sub-signals sent by the control circuit are received in parallel through multiple first command interfaces; The multiple sets of first sub-signals transmitted in parallel are converted into the first signal transmitted in serial form.

22. The memory control method according to claim 16, characterized in that, The memory also includes a second command interface; Generate a second command and determine a second signal that matches the second command; Triggered by the seventh clock signal, the second signal is sent to the control circuit through the second command interface; The clock frequency of the seventh clock signal is the same as the clock frequency of the eighth clock signal used to trigger the control circuit to receive the second signal.

23. The memory control method according to claim 22, characterized in that, The number of second command interfaces is multiple; the step of sending the second signal to the control circuit through the second command interface under the trigger of the seventh clock signal includes: The serial second signal is converted into multiple parallel sets of second sub-signals; Triggered by the seventh clock signal, the multiple sets of second sub-signals are sent in parallel to the control circuit through multiple second command interfaces.

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