Lower electrode system and semiconductor process equipment

Abstract

The present invention provides a lower electrode system and semiconductor process equipment. The system includes a carrier device and a pin device. The pin device is used to lift a wafer from the carrier device or place the wafer on the carrier device. The system also includes a grounding device, which includes a grounding circuit, a grounding switch, and a control unit. The grounding circuit is electrically connected to the lower electrode in the carrier device via the grounding switch and is used to ground the lower electrode when the grounding switch is closed. The control unit is used to control the grounding switch to open before the plasma generation phase of the semiconductor process begins, and to control the grounding switch to close after the plasma generation phase ends and the pin device lifts the wafer from the carrier device. This solution can improve the repeatable transfer accuracy of wafers and ensure that the AWC results meet the requirements.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a lower electrode system and semiconductor process equipment. Background Art

[0002] In advanced semiconductor edge etching equipment, the etcher etches the edge of the wafer after completing process steps such as photolithography, desmearing, deposition, or etching, removing edge polymer to reduce defects in subsequent process flows and improve product yield. In edge etching equipment, the wafer is usually placed on a carrier within the process chamber. During the edge etching process, due to the DC bias phenomenon, the wafer and the lower electrode in the carrier are both negatively charged. If the accumulated charge cannot be discharged in a timely and effective manner, it will accumulate on the wafer surface, causing particle problems. The charge will also accumulate inside the lower electrode. Because the lower electrode usually has gaps and channels, for example, if the lower electrode is provided with a gas delivery channel, the accumulated charge on the lower electrode will generate a potential difference with the cooling gas flowing into the channel. If the channel space is large, there is a risk of discharge and sparking. Once a discharge and spark occurs, it often causes electrical damage or even serious damage to the lower electrode. Therefore, the lower electrode needs to be grounded to conduct away the negative charge of the lower electrode. At the same time, the wafer also needs to be grounded to conduct away the negative charge of the wafer to avoid particle and spark problems.

[0003] However, at the end of the process, the lower electrode, which has been in a grounded state, will conduct the negative charge accumulated inside the lower electrode into the ground when the RF power is turned off. At this time, the wafer on the carrier is still negatively charged, and there is a potential difference between the wafer and the lower electrode, which in turn causes electrostatic adsorption between the wafer and the lower electrode, causing the wafer to shift during the needle lifting process, resulting in the AWC (Active Wafer Centering, wafer automatic correction) result failing to meet the requirements. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a lower electrode system and semiconductor process equipment, which can solve the problem of wafer deviation during the needle lifting process due to electrostatic adsorption between the wafer and the lower electrode.

[0005] To achieve the objectives of the present invention, a lower electrode system is provided for use in semiconductor process equipment, comprising a carrier device and an ejector pin device, wherein the ejector pin device is used to lift a wafer on the carrier device or place a wafer on the carrier device, and further comprising a grounding device, wherein the grounding device comprises a grounding circuit, a grounding switch, and a control unit, wherein the grounding circuit is electrically connected to the lower electrode in the carrier device through the grounding switch, and is used to ground the lower electrode when the grounding switch is closed;

[0006] The control unit is used to control the grounding switch to be disconnected before the plasma generation phase of the semiconductor process begins, and to control the grounding switch to be closed after the plasma generation phase ends and the ejector device lifts the wafer on the carrier device.

[0007] Optionally, the ejector device is configured to ground the wafer after lifting the wafer on the carrier device.

[0008] Optionally, the ejector device is configured to be electrically connected to the grounding switch through the lower electrode, so as to ground the wafer on the ejector device when the control unit controls the grounding switch to be closed.

[0009] Optionally, the ejector device includes a plurality of conductive ejectors and a plurality of conductive ejector bellows, wherein a plurality of through holes are provided in the carrier device and are spaced apart along the circumference of the carrier device, and the plurality of ejectors correspond one to one and are lifted and lowered through the plurality of through holes; the plurality of ejector bellows are sleeved on the plurality of ejectors in a one-to-one correspondence, and the upper end of each ejector bellows is sealed and connected to the carrier device and is electrically conductive; the lower end of each ejector bellows is sealed and connected to the corresponding ejector pin and is electrically conductive.

[0010] Optionally, a radio frequency feeding device is further included, wherein the radio frequency feeding device is electrically connected to the lower electrode and is used to be electrically connected to a radio frequency power supply through a matching device to load radio frequency power to the lower electrode.

[0011] Optionally, the grounding circuit includes a circuit for connecting between the lower electrode and the ground, and a grounding resistor connected in series to the grounding circuit; the grounding switch is connected in series to the grounding circuit and is located on a side of the grounding resistor close to the lower electrode.

[0012] Optionally, the resistance of the grounding resistor is greater than or equal to 5 MΩ and less than or equal to 20 MΩ.

[0013] As another technical solution, the present invention further provides a semiconductor process equipment, including a process chamber and a lower electrode system, wherein the lower electrode system includes a carrier device, a ejector device, and a grounding device, wherein the ejector device is used to lift a wafer on the carrier device or place a wafer on the carrier device; the grounding device includes a grounding circuit, a grounding switch, and a control unit, wherein the grounding circuit is electrically connected to the lower electrode in the carrier device through the grounding switch, and is used to ground the lower electrode when the grounding switch is closed;

[0014] The control unit includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, a lower electrode system control method is implemented, wherein the lower electrode system control method includes:

[0015] Before the plasma generation phase of the semiconductor process begins, controlling the ground switch to be open;

[0016] After the plasma generation phase ends and the ejector device lifts the wafer on the carrier device, the grounding switch is controlled to be closed.

[0017] Optionally, the control unit is further configured to:

[0018] Before placing the wafer on the carrier, controlling the chamber pressure to reach a first pressure value;

[0019] After the wafer is placed on the carrier, process gas is introduced into the process chamber, and the chamber pressure is controlled to reach a second pressure value; the second pressure value is greater than the first pressure value to form a pressure difference between the upper surface and the lower surface of the wafer, thereby fixing the wafer on the carrier.

[0020] Optionally, the semiconductor process equipment includes edge etching equipment.

[0021] The present invention has the following beneficial effects:

[0022] In the technical solution of the lower electrode system and semiconductor process equipment provided by the present invention, by controlling the ground switch to open before the plasma generation phase of the semiconductor process begins, the lower electrode in the carrier device is disconnected from the ground. Therefore, during the plasma generation phase, the negative charge accumulated in the lower electrode is not discharged. The lower electrode and the wafer accumulate negative charge simultaneously, so that both the lower electrode and the wafer are negatively charged and have substantially the same potential. This avoids a potential difference between the wafer and the lower electrode, and prevents electrostatic adsorption between them. Consequently, when the ejector device lifts the wafer from the carrier device, the wafer is not deflected due to electrostatic adsorption, thereby effectively improving the repeatable transfer accuracy of the wafer and ensuring that the AWC (wafer automatic correction) results meet the requirements. Furthermore, after the plasma generation phase ends and the ejector device lifts the wafer from the carrier device, controlling the ground switch to close grounds the lower electrode, thereby allowing the accumulated charge in the lower electrode to be discharged and preventing sparking within the lower electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A structural diagram of a lower electrode system and semiconductor process equipment provided by an embodiment of the present invention;

[0024] Figure 2is a timing diagram of the ground switch input signal and RF power in an embodiment of the present invention;

[0025] Figure 3 A state diagram of the lower electrode system provided by an embodiment of the present invention during the plasma generation stage;

[0026] Figure 4 A state diagram of the lower electrode system provided by an embodiment of the present invention when the ejector device holds up the wafer;

[0027] Figure 5 A state diagram of the lower electrode system provided in an embodiment of the present invention when the plasma generation stage ends and the ejector device lifts the wafer;

[0028] Figure 6 AWC result diagram of related technology;

[0029] Figure 7 This is an AWC result diagram of an embodiment of the present invention;

[0030] Figure 8 A flow chart of a lower electrode system control method used in semiconductor process equipment provided by an embodiment of the present invention;

[0031] Figure 9 Another flow chart of a lower electrode system control method used in semiconductor process equipment provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the technical solution of the present invention, the lower electrode system and semiconductor process equipment provided by the present invention are described in detail below with reference to the accompanying drawings.

[0033] See also Figure 1 The lower electrode system 100 provided in the embodiment of the present invention is applied to semiconductor process equipment, which includes, for example, Figure 1 The edge etching equipment shown is used to etch the edge region of the wafer 3 to remove edge polymer. Of course, in practical applications, the semiconductor process equipment may also include other types of process equipment, and the embodiment of the present invention has no particular limitation thereto.

[0034] Specifically, the lower electrode system 100 includes a carrier device 1 and a ejector device 2, wherein the ejector device 2 is used to lift the wafer 3 on the carrier device 1 or place the wafer 3 on the carrier device 1, so as to cooperate with the robot arm to realize the wafer 3 taking or placing operation.

[0035] In some embodiments, the ejector device 2 includes a plurality of ejector pins 21 and a plurality of ejector bellows 22, wherein a plurality of through holes 23 are provided in the carrier device 1 and are spaced apart along the circumference of the carrier device 1. The plurality of ejector pins 21 correspond to each other and are arranged to be lifted and lowered through the plurality of through holes 23. The lower end of each ejector pin 21 can pass through the bottom of the process chamber 200 of the semiconductor process equipment and extend outside the process chamber 200 so as to be connected to an external lifting drive source (not shown in the figure). Driven by the lifting drive source, the plurality of ejector pins 21 can be raised and lowered synchronously so that their top ends can rise to a position higher than the carrying surface of the carrier device 1, thereby lifting the wafer 3 on the carrier device 1; or the top ends of the ejector pins 21 can be lowered to a position lower than the carrying surface of the carrier device 1, thereby placing the wafer 3 placed on the top ends of the plurality of ejector pins 21 on the carrying surface of the carrier device 1. Of course, in actual applications, the aforementioned lift drive source may also be disposed within the process chamber 200. In this case, the lower ends of the plurality of ejector pins 21 do not need to extend outside the process chamber 200 and may be connected to the lift drive source within the process chamber 200. For example, the aforementioned lift drive source may be a plurality of drive components mounted on the carrier device 1 and connected one-to-one with the plurality of ejector pins 21. The plurality of drive components are used to drive the plurality of ejector pins 21 to rise and fall synchronously. The drive components may be, for example, a lift cylinder, an electric lift cylinder, or the like.

[0036] When the lower ends of the multiple ejector pins 21 extend outside the process chamber 200, multiple ejector bellows 22 are mounted one-to-one on the multiple ejector pins 21, and the upper end of each ejector bellows 22 is sealedly connected to the carrier device 1, for example, by welding. The lower end of each ejector bellows 22 extends outside the process chamber 200 through the through-hole 201 in the chamber bottom, which is penetrated by the ejector pin 21, and is sealedly connected to the corresponding ejector pin 21, for example, by welding. In this way, each ejector bellows 22 can seal the through-hole 23 in the carrier device 1. Since the upper end of the through-hole 23 is located on the supporting surface of the carrier device 1, sealing the through-hole 23 ensures the sealing of the process chamber 200 of the semiconductor processing equipment. At the same time, the ejector bellows 22 also enables the ejector pins 21 to be raised and lowered. In addition, the through-hole 201 in the chamber bottom, which is penetrated by the ejector pin 21, requires additional sealing structure to ensure the sealing of the process chamber 200.

[0037] The above-mentioned supporting device 1 can have a variety of structures, for example, including a base plate 11, a chuck 12 and an interface plate 13 arranged in sequence from top to bottom. The base plate 11, the chuck 12 and the interface plate 13 are integrated together and electrically conductive, and the three as a whole constitute the lower electrode. The base plate 11 is made of a conductive material, such as Al, and the upper surface of the base plate 11 is provided with a hard anodized coating 11a for supporting the wafer 3 and electrically insulating the base plate 11 from the wafer 3. The hard anodized coating 11a is, for example, Al2O3. The main body of the chuck 12 is made of a conductive material, such as Al. A temperature control channel can also be provided in the main body of the chuck 12 for conveying a temperature control medium (heating medium or cooling medium) to achieve temperature control of the lower electrode. Optionally, the outer peripheral surface of the chuck 12 and the outer peripheral surface of the interface plate 13 are provided with a hard anodized coating or other insulating layer to prevent the chuck 12 and the interface plate 13 from contacting the plasma. The main body of the chuck 12 can be used to electrically connect to the lower electrode RF device 400 (including the matcher 401 and the RF power supply 402). In some embodiments, the lower electrode system 100 also includes an RF feedthrough 14, which is, for example, mounted on the interface plate 13 and electrically connected to the main body of the chuck 12. The RF feedthrough 14 is used to electrically connect to the RF power supply 402 through the matcher 401 to load RF power to the main body of the chuck 12, thereby exciting the process gas in the process chamber 200 to form a plasma and etch the wafer 3.

[0038] In addition, taking the crystal edge etching equipment as an example, the crystal edge etching equipment includes a chamber 202 and an upper electrode cover plate 203 arranged on the top of the chamber 202. The chamber 202 and the upper electrode cover plate 203 together constitute a process chamber 200. In addition, a center hole 203a is provided in the upper electrode cover plate 203. The crystal edge etching equipment also includes an upper electrode 300, a lifting drive device 302 and a top bellows 301. The lifting drive device 302 is installed on the upper electrode cover plate 203, and its drive shaft extends into the process chamber 200 through the center hole 203 and is fixedly connected to the upper electrode 300. It is used to drive the upper electrode 300 to rise and fall to adjust the vertical distance between the upper electrode 300 and the supporting device 1. For example, when performing operations such as taking or placing a wafer, the lifting drive device 302 can be controlled to drive the upper electrode 300 to rise to increase the above-mentioned vertical distance. During the process, the lift drive 302 can be controlled to drive the upper electrode 300 downward, thereby reducing the vertical distance mentioned above to meet the requirements of the edge etching process. The top bellows 301 surrounds the drive shaft of the lift drive 302 and is sealed to the upper electrode cover plate 203, sealing the central hole 203a while ensuring that the drive shaft of the lift drive 302 can be raised and lowered. Of course, in actual applications, the top bellows 301 can also be replaced by other dynamic sealing components such as magnetic fluid seals.

[0039] The upper electrode 300 is used to form an electric field together with the lower electrode to excite the process gas in the process chamber 200 to form plasma. The upper electrode 300 is, for example, an upper electrode plate. The edge area of ​​the upper electrode plate is also provided with an edge gas inlet channel for introducing process gas (for etching) to the edge portion of the wafer 3. In addition, optionally, a central gas inlet channel can also be provided in the central area of ​​the upper electrode plate to introduce an inert gas (such as nitrogen) into the central area of ​​the process chamber 200 to prevent plasma from entering the central area of ​​the process chamber 200. On this basis, in order to prevent plasma from etching the central area of ​​the wafer 3, a shielding component can also be provided in the central area of ​​the upper surface of the wafer 3. The shielding component is, for example, a glass plate.

[0040] When the edge portion of the wafer 3 is etched to remove the edge polymer, before the RF power supply 401 is turned on, the chamber pressure of the process chamber 200 is first controlled to a relatively low pressure range (for example, 70mTorr to 100mTorr) by vacuuming, and then the wafer 3 is placed on the hard anodized coating 11a, and process gas is introduced into the process chamber 200 to raise the chamber pressure of the process chamber 200 to a relatively high pressure range (for example, 1Torr to 3Torr). At this time, there is a pressure difference between the upper surface of the wafer 3 and the lower surface of the wafer 3, that is, the pressure on the upper surface side of the wafer 3 is greater than the pressure on the lower surface side, so that the wafer 3 can be fixed on the hard anodized coating 11a. It is easy to understand that the gas in the process chamber 200 is also slowly flowing into the gap between the lower surface of the wafer 3 and the base 11, causing the pressure on the side of the lower surface of the wafer 3 to slowly increase, and the pressure difference between the upper surface of the wafer 3 and the lower surface of the wafer 3 gradually decays. However, since this is a slow process, there is enough time to fix the wafer 3 on the base 11 while the RF power is turned on, and by adjusting the above-mentioned pressure range, it can be ensured that before the ejector device 2 lifts the wafer 3 on the base 11, the above-mentioned pressure difference decays to zero or close to zero, so as to ensure that the ejector device 2 can normally lift the wafer 3. From the above, it can be seen that the carrier device 1 does not need to set up an additional structure to fix the wafer 3, for example, there is no need to set up an additional electrostatic adsorption electrode such as in an electrostatic chuck, and the wafer 3 can be fixed only by using the above-mentioned pressure difference.

[0041] The interface plate 13 is fixed to the bottom of the cavity 202 and is electrically insulated from the cavity 202. For example, the interface plate 13 can be electrically insulated from the cavity 202 by an insulating ring 15. The interface plate 13 is provided with a variety of interfaces with different functions, such as an RF interface for installing the RF feedthrough 14. For example, it also includes an interface for installing the ejector bellows 22. The ejector bellows 22 is inserted into this interface and its upper end is sealed to the main body of the chuck 12. In addition, through holes for the ejector 21 to pass through are correspondingly provided in the hard anodized coating 11a, the base plate 11, and the chuck 12, forming the above-mentioned through holes 23.

[0042] The lower electrode system 100 also includes a grounding device, which includes a grounding circuit, a grounding switch 102, and a control unit, wherein the grounding circuit is electrically connected to the lower electrode in the carrier device 1 (for example, composed of a base plate 11, a chuck 12, and an interface plate 13) through the grounding switch 102, and is used to ground the lower electrode when the grounding switch 102 is closed. The grounding circuit that realizes this function includes, for example, a circuit 101 for connecting between the lower electrode and the ground, and a grounding resistor 103 connected in series to the circuit 101; the grounding switch 102 is connected in series to the circuit 101 and is located on the side of the grounding resistor 103 close to the lower electrode. The grounding resistor 103 can slowly discharge the charge of the lower electrode when the grounding switch 102 is closed. In addition, when the above-mentioned lower electrode radio frequency device 400 is connected in parallel with the circuit 101, the grounding resistor 103 can also prevent radio frequency leakage when the grounding switch 102 is closed, that is, prevent radio frequency current from flowing into the ground through the circuit. Optionally, the resistance of the grounding resistor 103 ranges from 5 MΩ to 20 MΩ (inclusive), and specific resistance values ​​of the grounding resistor 103 include, for example, 5 MΩ, 10 MΩ, and 20 MΩ. The resistance of the grounding resistor 103 should not be too large, otherwise the charge discharge will be too slow, and static electricity will easily accumulate on the lower electrode (accumulation of static charge without discharge); the resistance of the grounding resistor 103 should not be too small, otherwise it will not effectively prevent RF leakage.

[0043] In some embodiments, the grounding switch 102 is, for example, a relay, which can receive an input signal from the control unit (for example, Figure 2 When the voltage is 0V or 24V, it will automatically open or close.

[0044] See also Figure 2 , the control unit is used to generate plasma during the semiconductor process (i.e., Figure 2 Before the RF start-up phase T2-T3 in the process begins, the ground switch 102 is controlled to be disconnected, for example, Figure 2 The process starts at the time T1 and ends at the plasma generation stage (i.e., at Figure 2The moment T3 in the process ends), and the ejector device 2 lifts the wafer 3 on the carrier device 1 (ie, Figure 2 After the ejector pin lifting phase T3-T4), the grounding switch 102 is controlled to be closed, for example, Figure 2 The process ends at time T4. When the lower electrode RF device 400 is turned on (ie, Figure 2 At the time T2 in the figure, RF power starts to be applied to the lower electrode. At this time, the electric field formed between the lower electrode and the upper electrode 300 can ionize the process gas in the process chamber 200 to form plasma, thereby realizing plasma ignition. The time T2 is the start time of the plasma generation stage. When the lower electrode RF device 400 is turned off (i.e., Figure 2 At time T3 in the figure, the RF power supply to the lower electrode is stopped, and this time T3 is the end time of the plasma generation stage. Of course, the embodiment of the present invention is not limited to this. In actual applications, the method of generating plasma in the process chamber 200 can also be any other method, such as applying RF power to the upper electrode (such as a coil or an electrode plate) by the upper electrode RF device to ionize the process gas in the process chamber 200 to form plasma. The above-mentioned control unit can be a host computer or a slave computer.

[0045] By controlling the grounding switch 102 to be disconnected before the plasma generation phase of the semiconductor process begins, the lower electrode in the carrier device 1 can be disconnected from the ground, so that during the plasma generation phase, the negative charge accumulated in the lower electrode will not be discharged, and the lower electrode and the wafer 3 will accumulate negative charge synchronously. The two are negatively charged as a whole, and the potentials are basically the same, as shown in FIG. Figure 3 As shown. Specifically, during the plasma generation stage, the gas in the process chamber 200 will be ionized under the action of radio frequency energy to form a plasma containing ions and electrons. Under the action of radio frequency energy, the ions and electrons will first be repeatedly accelerated and then decelerated. Since the mass of electrons is much smaller than that of ions, the movement speed of electrons is much greater than that of ions, thereby accumulating electrons on the wafer 3 and showing a negative polarity to the ground. This is the DC bias phenomenon. At the same time, the plasma will inevitably contact the lower electrode through the gap (the outer peripheral surface of the base plate 11 will contact the plasma), that is, the lower electrode will also accumulate negative charges. On this basis, since the lower electrode in the carrier device 1 is disconnected from the ground before the start of the plasma generation stage, the process of accumulating charges on the lower electrode is the same as the process of accumulating charges on the wafer 3. The two achieve the same potential due to the synchronous accumulation of charges, thereby avoiding the potential difference between the wafer 3 and the lower electrode, and no electrostatic adsorption will be generated between the two. Then, when the ejector device 2 lifts the wafer 3 on the carrier device 1, as shown Figure 4As shown, the wafer 3 will not be offset due to electrostatic adsorption, thereby effectively improving the repeatable transfer accuracy of the wafer and ensuring that the AWC (wafer automatic correction) results meet the requirements. It is easy to understand that during the plasma generation phase, and after the plasma generation phase, disconnecting the lower electrode in the carrier device 1 from the ground, it is impossible to synchronize the accumulation of charge between the lower electrode and the wafer 3, and thus it is impossible to achieve the same potential between the two.

[0046] On this basis, after the plasma generation stage is finished and the ejector device 2 lifts the wafer 3 on the carrier device 1, as shown in FIG. Figure 5 As shown, controlling the grounding switch 102 to be closed can ground the lower electrode, thereby allowing the charge accumulated in the lower electrode to be discharged, thereby avoiding the problem of sparking inside the lower electrode.

[0047] In the related art, the lower electrode is kept grounded during the plasma generation phase. In this case, Figure 6 The black box in the figure represents the distribution range of the center position points (black dots) of multiple wafers in the related art (i.e., the AWC range, which represents the wafer repeatability accuracy). In the embodiment of the present invention, before the plasma generation phase begins, the ground switch 102 is controlled to be disconnected. During the plasma generation phase, the negative charge accumulated in the lower electrode will not be discharged. In this case, Figure 7 The black frame in FIG represents the distribution range of the center position points (black dots) of multiple wafers according to the embodiment of the present invention. Figure 6 and Figure 7 As can be seen from the size of the black frame, the AWC range of the related art is too large, while the embodiment of the present invention can control the AWC range within a smaller range, thereby effectively improving the repeatable transmission accuracy of the wafer.

[0048] In some embodiments, the ejector device 2 is configured to ground the wafer 3 after lifting it from the carrier device 1, thereby resolving the particle problem caused by the accumulated charge on the wafer 3. Furthermore, optionally, the ejector device 2 is configured to be electrically connected to the grounding switch 102 via the lower electrode, so that the wafer 3 on the ejector device 2 is grounded simultaneously with the control unit controlling the closing of the grounding switch 102. In this way, the negative charge in the wafer 3 and the lower electrode can be discharged synchronously, thereby consistently avoiding a potential difference between the wafer 3 and the lower electrode, while also resolving the particle problem caused by the accumulated charge on the wafer 3 and the spark problem caused by the accumulated charge on the lower electrode.

[0049] Furthermore, in some embodiments, the ejector device 2 is electrically connected to the grounding switch 102 via the lower electrode in the following manner: the ejector pins 21 and the ejector bellows 22 are both made of a conductive material, such as stainless steel. Furthermore, since the ejector pins 21 and the ejector bellows 22 are interconnected to provide electrical continuity between them, and the ejector bellows 22 is interconnected to provide electrical continuity between them and the bottom of the carrier device 1 (i.e., the lower electrode), when multiple ejector pins 21 lift the wafer 3 on the carrier device 1 and the grounding switch 102 is closed, the negative charge within the wafer 3 is sequentially conducted to the ground via the ejector pins 21, the ejector bellows 22, the lower electrode, and the grounding circuit. Of course, in practical applications, the ejector device 2 can also be grounded in any other manner, or the wafer 3 can also be grounded in any other manner, and this is not particularly limited in the present invention.

[0050] In addition, in some embodiments, the control unit is further configured to control the grounding switch 102 to be in a closed state during a non-processing phase (e.g., including phases T0 to T2 and the phase after time T4) before the process begins and after the process ends. That is, during the non-processing phase, the grounding switch 102 is always in a normally closed state to conduct the negative charge in the lower electrode to the ground.

[0051] As another technical solution, an embodiment of the present invention also provides a semiconductor process equipment, including a process chamber 200 and a lower electrode system 100, wherein the lower electrode system 100 includes a carrier device 1, a pin device 2 and a grounding device. Since the structures and functions of these devices have been described in detail in the above embodiments, they will not be repeated here.

[0052] The control unit in the lower electrode system 100 includes at least one processor and at least one memory. The memory stores a computer program. When the computer program is executed by the processor, the lower electrode system control method is implemented. Figure 8 As shown, the lower electrode system control method includes:

[0053] S1. Before the plasma generation phase of the semiconductor process begins, the ground switch 102 is controlled to be disconnected;

[0054] S2 . After the plasma generation phase ends and the ejector device 2 lifts the wafer 3 on the carrier device 1 , the grounding switch 102 is controlled to be closed.

[0055] By controlling the ground switch 102 to open before the plasma generation phase of the semiconductor process begins, the lower electrode in the carrier device 1 can be disconnected from the ground. Therefore, during the plasma generation phase, the negative charge accumulated in the lower electrode will not be discharged. The lower electrode and wafer 3 will simultaneously accumulate negative charge, so that the lower electrode and wafer 3 are negatively charged as a whole, and the potential is basically the same. This can avoid a potential difference between wafer 3 and the lower electrode, and no electrostatic adsorption will occur between the two. As a result, when the ejector device 2 lifts the wafer on the carrier device 1, the wafer 3 will not be offset due to electrostatic adsorption, thereby effectively improving the repeatable transmission accuracy of wafer 3 and ensuring that the AWC (wafer automatic correction) results meet the requirements. On this basis, after the plasma generation phase ends and the ejector device 2 lifts the wafer 3 on the carrier device 1, controlling the ground switch 102 to close can ground the lower electrode, thereby allowing the accumulated charge in the lower electrode to be discharged, avoiding the problem of sparking inside the lower electrode.

[0056] In some embodiments, as Figure 9 As shown, the control unit in the lower electrode system 100 is further configured to execute the following step S3 after the above step S2:

[0057] Step S3 : After lifting the wafer 3 on the carrier device 1 , the wafer 3 on the ejector device 2 is grounded by the ejector device 2 .

[0058] Further optionally, the control unit is further configured to ground the wafer 3 on the ejector device 2 while the lower electrode is grounded. In this way, the negative charges in the wafer 3 and the lower electrode can be discharged synchronously, thereby always avoiding a potential difference between the wafer 3 and the lower electrode, and solving the problem of particles caused by the accumulated charge on the wafer 3 and the problem of sparks caused by the accumulated charge on the lower electrode.

[0059] In some embodiments, before step S1, in order to fix the wafer 3 on the carrier 1 (i.e., the base plate 11), the control unit is further configured to:

[0060] Before placing the wafer 3 on the carrier 1 , controlling the chamber pressure to reach a first pressure value;

[0061] After the wafer 3 is placed on the carrier device 1, process gas is introduced into the process chamber 200, and the chamber pressure is controlled to reach a second pressure value; the second pressure value is greater than the first pressure value to form a pressure difference between the upper surface and the lower surface of the wafer 3, thereby fixing the wafer 3 on the carrier device 1.

[0062] In some embodiments, the first pressure value ranges from 70 mTorr to 100 mTorr, for example.

[0063] In some embodiments, the second pressure value ranges from 1 Torr to 3 Torr, for example.

[0064] Before the RF power supply is turned on, the chamber pressure of the process chamber 200 is first controlled at a first pressure value by vacuuming, and then the wafer 3 is placed on the base plate 11, and process gas is introduced into the process chamber 200 to increase the chamber pressure of the process chamber 200 to a second pressure value. At this time, there is a pressure difference between the upper surface of the wafer 3 and the lower surface of the wafer 3, that is, the pressure on the upper surface side of the wafer 3 is greater than the pressure on the lower surface side, so that the wafer 3 can be fixed on the base plate 11. It is easy to understand that during this process, the gas in the process chamber 200 also slowly flows into the gap between the lower surface of the wafer 3 and the base 11, causing the pressure on the side of the lower surface of the wafer 3 to slowly increase, and the pressure difference between the upper surface of the wafer 3 and the lower surface of the wafer 3 gradually decays. However, since this is a slow process, there is enough time to fix the wafer 3 on the base 11 while the RF power is turned on, and by adjusting the above-mentioned pressure range, it can be ensured that before the ejector device 2 lifts the wafer 3 on the base 11, the above-mentioned pressure difference decays to zero or close to zero, so as to ensure that the ejector device 2 can normally lift the wafer 3. From the above, it can be seen that the chuck 12 does not need to be equipped with an additional structure to fix the wafer 3, such as an electrostatic chuck, and can fix the wafer 3 only by using the above-mentioned pressure difference.

[0065] Exemplarily, the control unit may be a host computer or a slave computer.

[0066] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A lower electrode system, applied to semiconductor process equipment, comprising a carrier device and a ejector device, wherein the ejector device is used to lift a wafer on the carrier device or place a wafer on the carrier device, characterized in that: The device further comprises a grounding device, the grounding device comprising a grounding circuit, a grounding switch, and a control unit, wherein the grounding circuit is electrically connected to the lower electrode in the carrier device through the grounding switch, and is configured to ground the lower electrode when the grounding switch is closed; The control unit is used to control the grounding switch to be disconnected before the plasma generation phase of the semiconductor process begins, and to control the grounding switch to be closed after the plasma generation phase ends and the ejector device lifts the wafer on the carrier device.

2. The lower electrode system according to claim 1, characterized in that The ejector device is configured to lift the wafer on the carrier device and then ground the wafer.

3. The lower electrode system according to claim 2, characterized in that The ejector device is configured to be electrically connected to the grounding switch through the lower electrode, so as to ground the wafer on the ejector device while the control unit controls the grounding switch to be closed.

4. The lower electrode system according to claim 2, characterized in that The ejector device includes a plurality of conductive ejectors and a plurality of conductive ejector bellows, wherein a plurality of through holes are provided in the carrying device and are spaced apart along the circumference of the carrying device, and the plurality of ejectors correspond one to one and are lifted and lowered through the plurality of through holes; the plurality of ejector bellows are sleeved on the plurality of ejectors in a one-to-one correspondence, and the upper end of each ejector bellows is sealed and electrically connected to the carrying device; the lower end of each ejector bellows is sealed and electrically connected to the corresponding ejector.

5. The lower electrode system according to claim 1, characterized in that It also includes a radio frequency feeding device, which is electrically connected to the lower electrode and is used to be electrically connected to a radio frequency power supply through a matching device to load radio frequency power to the lower electrode.

6. The lower electrode system according to any one of claims 1 to 5, characterized in that: The grounding circuit includes a circuit for connecting between the lower electrode and the ground, and a grounding resistor connected in series to the grounding circuit; the grounding switch is connected in series to the grounding circuit and is located on a side of the grounding resistor close to the lower electrode.

7. The lower electrode system according to claim 6, characterized in that The resistance of the grounding resistor is greater than or equal to 5 MΩ and less than or equal to 20 MΩ.

8. A semiconductor process equipment, comprising a process chamber, characterized in that: It also includes a lower electrode system, the lower electrode system includes a carrier device, a ejector device and a grounding device, the ejector device is used to lift the wafer on the carrier device or place the wafer on the carrier device; The grounding device includes a grounding circuit, a grounding switch, and a control unit, wherein the grounding circuit is electrically connected to the lower electrode in the carrying device through the grounding switch, and is used to ground the lower electrode when the grounding switch is closed; The control unit includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, a lower electrode system control method is implemented, wherein the lower electrode system control method includes: Before the plasma generation phase of the semiconductor process begins, controlling the ground switch to be open; After the plasma generation phase ends and the ejector device lifts the wafer on the carrier device, the grounding switch is controlled to be closed.

9. The semiconductor process equipment according to claim 8, wherein: The control unit is further configured to: Before placing the wafer on the carrier, controlling the chamber pressure to reach a first pressure value; After the wafer is placed on the carrier, process gas is introduced into the process chamber, and the chamber pressure is controlled to reach a second pressure value; the second pressure value is greater than the first pressure value to form a pressure difference between the upper surface and the lower surface of the wafer, thereby fixing the wafer on the carrier.

10. The semiconductor process equipment according to claim 8, wherein: The semiconductor process equipment includes crystal edge etching equipment.

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