Source-drain interconnection method of self-aligned transistor, self-aligned transistor and device

Abstract

The present application provides a method for source-drain interconnection of a self-aligned transistor, a self-aligned transistor, and a device. The method includes: forming an active structure on a semiconductor substrate, where the active structure includes a first active structure and a second active structure; based on the first active structure, sequentially forming a first source-drain structure, a first interlayer dielectric layer, and a first source-drain metal, and the first interlayer dielectric layer wraps the first active structure, the first source-drain structure, and the first source-drain metal; flipping the wafer and removing the semiconductor substrate; based on the second active structure, sequentially forming a second source-drain structure, a second interlayer dielectric layer, and a second source-drain metal, and the second interlayer dielectric layer wraps the second active structure, the second source-drain structure, and the second source-drain metal; wherein, the first source-drain metal and the second source-drain metal are connected through an interconnect via structure, and the interconnect via structure penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer. Through the present application, the difficulty in controlling the etching time in the source-drain interconnection scheme can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and particularly to a source-drain interconnection method for self-aligned transistors, self-aligned transistors, and devices. Background Art

[0002] At present, with the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development. By integrating two or more layers of transistors in the vertical space, stacked transistors can further improve the transistor integration density, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] When preparing stacked transistors using the traditional sequential scheme, there are the following technical difficulties: when solving the problem of source-drain interconnection between the upper and lower layers of transistors, it is necessary to precisely control the etching time to ensure the depth of the source-drain contact metal of the lower layer of transistors. Summary of the Invention

[0004] This application provides a source-drain interconnection method for self-aligned transistors, self-aligned transistors, and devices to reduce the difficulty of controlling the etching time in the source-drain interconnection scheme.

[0005] In a first aspect, an embodiment of this application provides a source-drain interconnection method for self-aligned transistors. The method includes: forming an active structure on a semiconductor substrate, where the active structure includes a first active structure and a second active structure; based on the first active structure, sequentially forming a first source-drain structure, a first interlayer dielectric layer, and a first source-drain metal, where the first interlayer dielectric layer wraps the first active structure, the first source-drain structure, and the first source-drain metal; flipping the wafer and removing the semiconductor substrate; based on the second active structure, sequentially forming a second source-drain structure, a second interlayer dielectric layer, and a second source-drain metal, where the second interlayer dielectric layer wraps the second active structure, the second source-drain structure, and the second source-drain metal; wherein, the first source-drain metal and the second source-drain metal are connected through an interconnection via structure, and the interconnection via structure penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer.

[0006] In some possible implementation manners, based on the first active structure, sequentially forming a first source-drain structure, a first interlayer dielectric layer, and a first source-drain metal includes: etching a part of the first active structure to form the first source-drain structure; depositing a semiconductor material on the first active structure and the first source-drain structure to form the first interlayer dielectric layer; etching a first part of the first interlayer dielectric layer to form the first source-drain metal; etching a second part of the first interlayer dielectric layer to form a first interconnection via structure, and the first interconnection via structure is connected to the first source-drain metal.

[0007] In some possible embodiments, based on the second active structure, a second source-drain structure, a second interlayer dielectric layer, and a second source-drain metal are sequentially formed, including: etching a part of the second active structure to form the second source-drain structure; depositing a semiconductor material on the second active structure and the second source-drain structure to form the second interlayer dielectric layer; etching a first part of the second interlayer dielectric layer to form the second source-drain metal; etching a second part of the second interlayer dielectric layer until it communicates with the first interconnect via structure to form a second interconnect via structure, and the second interconnect via structure and the first interconnect via structure form an interconnect via structure.

[0008] In some possible embodiments, based on the first active structure, a first source-drain structure, a first interlayer dielectric layer, and a first source-drain metal are sequentially formed, including: etching a part of the first active structure to form the first source-drain structure; depositing a semiconductor material on the first active structure and the first source-drain structure to form the first interlayer dielectric layer; etching a third part of the first interlayer dielectric layer to form the first source-drain metal.

[0009] In some possible embodiments, based on the second active structure, a second source-drain structure, a second interlayer dielectric layer, and a second source-drain metal are sequentially formed, including: etching a part of the second active structure to form the second source-drain structure; depositing a semiconductor material on the second active structure and the second source-drain structure to form the second interlayer dielectric layer; etching a third part of the second interlayer dielectric layer to form the second source-drain metal; etching a fourth part of the second interlayer dielectric layer until it penetrates the first interlayer dielectric layer to form an interconnect via structure.

[0010] In some possible embodiments, the interconnect via structure is located on one side of the active structure; or, the interconnect via structure is located on both sides of the active structure; or, the interconnect via structure is located in the middle of the active structure.

[0011] In some possible embodiments, before flipping the wafer and removing the semiconductor substrate, the above method further includes: forming a first transistor based on the first interlayer dielectric layer; bonding the first transistor to a carrier wafer.

[0012] In some possible embodiments, after sequentially forming a second source-drain structure, a second interlayer dielectric layer, and a second source-drain contact structure based on the second active structure, the above method further includes: forming a second transistor based on the second interlayer dielectric layer, and the second transistor is self-aligned with the first transistor in the vertical direction of the semiconductor substrate.

[0013] In a second aspect, an embodiment of the present application provides a self-aligned transistor, including: a first transistor; a second transistor, which is disposed opposite to the first transistor; wherein, a first source-drain metal of the first transistor is connected to a second source-drain metal of the second transistor through an interconnection via structure, and the interconnection via structure penetrates through a first interlayer dielectric layer of the first transistor and a second interlayer dielectric layer of the second transistor.

[0014] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: the self-aligned transistor as described in the above embodiment.

[0015] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and the semiconductor device as described in the above embodiment, and the semiconductor device is disposed on the circuit board.

[0016] In the present application, the interconnection via structure in the self-aligned transistor is respectively connected to the first source-drain metal and the second source-drain metal, and the interconnection between the first source-drain structure and the second source-drain structure can be realized;

[0017] Furthermore, since the interconnection via structure penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer, the etching can be stopped at the source-drain metal by means of selective etching, thereby reducing the difficulty of controlling the etching time in the source-drain interconnection scheme.

[0018] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0020] Figure 1 It is a schematic diagram of the first implementation process of the source-drain interconnection method of the self-aligned transistor in the embodiment of the present application;

[0021] Figure 2 It is a schematic diagram of the first structure of the self-aligned transistor in the embodiment of the present application;

[0022] Figure 3 It is a schematic diagram of the first structure of the interconnection via structure in the embodiment of the present application;

[0023] Figures 4A to 4E It is a schematic diagram of the first manufacturing process of the self-aligned transistor in the embodiment of the present application;

[0024] Figure 5 It is a schematic diagram of the second structure of the self-aligned transistor in the embodiment of the present application;

[0025] Figure 6 This is the second structural schematic diagram of the interconnected via structure in the embodiment of the present application;

[0026] Figure 7 This is the third structural schematic diagram of the self-aligned transistor in the embodiment of the present application;

[0027] Figure 8 This is the fourth structural schematic diagram of the self-aligned transistor in the embodiment of the present application;

[0028] Figure 9 This is the fifth structural schematic diagram of the self-aligned transistor in the embodiment of the present application;

[0029] Figure 10 This is the sixth structural schematic diagram of the self-aligned transistor in the embodiment of the present application;

[0030] In the above figures:

[0031] 10. Self-aligned transistor; 11. First transistor; 111. First active structure; 112. First source / drain structure; 113. First source / drain metal; 114. First interlayer dielectric layer; 115. First gate structure; 116. First spacer; 117. First metal interconnect layer; 12. Second transistor; 121. Second active structure; 122. Second source / drain structure; 123. Second source / drain metal; 124. Second interlayer dielectric layer; 125. Second gate structure; 126. Second spacer; 127. Second metal interconnect layer; 13. Interconnected via structure; 131. First interconnected via structure; 132. Second interconnected via structure; 14. Shallow trench isolation layer; 15. First insulating layer; 16. Carrier wafer; 21. Semiconductor substrate; 22. Fin structure; 23. Shallow trench isolation structure; 241. First dummy gate structure; 242. Second dummy gate structure. Detailed Description of the Invention

[0032] Here, exemplary embodiments will be described in detail, and examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application.

[0033] At present, with the continuous deepening of Moore's Law, after the technology node of gate-all-around FET (GAA), continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development. By three-dimensional transistor stacking, stacked transistors can achieve the integration of two or more layers of transistors in the vertical space, which helps to further improve the transistor integration density and circuit performance, and is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0034] In one embodiment, there are two schemes for manufacturing a stacked transistor, the first is a monolithic scheme, and the second is a sequential scheme.

[0035] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0036] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding a wafer on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, the temperature needs to be strictly controlled during the thermal process of processing the upper transistor to avoid affecting the lower transistor and the interconnection line. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonded wafer; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy; (4) When solving the problem of source-drain interconnection between the upper and lower transistors, the etching time needs to be accurately controlled to ensure the depth of the source-drain contact metal of the lower transistor; (5) In the layout design, the position of the active structure (such as the fin structure) in the transistor is fixed, which will limit the width of the source-drain metal, resulting in a large resistance of the source-drain metal, which is not conducive to the performance of the circuit.

[0037] In order to solve the above technical problems, an embodiment of the present application provides a source-drain interconnection method of a self-aligned transistor to reduce the difficulty of controlling the etching time for manufacturing an interconnection through-hole structure.

[0038] In the embodiments of the present application, the self-aligned transistor can be applied to semiconductor devices such as memory and processor.

[0039] In one embodiment, a self-aligned transistor may include at least two transistors. For example, taking the first transistor and the second transistor as an example. The first transistor and the second transistor are arranged back to back. Among them, the first active structure in the first transistor and the second active structure in the second transistor are formed through the same process. At this time, it can be understood that the first transistor and the second transistor share the same active structure, and the first active structure and the second active structure are self-aligned.

[0040] In the embodiments of the present application, the first transistor and the second transistor in the self-aligned transistor may be of the same type of transistor, such as any one of the following: fin field-effect transistor, gate-all-around transistor, and planar transistor.

[0041] Figure 2 For a self-aligned transistor composed of fin field-effect transistors, the preparation method provided in the embodiments of the present application will be described below in conjunction with Figure 2 the structure of the self-aligned transistor shown.

[0042] Figure 1 FIG. is a schematic diagram of the first implementation process of the source-drain interconnection method of the self-aligned transistor in the embodiments of the present application. Refer to Figure 1 shown, the source-drain interconnection method of the above self-aligned transistor may include:

[0043] S101, forming an active structure on a semiconductor substrate, the active structure including a first active structure and a second active structure.

[0044] Among them, the semiconductor substrate in the embodiments of the present application may be a silicon (Si) substrate, or a silicon-on-insulator (SOI) substrate. Of course, it may also be a substrate made of other semiconductor materials. The embodiments of the present application do not make specific limitations on this.

[0045] It can be understood that when the types of self-aligned transistors are different, the settings of the substrates are also correspondingly different. For example, when the self-aligned transistor is a fin field-effect transistor or a planar transistor, the semiconductor substrate may be a single-layer structure, that is, a substrate made of a semiconductor material; when the self-aligned transistor is a gate-all-around transistor, the semiconductor substrate may be a stacked structure, that is, a stack obtained by laminating Si material and silicon germanium (SiGe) material.

[0046] In some embodiments, when the self-aligned transistor is a fin field-effect transistor, the above S101 may include: etching the semiconductor substrate to form a plurality of fin structures; the upper half of the fin structure is the first active structure, and the lower half of the fin structure is the second active structure.

[0047] In some other embodiments, when the self-aligned collective transistor is a fully-depleted surround gate transistor, the above S101 may include: etching a semiconductor substrate to form a columnar structure, wherein the semiconductor substrate is formed by alternately depositing silicon layers and silicon germanium layers; the upper half of the columnar structure is a first active structure, and the lower half of the columnar structure is a second active structure.

[0048] In still some other embodiments, when the self-aligned collective transistor is a planar transistor, the above S101 may include: etching a semiconductor substrate to form a block structure; the upper half of the block structure is a first active structure, and the lower half of the block structure is a second active structure.

[0049] In the embodiments of the present application, since the self-aligned transistor includes two transistors (i.e., the first transistor and the second transistor), and the first active structure of the first transistor and the second active structure of the second transistor are formed by the same etching process, therefore, when etching the semiconductor substrate, a relatively large etching depth can be adopted. For example, the height of the fin structure (which may also be a columnar structure or a block structure) obtained by etching can be greater than 100 nm. It should be noted that the height of the fin structure can be set according to actual situations, and the embodiments of the present application do not make specific limitations thereto.

[0050] In some embodiments, after the active structure, the above method may further include: filling an oxide above the active structure to form a shallow trench isolation (STI) structure. The height of the shallow trench isolation structure is greater than the height of the active structure.

[0051] In the embodiments of the present application, the oxide for forming the shallow trench isolation structure may be any one of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon carbon oxide (SiCO), etc.

[0052] In some embodiments, after forming the shallow trench isolation structure, the above method may further include: performing chemical-mechanical planarization (CMP) treatment on the shallow trench isolation structure.

[0053] In the embodiments of the present application, performing chemical-mechanical planarization treatment on the shallow trench isolation structure can make the corrosion depths corresponding to different regions of the shallow trench isolation structure the same when etching the shallow trench isolation structure subsequently, so that the top heights of the exposed active structures are the same.

[0054] In some embodiments, after forming the shallow trench isolation structure, the above method may further include: removing a part of the shallow trench isolation structure by etching to expose the first active structure.

[0055] It can be understood that, in order to perform subsequent fabrication of the first transistor on the first active structure, such as fabricating the first source / drain structure, etc., the upper half of the shallow trench isolation structure can be etched first to expose the first active structure for subsequent fabrication processes.

[0056] It should be noted that the etching process mentioned in the embodiments of the present application can include any one of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal process, and the embodiments of the present application do not limit this.

[0057] In the embodiments of the present application, the solvent used for etching the shallow trench isolation structure can be: DHF solution or BOE solution. The solvent adopted in the etching process in the embodiments of the present application can be selected according to the actual situation, and is not limited to the above DHF solution or BOE solution.

[0058] In some embodiments, after exposing the first active structure, ion implantation can be performed at the connection between the first active structure and the second active structure to form an electrical isolation layer, and the electrical isolation layer is used to electrically isolate the first active structure and the second active structure.

[0059] Among them, the ions for ion implantation include P-type ions, N-type ions, or oxygen ions. The P-type ions can be one of the following: boron (B), gallium (Ga), aluminum (Al). The N-type ions can be one of the following: phosphorus (P), arsenic (As), antimony (Sb).

[0060] S102, based on the first active structure, sequentially form a first source / drain structure, a first interlayer dielectric layer, and a first source / drain metal, and the first interlayer dielectric layer wraps the first active structure, the first source / drain structure, and the first source / drain metal.

[0061] It can be understood that the removal of the shallow trench isolation structure and the exposure of the first active structure can provide the gate region and the source / drain grooves of the first transistor. Depositing a semiconductor material in the gate region of the first transistor can obtain the first dummy gate structure of the first transistor. Performing source / drain epitaxial growth in the source / drain grooves of the first transistor can obtain the first source / drain structure. Depositing a semiconductor material above the first active structure can obtain the first interlayer dielectric layer. Depositing a metal material above the first source / drain structure can obtain the first source / drain metal.

[0062] In some embodiments, the method for forming the first dummy gate structure can include: lithographically opening the gate region of the first transistor and depositing a semiconductor material (such as polysilicon) in the gate region to form the first dummy gate structure of the first transistor.

[0063] In some embodiments, after forming the first dummy gate structure, spacers can be formed on both sides of the first dummy gate structure.

[0064] In some possible embodiments, the above S102 may include: etching a part of the first active structure to form a first source-drain structure; depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; etching a first part of the first interlayer dielectric layer to form a first source-drain metal; etching a second part of the first interlayer dielectric layer to form a first interconnect via structure that is connected to the first source-drain metal.

[0065] In some embodiments, etching a part of the first active structure to form a first source-drain structure may include: removing a part of the first active structure by etching to provide a source-drain groove of the first transistor. Using a spacer as a mask, a strained material such as silicon germanium or silicon carbide is formed in the source-drain groove by selective epitaxial growth to fill the source-drain groove of the first transistor, and then a first source-drain structure is formed on the above strained material through a heavy doping process.

[0066] It should be noted that for ease of description, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, the source-drain groove, etc. are all similar to the first source-drain structure, and the "source-drain" therein is an abbreviation for "source and / or drain".

[0067] In some embodiments, depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer may include: depositing an insulating material (such as silicon dioxide (SiO2)) above the first active structure and the first source-drain structure to form a first interlayer dielectric layer; the first interlayer dielectric layer may cover the first active structure and the first source-drain structure.

[0068] In some embodiments, etching a first part of the first interlayer dielectric layer to form a first source-drain metal; etching a second part of the first interlayer dielectric layer to form a first interconnect via structure that is connected to the first source-drain metal may include: etching the part of the first interlayer dielectric layer located above the first source-drain structure (i.e., the first part of the first interlayer dielectric layer) until the upper surface of the first source-drain structure is exposed to form a first source-drain metal groove. Depositing a metal material in the first source-drain metal groove may obtain a first source-drain metal. Then, etching the part of the first interlayer dielectric layer located on the side of the first source-drain groove (i.e., the second part of the first interlayer dielectric layer), the etching depth may be lower than the epitaxy of the first source-drain structure to form a trough-shaped hole, and depositing the same metal material as the first source-drain metal in the trough-shaped hole may obtain a first interconnect via structure.

[0069] It should be noted that the preparation sequence of first preparing the first source / drain metal and then preparing the first interconnect via structure in the above embodiments is only an example. It is also possible to first prepare the first interconnect via structure and then prepare the first source / drain metal, or to prepare the first source / drain metal and the first interconnect via structure simultaneously. The embodiments of the present application do not make specific limitations in this regard. The prepared first source / drain metal and the first interconnect via structure are interconnected, and can be understood as an integral structure of the first source / drain metal and the first interconnect via structure.

[0070] In some other possible implementation manners, during the process of manufacturing the first transistor, the first interconnect via structure in the first transistor may not be manufactured. In the case of not manufacturing the first interconnect via structure, S102 may include: etching a part of the first active structure to form a first source / drain structure; depositing a semiconductor material on the first active structure and the first source / drain structure to form a first interlayer dielectric layer; etching a third part of the first interlayer dielectric layer to form a first source / drain metal.

[0071] It should be noted that the processes of forming the first source / drain structure, the first interlayer dielectric layer, and the first source / drain metal are the same as those in the above embodiments, and the embodiments of the present application will not elaborate on this.

[0072] S103, flip the wafer and remove the semiconductor substrate.

[0073] It can be understood that after forming the first source / drain structure, the first interlayer dielectric layer, and the first source / drain metal, other structures in the first transistor can be prepared according to standard steps. After the first transistor is manufactured, the first transistor is flipped, and the semiconductor substrate is removed so that the second active structure is placed upward, which is convenient for subsequent manufacturing of the second transistor.

[0074] In some embodiments, before S103, the above method may further include: forming a first transistor based on the first interlayer dielectric layer; bonding the first transistor to a carrier wafer.

[0075] It can be understood that post-processes (such as deposition of interconnection dielectric, formation of metal lines, formation of lead pads, etc.) are performed on the first interlayer dielectric layer to form the first metal interconnection layer of the first transistor. An insulating material (such as silicon oxide) is deposited on the first metal interconnection layer to form a first insulating layer, and the first insulating layer is bonded to the carrier wafer.

[0076] In the embodiments of the present application, the bonded carrier wafer can provide physical support for the flipped first transistor after flipping, effectively preventing the first transistor from being broken by external forces during the process of manufacturing the second transistor.

[0077] In some embodiments, before forming the first metal interconnect layer, the above method may further include: removing the first dummy gate structure by etching to expose the gate region of the first transistor, and depositing a metal material in the gate region of the first transistor to form the first gate structure of the first transistor.

[0078] In some embodiments, after removing the semiconductor substrate, the above method may further include: removing a part of the shallow trench isolation structure by etching to expose the second active structure.

[0079] It can be understood that, in order to perform subsequent fabrication of the second transistor on the second active structure, such as fabricating the second source / drain structure, etc., the lower half of the shallow trench isolation structure can be etched first so that the second active structure is exposed for subsequent fabrication processes.

[0080] It should be noted that when etching the lower half of the shallow trench isolation structure, a certain thickness of the shallow trench isolation structure can be retained, and the retained shallow trench isolation structure can be used to isolate the first transistor and the second transistor.

[0081] S104, based on the second active structure, sequentially form the second source / drain structure, the second interlayer dielectric layer, and the second source / drain metal, and the second interlayer dielectric layer wraps the second active structure, the second source / drain structure, and the second source / drain metal.

[0082] Wherein, the first source / drain metal and the second source / drain metal are connected through an interconnection via structure, and the interconnection via structure penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer.

[0083] It can be understood that the removal of the shallow trench isolation structure and the exposure of the second active structure can provide the gate region and the source / drain recess of the second transistor. Depositing a semiconductor material in the gate region of the second transistor can obtain the second dummy gate structure of the second transistor. Performing source / drain epitaxial growth in the source / drain recess of the second transistor can obtain the second source / drain structure. Depositing a semiconductor material above the second active structure can obtain the second interlayer dielectric layer. Depositing a metal material above the second source / drain structure can obtain the second source / drain metal.

[0084] In some embodiments, the method of forming the second dummy gate structure may include: patterning to open the gate region of the second transistor, and depositing a semiconductor material (such as polysilicon) in the gate region to form the first dummy gate structure of the second transistor.

[0085] In some embodiments, after forming the second dummy gate structure, spacers can be formed on both sides of the second dummy gate structure.

[0086] In some possible implementation manners, the above S104 may include: etching a part of the second active structure to form a second source-drain structure; depositing a semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; etching a first part of the second interlayer dielectric layer to form a second source-drain metal; etching a second part of the second interlayer dielectric layer until it communicates with the first interconnection via structure to form a second interconnection via structure, and the second interconnection via structure and the first interconnection via structure form an interconnection via structure.

[0087] In some embodiments, etching a part of the second active structure to form a second source-drain structure may include: removing a part of the second active structure by etching to provide a source-drain groove of the second transistor. Using the spacer as a mask, a strained material such as silicon germanium or silicon carbide is formed in the source-drain groove by selective epitaxial growth to fill the source-drain groove of the second transistor, and then a second source-drain structure is formed on the above strained material through a heavy doping process.

[0088] In some embodiments, depositing a semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer may include: depositing an insulating material (such as silicon dioxide) above the second active structure and the second source-drain structure to form a second interlayer dielectric layer; the second interlayer dielectric layer may cover the second active structure and the second source-drain structure.

[0089] It should be noted that the first interlayer dielectric layer and the second interlayer dielectric layer in the embodiments of the present application may be formed of the same material or different materials.

[0090] In some embodiments, etching a first part of the second interlayer dielectric layer to form a second source-drain metal; etching a second part of the second interlayer dielectric layer until it communicates with the first interconnection via structure to form a second interconnection via structure, and the second interconnection via structure and the first interconnection via structure form an interconnection via structure may include: etching a part of the second interlayer dielectric layer located above the second source-drain structure (i.e., the first part of the second interlayer dielectric layer) until the upper surface of the second source-drain structure is exposed to form a second source-drain metal groove. Depositing a metal material in the second source-drain metal groove can obtain a second source-drain metal. Then, etching a part of the second interlayer dielectric layer located on the side of the second source-drain groove (i.e., the second part of the second interlayer dielectric layer), the second part of the second interlayer dielectric layer is aligned with the second part of the above first interlayer dielectric layer, and when etching reaches a position where it communicates with the above first interconnection via structure, stop etching to form a trough-shaped hole, and deposit the same metal material as the second source-drain metal in the trough-shaped hole to obtain a second interconnection via structure.

[0091] In the embodiment of the present application, since the first interconnection via structure is connected to the first source / drain metal, the second interconnection via structure is connected to the second source / drain metal, and the second interconnection via structure is connected to the first interconnection via structure, this enables the interconnection between the first source / drain metal and the second source / drain metal.

[0092] It should be noted that the above solution for preparing the second interconnection via structure corresponds to the solution for preparing the first interconnection via structure. The first interconnection via structure and the second interconnection via structure together form the interconnection via structure in the self-aligned transistor, realizing the interconnection between the first source / drain metal and the second source / drain metal.

[0093] It should be noted that the preparation sequence of first preparing the second source / drain metal and then preparing the second interconnection via structure in the above embodiment is only an example. It is also possible to first prepare the second interconnection via structure and then prepare the second source / drain metal, or to prepare the second source / drain metal and the second interconnection via structure simultaneously. The embodiment of the present application does not make specific limitations in this regard. The prepared second source / drain metal and the second interconnection via structure are connected to each other, and can be understood as an integral structure of the second source / drain metal and the second interconnection via structure.

[0094] In some other possible implementation manners, during the process of preparing the first transistor, the first interconnection via structure in the first transistor may not be prepared. In the case of not preparing the first interconnection via structure, S104 above may include: etching a part of the second active structure to form a second source / drain structure; depositing a semiconductor material on the second active structure and the second source / drain structure to form a second interlayer dielectric layer; etching a third part of the second interlayer dielectric layer to form a second source / drain metal; etching a fourth part of the second interlayer dielectric layer until it penetrates the first interlayer dielectric layer to form an interconnection via structure.

[0095] It should be noted that the processes of forming the second source / drain structure, the second interlayer dielectric layer, and the second source / drain metal are the same as those in the above embodiment, and the embodiment of the present application will not elaborate on this.

[0096] In some embodiments, etching the fourth part of the second interlayer dielectric layer until it penetrates the first interlayer dielectric layer to form an interconnection via structure may include: etching the part of the second interlayer dielectric layer located on the side of the second source / drain metal groove (i.e., the fourth part of the second interlayer dielectric layer) until reaching the side of the first source / drain metal, then stopping etching to form a groove-shaped hole, and depositing a metal material the same as the second source / drain metal in the groove-shaped hole to obtain the interconnection via structure. The interconnection via structure penetrates the first interlayer dielectric layer and the second interlayer dielectric layer.

[0097] In some possible implementation manners, the interconnection via structure is located on one side of the active structure; or, the interconnection via structure is located on both sides of the active structure; or, the interconnection via structure is located in the middle of the active structure.

[0098] It can be understood that for fin field effect transistors, the active structure is a plurality of fin structures, and the interconnection through-hole structure can be located on one side of the plurality of fin structures; it can also be located on both sides of the plurality of fin structures; when the intervals between the plurality of fin structures are large and the source and drain epitaxy are not fused together, the interconnection through-hole structure can be located between adjacent source and drain (it can also be understood that the interconnection through-hole structure can be located between the left fin structure and the right fin structure). For all-around gate transistors, the active structure is a nanosheet structure arranged at intervals, and the interconnection through-hole structure can be located on one side of the nanosheet structure; it can also be located on both sides of the nanosheet structure. For planar transistors, the active structure is a block structure, and the interconnection through-hole structure can be located on one side of the block structure; it can also be located on both sides of the block structure.

[0099] In some other possible implementations, during layout design, the position of the active structure can be biased toward the left or right side of the self-aligned transistor so that the active structure is not located in the middle of the semiconductor substrate; on the other side (i.e., the right or left side), an interconnection through-hole structure with a larger width is formed.

[0100] In the embodiment of the present application, moving the position of the active structure to one side can leave more space for the interconnection through-hole structure, increase the width of the interconnection through-hole structure, and thus reduce the resistance when the first source-drain metal and the second source-drain metal are interconnected.

[0101] In some possible implementations, after S104, the method may further include: forming a second transistor based on the second interlayer dielectric layer.

[0102] The second transistor is self-aligned with the first transistor in a vertical direction of the semiconductor substrate.

[0103] It can be understood that the back-end process (such as dielectric deposition between interconnect lines, metal line formation, lead pad formation, etc.) is performed on the second interlayer dielectric layer to form the second metal interconnect layer of the second transistor. At this point, the second transistor in the self-aligned transistor is completed.

[0104] In some embodiments, before forming the second metal interconnect layer, the method may further include: removing the second dummy gate structure by etching to expose the gate region of the second transistor, and depositing metal material in the gate region of the second transistor to form a second gate structure of the second transistor.

[0105] In the embodiments of the present application, the metal material of the first gate structure and the second gate structure can be any one of the following: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN). The materials of the first gate structure and the second gate structure can be selected according to the actual situation and are not limited to the metal materials listed above.

[0106] In the embodiments of the present application, the materials of the first gate structure and the second gate structure can be made of the same or different metal materials according to the actual situation, and the embodiments of the present application do not make specific limitations in this regard.

[0107] In some embodiments, before preparing the first gate structure, the above method may further include: depositing a semiconductor material on the surface of the first active structure to form a first gate dielectric layer of the first transistor, and the first gate dielectric layer is used to isolate the first active structure and the first gate structure.

[0108] In the embodiments of the present application, the preparation method of the second gate dielectric layer of the second transistor is the same as that of the first gate dielectric layer, and the embodiments of the present application will not elaborate on this.

[0109] It should be noted that the materials for preparing the first gate dielectric layer and the second gate dielectric layer can be the same or different, and the embodiments of the present application do not make specific limitations in this regard.

[0110] Next, taking the first transistor and the second transistor as fin field effect transistors as an example, the self-aligned transistor provided by the embodiments of the present application will be described. Figure 2 This is the first structural schematic diagram of the self-aligned transistor in the embodiments of the present application. Among them, Figure 2 in (a) is the top view of the self-aligned transistor. It should be noted that for the convenience of understanding, only the fin structure, gate structure, and source-drain structure are shown in the top view; (b) is the sectional view of the self-aligned transistor taken along the sectional direction of the source-drain structure (i.e., the A-A' direction); (c) is the sectional view of the self-aligned transistor taken along the sectional direction of the gate structure (i.e., the B-B' direction).

[0111] See Figure 2As shown, the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12. The active structure in the self-aligned transistor 10 is a plurality of fin structures. The fin structures are divided into upper and lower parts, denoted as the first part and the second part respectively. The first part serves as the first active structure 111 in the first transistor 11, and the second part serves as the second active structure 121 in the second transistor 12. The first source / drain metal 113 in the first transistor 11 and the second source / drain metal 123 in the second transistor 12 are interconnected through an interconnect via structure 13. A shallow trench isolation layer 14 is provided between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used to isolate the first transistor 11 and the second transistor 12.

[0112] Figure 3 This is the first schematic diagram of the interconnect via structure in the embodiment of the present application. Figure 3 Shown is a disassembly schematic diagram of the interconnect via structure 13, the first source / drain metal 113, and the second source / drain metal 123. Refer to Figure 3 As shown, the interconnect via structure 13 can include two parts. One part is the first interconnect via structure 131, and the first interconnect via structure 131 is connected to the first source / drain metal 113. The other part is the second interconnect via structure 132, and the second interconnect via structure 132 is connected to the second source / drain metal 123. The first interconnect via structure 131 and the second interconnect via structure 132 are connected.

[0113] It should be noted that Figure 3 the interconnect via structure 13 in Figure 2 corresponds to the interconnect via structure 13 in the self-aligned transistor shown in

[0114] In the embodiment of the present application, the first active structure 111 of the first transistor 11 and the second active structure 121 of the second transistor 12 are formed through the same etching process. In this way, self-alignment of the first transistor 11 and the second transistor 12 can be achieved.

[0115] Next, in combination with the above preparation method, the Figure 2 preparation process of the self-aligned transistor shown in Figure 2 The self-aligned transistor shown in Figures 4A to 4E can be prepared through the process shown in Figures 4A to 4E This is the first schematic diagram of the preparation process of the self-aligned transistor in the embodiment of the present application.

[0116] In one example, taking the first transistor 11 and the second transistor 12 as fin field-effect transistors, the first preparation process of the self-aligned transistor 10 with source / drain interconnection can include the following steps:

[0117] The first step: Provide a semiconductor substrate 21 (such as a Si substrate) (see Figure 4A (a) in

[0118] The second step: Etch the semiconductor substrate 21 to form a plurality of fin structures 22 (see Figure 4A (b) in

[0119] The third step: Fill an oxide above the fin structures 22 to form a shallow trench isolation structure 23 (see Figure 4A (c) in

[0120] The height of the shallow trench isolation structure 23 is greater than that of the fin structures 22, and it can cover the plurality of fin structures 22. Then, perform chemical mechanical planarization on the shallow trench isolation structure 23. Figure 4B (a) in

[0121] The fourth step: Use standard steps to etch a part of the shallow trench isolation structure 23 to expose the first part of the fin structure 22 (i.e., the first active structure 111) (see Figure 4B (b) in

[0122] The fifth step: Etch the first part of the fin structure 22 to form source / drain grooves of the first transistor 11. Then, lithographically open the gate region of the first transistor 11, deposit polysilicon at the gate region to form a first dummy gate structure 241. Form first spacer walls 116 on both sides of the first dummy gate structure 241 (see Figure 4B (b) in

[0122] The sixth step: Perform source / drain epitaxial growth at the source / drain grooves of the first transistor 11 to form a first source / drain structure 112. Then, deposit a semiconductor material above the first active structure 111 to form a first interlayer dielectric layer 114 (see Figure 4B (c) in

[0123] The seventh step: Remove a part of the first interlayer dielectric layer 114 by etching to form a first source / drain metal groove, deposit a metal material in the first source / drain metal groove to form a first source / drain metal 113. Then, through etching, form a first trench hole on the side of the first source / drain metal 113 (i.e., the side of the source / drain epitaxy), deposit a metal material in the first trench hole to form a first interconnect via structure 131, and the first interconnect via structure 131 is connected to the first source / drain metal 113 (see Figure 4C (a) in

[0124] The eighth step: Remove the first dummy gate structure 241, deposit a metal at the gate region to form a first gate structure 115. Then, perform back-end processes above the first interlayer dielectric layer 114 to form a first metal interconnect layer 117 (see Figure 4C (b) in

[0125] Step 9: Deposit an oxide above the first metal interconnect layer 117 to form the first insulating layer 15, and bond the first insulating layer 15 to the carrier wafer 16. Then, flip the first transistor 11 after bonding the carrier wafer 16 so that the semiconductor substrate 21 faces upward (see Figure 4C in (c)).

[0126] Step 10: Remove the semiconductor substrate 21 by etching, and etch the shallow trench isolation structure 23 to expose the second part of the fin structure 22 (see Figure 4D in (a)).

[0127] It should be noted that when etching the shallow trench isolation structure 23, control the etching depth to retain a certain thickness of the shallow trench isolation structure 23 as the shallow trench isolation layer 14. The shallow trench isolation layer 14 is used to isolate the first transistor 11 and the second transistor 12.

[0128] Step 11: Form a second source / drain structure 122, a second dummy gate structure 242, a second spacer 126, and a second interlayer dielectric layer 124 on the second part of the fin structure 22 (see Figure 4D in (b)) (for the specific fabrication process, refer to Step 5 and Step 6).

[0129] Step 12: Remove a part of the second interlayer dielectric layer 124 by etching to form a second source / drain metal groove, and deposit a metal material in the second source / drain metal groove to form the second source / drain metal 123. The first source / drain metal 113 and the second source / drain metal 123 have the same shape and are disposed opposite to each other. Then, through etching, form a second trench-shaped hole on the side of the second source / drain metal 123 (at the position aligned with the first interconnection via structure 131). When etching the second trench-shaped hole, stop etching until the second trench-shaped hole communicates with the first trench-shaped hole. Deposit a metal material in the second trench-shaped hole to form a second interconnection via structure 132, and the second interconnection via structure 132 is connected to the second source / drain metal 123 (see Figure 4D in (c)).

[0130] Step 13: Form a second gate structure 125 and a second metal interconnect layer 127 (for the specific fabrication process, refer to Step 8) (see Figure 4E ).

[0131] So far, the first transistor 11 and the second transistor 12, which are fin field-effect transistors, and the self-aligned transistor 10 in which the first source / drain metal 113 and the second source / drain metal 123 are interconnected through the first interconnection via structure 131 and the second interconnection via structure 132, are fabricated.

[0132] The above Figure 2The interconnection via structure 13 in the self-aligned transistor 10 shown is composed of two parts (i.e., the first interconnection via structure 131 and the second interconnection via structure 132). It can be understood that the above-mentioned Figure 2 The interconnection via structure 13 in the self-aligned transistor 10 shown is formed by two processes. In another embodiment, the interconnection via structure 13 in the self-aligned transistor 10 can be formed by one process. Figure 5 This is the second structural schematic diagram of the self-aligned transistor in the embodiment of the present application. Among them, Figure 5 In (a) is a top view of the self-aligned transistor. It should be noted that for ease of understanding, only the fin structure, gate structure, and source / drain structure are shown in the top view; (b) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the source / drain structure (i.e., the A-A' direction); (c) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the gate structure (i.e., the B-B' direction).

[0133] See Figure 5 As shown, the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12. The active structure in the self-aligned transistor 10 is multiple fin structures. The fin structures are divided into upper and lower parts, which are respectively denoted as the first part and the second part. The first part serves as the first active structure 111 in the first transistor 11, and the second part serves as the second active structure 121 in the second transistor 12. The first source / drain metal 113 in the first transistor 11 and the second source / drain metal 123 in the second transistor 12 are interconnected through the interconnection via structure 13. The interconnection via structure 13 is located on one side of the active structure. The two ends of the interconnection via structure 13 are respectively connected to the first source / drain metal 113 and the second source / drain metal 123. A shallow trench isolation layer 14 is provided between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used to isolate the first transistor 11 and the second transistor 12.

[0134] Figure 6 This is the second structural schematic diagram of the interconnection via structure in the embodiment of the present application. Figure 6 Shown is a disassembly schematic diagram of the interconnection via structure 13, the first source / drain metal 113, and the second source / drain metal 123. See Figure 6 As shown, the interconnection via structure 13 extends from the second source / drain metal 123 to the first source / drain metal 113. The two ends of the interconnection via structure 13 are respectively connected to the first source / drain metal 113 and the second source / drain metal 123.

[0135] Next, in combination with the above preparation method, the Figure 5 preparation process of the self-aligned transistor shown will be described.

[0136] The first step: Provide a silicon substrate.

[0137] Step 2: Etch the silicon substrate to form a plurality of fin structures.

[0138] Step 3: Form a shallow trench isolation structure (specifically, refer to Step 3 in the first manufacturing process of the self-aligned transistor).

[0139] Step 4: Expose the first part of the fin structure (i.e., the first active structure) (specifically, refer to Step 4 in the first manufacturing process of the self-aligned transistor).

[0140] Step 5: Form a first dummy gate structure and spacer (specifically, refer to Step 5 in the first manufacturing process of the self-aligned transistor).

[0141] Step 6: Form a first source / drain structure and a first interlayer dielectric layer (specifically, refer to Step 6 in the first manufacturing process of the self-aligned transistor).

[0142] Step 7: Remove a part of the first interlayer dielectric layer by etching to form a first source / drain metal groove, deposit a metal material in the first source / drain metal groove to form a first source / drain metal.

[0143] Step 8: Form a first gate structure and a first metal interconnect layer (specifically, refer to Step 8 in the first manufacturing process of the self-aligned transistor).

[0144] Step 9: Flip the wafer, remove the semiconductor substrate, and expose the second part of the fin structure (specifically, refer to Steps 9 and 10 in the first manufacturing process of the self-aligned transistor).

[0145] Step 10: Form a second source / drain structure, a second dummy gate structure, and a second interlayer dielectric layer on the second part of the fin structure (the specific manufacturing process can refer to Steps 5 and 6 in the first manufacturing process of the aligned transistor).

[0146] Step 11: Remove a part of the second interlayer dielectric layer by etching to form a second source / drain metal groove, deposit a metal material in the second source / drain metal groove to form a second source / drain metal. Among them, the first source / drain metal and the second source / drain metal have the same shape and are oppositely arranged. Then, through etching, a third trench-shaped hole is formed on the side of the second source / drain metal. When etching the third trench-shaped hole, the etching stops until the third trench-shaped hole contacts the first source / drain metal and the third trench-shaped hole penetrates the first interlayer dielectric layer. Deposit a metal material in the third trench-shaped hole to form an interconnection via structure, and both ends of the interconnection via structure are connected to the first source / drain metal and the second source / drain metal respectively.

[0147] Step 12: Form a second gate structure and a second metal interconnect layer (specifically, refer to Step 8 in the first manufacturing process of the self-aligned transistor).

[0148] So far, the first transistor 11 and the second transistor 12 are fin field-effect transistors, and the self-aligned transistor 10 in which the first source-drain metal 113 and the second source-drain metal 123 are interconnected through the interconnection via structure 13 is fabricated.

[0149] In some embodiments, Figure 7 FIG. is a schematic diagram of the third structure of the self-aligned transistor in the embodiments of the present application. Among them, Figure 7 FIG. (a) is a top view of the self-aligned transistor. It should be noted that for ease of understanding, only the fin structure, gate structure, and source-drain structure are shown in the top view; (b) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the source-drain structure (i.e., the A-A' direction); (c) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the gate structure (i.e., the B-B' direction).

[0150] See Figure 7 As shown, the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of fin structures. In the A-A' direction, the positions of the plurality of fin structures are biased towards one side (such as side A) of the semiconductor substrate. The fin structure is divided into upper and lower parts, which are respectively denoted as the first part and the second part. The first part serves as the first active structure 111 in the first transistor 11, and the second part serves as the second active structure 121 in the second transistor 12. The first source-drain metal 113 in the first transistor 11 and the second source-drain metal 123 in the second transistor 12 are interconnected through the interconnection via structure 13. Both ends of the interconnection via structure 13 are connected to the first source-drain metal 113 and the second source-drain metal 123 respectively. A shallow trench isolation layer 14 is provided between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used to isolate the first transistor 11 and the second transistor 12.

[0151] See Figure 7 and Figure 2 As shown, Figure 7 the interconnection via structure 13 in FIG. Figure 2 has a larger width compared to the interconnection via structure 13 in FIG. This is because Figure 7 the active structure of the self-aligned transistor 10 shown in FIG. is not disposed in the middle of the semiconductor substrate, but is biased towards one side of the semiconductor substrate, leaving a larger space for the interconnection via structure 13. Increasing the width of the interconnection via structure 13 can reduce the resistance when the first source-drain structure 112 and the second source-drain structure 122 are interconnected.

[0152] In some embodiments, during the fabrication of Figure 7In the process of the self-aligned transistor 10 shown, when etching the semiconductor substrate to form a fin structure, the position of the etching is controlled so that the position of the formed fin structure is biased towards one side of the semiconductor substrate, and a relatively large space is reserved on the other side of the semiconductor substrate for subsequent preparation of the interconnect via structure 13. When forming the interconnect via structure 13, a groove-shaped hole with a relatively large diameter is etched, and then a metal material is deposited in the groove-shaped hole to form the interconnect via structure 13. Figure 7 The preparation method of other structures in the self-aligned transistor 10 shown is the same as Figure 2 the preparation method of the self-aligned transistor 10 shown, which can be referred to the first preparation process of the self-aligned transistor 10, and the embodiments of the present application will not elaborate on this.

[0153] In some embodiments, Figure 8 This is the fourth schematic structural diagram of the self-aligned transistor in the embodiments of the present application. Among them, Figure 6 in (a) is the top view of the self-aligned transistor. It should be noted that for the sake of understanding, only the fin structure, the gate structure, and the source / drain structure are shown in the top view; (b) is the cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the source / drain structure (i.e., the A-A' direction); (c) is the cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the gate structure (i.e., the B-B' direction).

[0154] See Figure 8 As shown, the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of fin structures. The fin structure is divided into upper and lower parts, which are respectively denoted as the first part and the second part. The first part serves as the first active structure 111 in the first transistor 11, and the second part serves as the second active structure 121 in the second transistor 12. The first source / drain metal 113 in the first transistor 11 and the second source / drain metal 123 in the second transistor 12 are interconnected through the interconnect via structure 13. The interconnect via structure 13 is located on both sides of the active structure, and both ends of the interconnect via structure 13 are respectively connected to the first source / drain metal 113 and the second source / drain metal 123. A shallow trench isolation layer 14 is provided between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used to isolate the first transistor 11 and the second transistor 12.

[0155] In some embodiments, in the process of preparing Figure 8 the self-aligned transistor shown, when forming the interconnect via structure 13, groove-shaped holes are etched simultaneously on both sides of the active structure to form the interconnect via structure 13 located on both sides of the active structure. Figure 8 The preparation method of other structures in the self-aligned transistor 10 shown is the same as Figure 2The method for preparing the self-aligned transistor 10 shown is the same, and reference can be made to the first preparation process of the self-aligned transistor 10, which will not be elaborated in this embodiment of the present application.

[0156] In some embodiments, Figure 9 This is the sixth structural schematic diagram of the self-aligned transistor in the embodiment of the present application. Among them, Figure 9 In (a) is the top view of the self-aligned transistor. It should be noted that for ease of understanding, only the fin structure, gate structure, and source-drain structure are shown in the top view; (b) is the cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the source-drain structure (i.e., the A-A' direction); (c) is the cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the gate structure (i.e., the B-B' direction).

[0157] See Figure 9 As shown, the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is multiple fin structures. The fin structures are divided into upper and lower parts, respectively denoted as the first part and the second part. The first part serves as the first active structure 111 in the first transistor 11, and the second part serves as the second active structure 121 in the second transistor 12. The first source-drain metal 113 in the first transistor 11 and the second source-drain metal 123 in the second transistor 12 are interconnected through an interconnection via structure 13. The interconnection via structure 13 is located in the middle of adjacent source-drain epitaxies (which can be understood as being in the middle position of multiple fin structures), and both ends of the interconnection via structure 13 are connected to the first source-drain metal 113 and the second source-drain metal 123 respectively. A shallow trench isolation layer 14 is provided between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used to isolate the first transistor 11 and the second transistor 12.

[0158] In some embodiments, during the preparation of Figure 9 the self-aligned transistor 10 shown, when etching multiple fin structures on the semiconductor substrate, the spacing between the fin structures is increased, and when growing the source-drain epitaxy, the source-drain epitaxies are not fused together, and a position for the interconnection via structure 13 is reserved in the middle of the multiple fin structures and the source-drain epitaxy. When forming the interconnection via structure 13, a trench-shaped hole is etched in the middle of the active structure to form the interconnection via structure 13 located in the middle of the active structure. Figure 9 The preparation methods of other structures in the self-aligned transistor 10 shown are the same as those of the self-aligned transistor shown in Figure 2 The preparation method of the self-aligned transistor shown, and reference can be made to the first preparation process of the self-aligned transistor, which will not be elaborated in this embodiment of the present application.

[0159] In some embodiments, Figure 10 This is the sixth structural schematic diagram of the self-aligned transistor in the embodiment of the present application. Among them, Figure 10Figure (a) is a top view of the self-aligned transistor. It should be noted that for the sake of understanding, only the nanosheet layer structure, gate structure, and source-drain structure are shown in the top view; (b) is a cross-sectional view of the self-aligned transistor taken along the cross-section direction of the source-drain structure (i.e., the A-A' direction); (c) is a cross-sectional view of the self-aligned transistor taken along the cross-section direction of the gate structure (i.e., the B-B' direction).

[0160] See Figure 10 As shown, the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12. The active structure in the self-aligned transistor 10 is a plurality of nanosheet layer structures. The nanosheet layer structure is divided into upper and lower parts, which are respectively denoted as the first part and the second part. The first part serves as the first active structure 111 in the first transistor 11, and the second part serves as the second active structure 121 in the second transistor 12. The first source-drain metal 113 in the first transistor 11 and the second source-drain metal 123 in the second transistor 12 are interconnected through an interconnect via structure 13. The interconnect via structure 13 is located on one side of the active structure, and the two ends of the interconnect via structure 13 are respectively connected to the first source-drain metal 113 and the second source-drain metal 123. A shallow trench isolation layer 14 is provided between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used to isolate the first transistor 11 and the second transistor 12.

[0161] In some embodiments, during the preparation Figure 10 of the self-aligned transistor 10 shown, when etching the semiconductor substrate to form the nanosheet layer structure, the position of the etching is controlled such that the position of the formed nanosheet layer structure is biased towards one side of the semiconductor substrate, and a relatively large space is reserved on the other side of the semiconductor substrate for subsequent preparation of the interconnect via structure 13. When forming the interconnect via structure 13, a trench hole with a larger diameter is etched, and then a metal material is deposited in the trench hole to form the interconnect via structure 13. Figure 10 The preparation methods of the other structures in the self-aligned transistor 10 shown Figure 2 are the same as those of the self-aligned transistor 10 shown. Reference can be made to the first preparation process of the self-aligned transistor 10, and this application embodiment will not elaborate on it.

[0162] In the embodiment of the present application, the interconnect via structure 13 in the self-aligned transistor 10 penetrates through the first interlayer dielectric layer 114 and the second interlayer dielectric layer 124 to realize the interconnection between the first source-drain structure 112 and the second source-drain structure 122;

[0163] Furthermore, since the interconnect via structure 13 penetrates through the first interlayer dielectric layer 114 and the second interlayer dielectric layer 124, by means of selective etching, the etching can be stopped at the source-drain metal, thereby reducing the control difficulty of the etching time in the source-drain interconnection scheme;

[0164] Further, the interconnected via structure 13 can be disposed at any one of the following positions: one side of the active structure, both sides of the active structure, and in the middle of the active structure, which makes the interconnection of the first source / drain structure 112 and the second source / drain structure 122 in the self-aligned transistor 10 more flexible.

[0165] Further, the self-aligned transistor 10 provided by the embodiments of the present application can be detected using a detection and analysis instrument, such as: scanning electron microscope (SEM), transmission electron microscope (TEM), scanning transmission electron microscopy (STEM), etc. Taking TEM as an example, the self-aligned transistor 10 provided by the embodiments of the present application can adopt the TEM sectioning method to detect the interconnection between the first source / drain metal 113 and the second source / drain metal 123.

[0166] The embodiments of the present application provide a semiconductor device, including: the self-aligned transistor as described in the above embodiments. The specific limitations of the self-aligned transistor can be referred to the above Figure 2 、 Figure 5 、 Figure 7 、 Figure 8 、 Figure 9 and Figure 10 shown self-aligned transistors, which will not be elaborated here.

[0167] The embodiments of the present application provide an electronic device, including: a circuit board and the semiconductor device as described in the above embodiments, and the semiconductor device is disposed on the circuit board. The semiconductor device includes the above self-aligned transistor. The specific limitations of the self-aligned transistor can be referred to the above Figure 2 、 Figure 5 、 Figure 7 、 Figure 8 、 Figure 9 and Figure 10 shown self-aligned transistors, which will not be elaborated here.

[0168] In the description of the present application, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine the different embodiments or examples described in the present application and the features of the different embodiments or examples.

[0169] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A method for source-drain interconnection of a self-aligned transistor, characterized in that, The method includes: Forming an active structure on a semiconductor substrate, the active structure including a first active structure and a second active structure; Based on the first active structure, sequentially forming a first source / drain structure, a first interlayer dielectric layer, and a first source / drain metal, the first interlayer dielectric layer wrapping the first active structure, the first source / drain structure, and the first source / drain metal; Flipping the wafer and removing the semiconductor substrate; Based on the second active structure, sequentially forming a second source / drain structure, a second interlayer dielectric layer, and a second source / drain metal, the second interlayer dielectric layer wrapping the second active structure, the second source / drain structure, and the second source / drain metal; Wherein, the first source / drain metal and the second source / drain metal are connected through an interconnection via structure, and the interconnection via structure penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer; The forming the first source / drain structure, the first interlayer dielectric layer, and the first source / drain metal based on the first active structure includes: etching a part of the first active structure to form the first source / drain structure; depositing a semiconductor material on the first active structure and the first source / drain structure to form the first interlayer dielectric layer; etching a first part of the first interlayer dielectric layer to form the first source / drain metal; etching a second part of the first interlayer dielectric layer to form a first interconnection via structure, and the first interconnection via structure is connected to the first source / drain metal; The etching the second part of the first interlayer dielectric layer to form the first interconnection via structure includes: etching the second part of the first interlayer dielectric layer to form a groove-shaped hole, wherein the etching depth is lower than the epitaxy of the first source / drain structure; depositing a metal material in the groove-shaped hole to form the first interconnection via structure; The interconnection via structure is located on one side of the active structure; or, the interconnection via structure is located on both sides of the active structure; or, the interconnection via structure is located in the middle of the active structure.

2. The method according to claim 1, wherein The forming the second source / drain structure, the second interlayer dielectric layer, and the second source / drain metal based on the second active structure includes: Etching a part of the second active structure to form the second source / drain structure; Depositing a semiconductor material on the second active structure and the second source / drain structure to form the second interlayer dielectric layer; Etching a first part of the second interlayer dielectric layer to form the second source / drain metal; Etching a second part of the second interlayer dielectric layer until it is connected to the first interconnection via structure to form a second interconnection via structure, and the second interconnection via structure and the first interconnection via structure form the interconnection via structure.

3. The method according to claim 1, wherein Before the flipping the wafer and removing the semiconductor substrate, the method further includes: Forming a first transistor based on the first interlayer dielectric layer; Bonding the first transistor to a carrier wafer.

4. The method according to claim 3, wherein After forming the second source / drain structure, the second interlayer dielectric layer, and the second source / drain contact structure based on the second active structure, the method further includes: Based on the second interlayer dielectric layer, a second transistor is formed, and the second transistor is self-aligned with the first transistor in the vertical direction of the semiconductor substrate.

5. A self-aligned transistor, characterized in that, Prepared by the method according to any one of claims 1 to 4, the self-aligned transistor includes: A first transistor; A second transistor, which is disposed opposite to the first transistor; Wherein, a first source / drain metal of the first transistor is connected to a second source / drain metal of the second transistor through an interconnection via structure, and the interconnection via structure penetrates through a first interlayer dielectric layer of the first transistor and a second interlayer dielectric layer of the second transistor; The interconnection via structure is located on one side of the active structure of the self-aligned transistor; or, the interconnection via structure is located on both sides of the active structure; or, the interconnection via structure is located in the middle of the active structure; The interconnection via structure is composed of a first interconnection via structure and a second interconnection via structure. The first interconnection via structure is connected to the first source / drain metal, the second interconnection via structure is connected to the second source / drain metal, and the first interconnection via structure is aligned with the second interconnection via structure.

6. A semiconductor device, characterized in that, Comprising: The self-aligned transistor according to claim 5.

7. An electronic device, characterized in that, Comprising: A circuit board and the semiconductor device according to claim 6, wherein the semiconductor device is disposed on the circuit board.

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