Semiconductor delay testing method, device, electronic device and storage medium

Abstract

The present invention discloses a semiconductor delay test method, a semiconductor delay test method, a test loop is provided with a network analyzer, a coaxial connector, a cable and an aging test board, and also includes a test probe group, the aging test board is provided with a plurality of signal holes, the cable sequentially connects the network analyzer, the coaxial connector, and the test probe group, and the probes in the test probe group are sequentially inserted into the signal holes according to the test requirements. Through the above method, the present invention directly connects the probes of the test probe group directly or indirectly to the signal holes of the measurement backplane, is not limited by the number of coaxial connectors, and can effectively improve the number of test channels and test efficiency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor aging testing, and in particular to a semiconductor delay testing method, device, electronic equipment and storage medium. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, high-speed and high-capacity memories are emerging in an endless stream, and the demand for semiconductor memory aging test equipment is also increasing.

[0003] In the traditional delay test system, we need to design a test board specifically for testing, lead out the required signal at both ends with coaxial heads, and then connect the coaxial heads to the corresponding network points for testing. This test method requires a separate test board to be designed, and the number of test channels is limited by the number of coaxial heads. Most existing solutions use network analyzers (TDR sampling heads) connected to coaxial terminals on PCB boards through cables, SMA connectors, and PCB boards; because coaxial terminals need to occupy a large area of ​​limited space on PCB boards, in actual operation, the test channels are limited by the area of ​​PCB boards. Generally, a separate test board needs to be designed to test the delay of each channel on the BIB. This solution proposes a signal delay test method for high-speed test equipment. Summary of the invention

[0004] The purpose of the present invention is to provide a semiconductor delay test method, device, electronic device and storage medium, which directly connect the test probe group to the signal hole of the measurement backplane, are not limited by the number of coaxial connectors, and can effectively improve the number of test channels and test efficiency.

[0005] In order to solve the above technical problems, a technical solution adopted by the present invention is:

[0006] In the first aspect, the present embodiment provides a semiconductor delay test method, wherein a network analyzer, a coaxial connector, a cable, and an aging test board are provided on the test loop, and a test probe group is also provided on the aging test board. The cable sequentially connects the network analyzer, the coaxial connector, and the test probe group, and the probes in the test probe group are sequentially inserted into the signal holes according to the test requirements. The test loop of the needle of the present application uses a test probe group to test the signal hole, and the test results are transmitted to the same network analyzer. Since the coaxial connector and the aging test board are avoided to test the delay, the present application is not limited by the number of coaxial connectors, and can effectively improve the number of test channels and test efficiency.

[0007] The aging test board is provided with a second backplane, and the signal hole is arranged in the second backplane.

[0008] The test loop is also provided with a first backplane, the test probe group is connected to the first backplane, and the first backplane is butted with the second backplane to ensure that the probe is directly or indirectly connected to the signal hole.

[0009] S1, the tester measures the delay of the first backplane signal hole, and the test time is T1;

[0010] S2, after the connector of the first backplane is connected to the second backplane of the test board, the tester measures the delay of the signal hole of the first backplane again, and the test time is T2;

[0011] S3. The delay time of the test board is T=T2-T1.

[0012] The present invention also provides a semiconductor delay testing method, comprising the following steps:

[0013] S1, the test probe group measures the delay of the first backplane signal hole, and the test time is T1;

[0014] S2, after the connector of the first backplane is connected to the second backplane of the aging test board, the test probe group measures the delay of the signal hole of the first backplane again, and the test time is T2;

[0015] S3. The delay time of the aging test board is T=T2-T1.

[0016] The test probe group in S1 is connected to the network analyzer through a cable, a coaxial connector, and a cable in sequence.

[0017] A plurality of devices under test are placed on the aging test board of S2, and pins of the plurality of devices under test are connected to the second backplane of the aging test board.

[0018] In S2, the second backplane of the aging test board and the plurality of devices under test form a topological structure.

[0019] The connector of the first backplane in S2 is connected to the second backplane of the aging test board by using a male and female terminal plug connection method.

[0020] The present invention also provides a semiconductor delay test device, including a network analyzer, a test probe group, a first backplane and an aging test board.

[0021] The first backplane is connected to the second backplane access device of the aging test board to form a topology structure for transmitting the signal of the device under test on the aging test board;

[0022] The network analyzer is connected to the test probe group via a cable, the coaxial connector, and the cable in sequence, and is used to measure and calculate the delay of the first backplane and the aging test board respectively.

[0023] The present invention also provides a delay test system, comprising at least one processor; and

[0024] a memory communicatively connected to at least one of the processors; wherein,

[0025] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform any of the above-mentioned testing methods.

[0026] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement any of the above-mentioned test methods when executed.

[0027] A semiconductor delay test method, device, electronic device and storage medium of the present invention directly connect the probes of a test probe group directly or indirectly to signal holes on a PCB, are not limited by the number of coaxial connectors, and can effectively improve the number of test channels and test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 It is a flow chart of a semiconductor delay testing method of the present invention;

[0030] Figure 2 It is a topological structure of an aging test board of a semiconductor delay test device of the present invention;

[0031] Figure 3 A schematic structural diagram of a semiconductor delay testing device of the present invention.

[0032] 1. Tester; 2. Tester; 3. First backplane; 4. Aging test board; 5. Second backplane; 6. Cable; 7. Coaxial connector. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical scheme and advantages of the present invention clearer, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the present invention shown in the accompanying drawings and described according to the accompanying drawings are merely exemplary, and the present invention is not limited to these embodiments.

[0034] It should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.

[0035] Also, in the description of the present invention, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0036] See also Figure 1 , Figure 2 , the embodiment of the present invention includes:

[0037] A semiconductor delay test method, a semiconductor delay test method, a test loop is provided with a network analyzer, a coaxial connector, a cable, an aging test board, and also includes a test probe group, the aging test board is provided with a plurality of signal holes, the cable sequentially connects the network analyzer, the coaxial connector, and the test probe group, and the probes in the probe group are sequentially inserted into the signal holes according to the test requirements. The test loop of the needle of the present application uses a test probe group to test the signal hole, and the test result is transmitted to the same network analyzer. Since the coaxial connector and the aging test board are avoided to connect to test the delay, the present application is not limited by the number of coaxial connectors, and can effectively improve the number of test channels and test efficiency.

[0038] The aging test board is provided with a second backplane, and the signal hole is arranged in the second backplane.

[0039] A first backplane is also provided on the test loop, and the probes of the test probe group are connected to the first backplane. The first backplane and the second backplane are butted against each other to ensure that the probes of the test probe group are directly or indirectly connected to the signal holes.

[0040] The specific test method is as follows:

[0041] S1, the probe of the test probe group measures the delay of the first backplane signal hole, and the test time is T1;

[0042] S2, after the connector of the first backplane is connected to the second backplane of the aging test board, the test probe group measures the delay of the signal hole of the first backplane again, and the test time is T2;

[0043] S3. The delay time of the aging test board is T=T2-T1.

[0044] The probes of the test probe group measure the first backplane signal hole, obtain the delay time T1 and send it to the network analyzer, the memory of the network analyzer stores the T1 time, the probes of the test probe group measure the connector of the first backplane and the same signal hole after the second backplane of the aging test board is connected, obtain the delay time T2 and send it to the network analyzer, the memory of the network analyzer stores the T2 time, the processor of the network analyzer processes the secondary delay time of a single signal hole, the test probe group continuously tests multiple signal holes, continuously sends multiple data packets to the network analyzer, and finally obtains the delay time of the aging test board.

[0045] All delay times in this application are processed by only one network analyzer to ensure the accuracy of the test.

[0046] The present application proposes an efficient delay testing method for an aging test board. Since the connection between a coaxial connector and a PCB board is avoided, the connector of the first backplane is connected to the second backplane access device of the aging test board, and the test probe group is connected to the signal hole on the aging test board. It is not limited by the number of coaxial connectors, and the number of test channels and test efficiency can be effectively improved.

[0047] The test probe group in S1 is connected to the network analyzer through a cable, a coaxial connector, and a cable in sequence. The test probe group is connected to the network analyzer through a cable and a coaxial connector. The test probe group is directly used to measure the test time before and after the first backplane is connected to the second backplane, and is not limited by the number of coaxial connectors.

[0048] A plurality of devices under test are placed on the aging test board of S2, and the pins of the plurality of devices under test are connected to the second backplane of the aging test board. The second backplane of the aging test board in S2 and the plurality of devices under test form a topological structure. The connector of the first backplane of S2 and the second backplane of the aging test board are connected by male and female terminal plugs.

[0049] See also Figure 3A semiconductor delay test device includes a network analyzer 1, a test probe group 2, a first backplane 3 and an aging test board 4, wherein the first backplane 3 is connected to the second backplane 5 of the aging test board 4 to form a topological structure for transmitting the signal of the device under test on the aging test board 4; the network analyzer 1 is connected to the test probe group through a cable 6, a coaxial connector 7 and a cable 6 in sequence, for respectively measuring and calculating the delay of the first backplane and the aging test board. The network analyzer has high RF performance and fast speed, and has a wide frequency range and comprehensive functions. Time recording is performed only through the network analyzer to avoid test time differences generated by multiple network analyzers when multiple aging test boards are tested at the same time.

[0050] The test probe set can be handheld for manual testing or fully automatic testing by a manipulator. The test probe of this application is suitable for 9GHz bandwidth, 0.3-20mm adjustable probe array feet, and its spacing adjustment is convenient and quick.

[0051] The cable is a radio frequency coaxial cable. The insulation material of the radio frequency coaxial cable is composed of physically foamed polyethylene to isolate the copper wire conductor. Outside the inner insulating material is another layer of annular conductor, namely the outer conductor. The outer conductor (organization shielding layer) is formed, welded, and tied with copper tape; or an aluminum tube structure; or a braided structure, and then the entire cable is wrapped with a polyvinyl chloride sheath. The advantage of radio frequency coaxial cable is that it can support high-bandwidth communication on relatively long lines without repeaters. The frequency range of the cable in this application is: DC-6GHz, including connectors SMPM and SSMP, the standing wave ratio is: 1.20:1, and the appearance material is black PE.

[0052] The coaxial connector uses SMA connector, which is a widely used small threaded coaxial connector with wide bandwidth, excellent performance, high reliability and long life. SMA connector is suitable for connecting RF cables or microstrip lines in the RF circuit of microwave equipment and digital communication systems. SMA connector is suitable for microwave applications with a frequency range up to 26.5GHz. It is often used in GPS clock interfaces on single boards and test ports of base station RF modules on wireless devices.

[0053] A delay test system comprises at least one processor; and a memory in communication with the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the test method described in any one of the above claims.

[0054] The memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0055] The memory stores executable instructions, and the processor can read the executable instructions from the memory and execute the instructions to implement all or part of the steps of the latency testing method based on underlying communication described in any of the above exemplary embodiments.

[0056] A computer-readable storage medium storing computer instructions, wherein the computer-readable storage medium is used to implement any of the above-mentioned test methods when executed by a processor. The computer-readable storage medium may adopt any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or components, or any combination thereof.

[0057] A semiconductor delay test method, device, electronic device and storage medium of the present invention directly connect the probe to the signal hole on the PCB, are not limited by the number of coaxial connectors, and can effectively improve the number of test channels and test efficiency.

[0058] In addition, it should be noted that in this specification, "includes", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0059] It should be understood that although this specification is described according to implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A semiconductor delay test device, wherein a network analyzer, a coaxial connector, a cable and an aging test board are arranged on the test loop, characterized in that: It also includes a test probe group. The aging test board is provided with a plurality of signal holes. The cable sequentially connects the network analyzer, the coaxial connector and the test probe group. The aging test board is provided with a second backplane. The signal holes are provided in the second backplane. A first backplane is also provided on the test loop. The test probe group is connected to the first backplane. The first backplane and the second backplane are docked to ensure that the probes in the test probe group are directly or indirectly connected to the signal holes.

2. A semiconductor delay test method, characterized in that: The following steps are involved: S1, the test probe group measures the delay of the first backplane signal hole, the test time is T1, and the test probe group is connected to the network analyzer through the cable, the coaxial connector, and the cable in sequence; S2, multiple devices under test are placed on the aging test board, and the pins of the multiple devices under test are connected to the second backplane of the aging test board. After the connector of the first backplane is connected to the second backplane of the aging test board, the connector of the first backplane is connected to the second backplane of the aging test board using a male and female terminal plug connection method, and the second backplane of the aging test board and the multiple devices under test form a topological structure, and the test probe group measures the delay of the signal hole of the first backplane again, and the test time is T2; S3. The delay time of the aging test board is T=T2-T1.

3. A semiconductor delay testing method according to claim 2, characterized in that: The first backplane is connected to the second backplane access device of the aging test board to form a topological structure for transmitting the signal of the device under test on the aging test board; the network analyzer is connected to the test probe group through cables, coaxial connectors, and cables in sequence to measure and calculate the delay of the first backplane and the aging test board respectively.

4. A time delay test system, characterized in that: The invention comprises at least one processor; and a memory which is communicatively connected to at least one of the processors; wherein the memory stores a computer program which can be executed by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the test method according to any one of claims 2 to 3.

5. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the testing method according to any one of claims 2 to 3 when executed.

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