Array substrate and display panel

Abstract

The embodiment of the present application discloses an array substrate and a display panel, including a non-display area, in which a scan drive circuit, a plurality of clock lines extending along a first direction and arranged in sequence along a second direction, and a plurality of signal transmission lines extending along the second direction and arranged in sequence along the first direction are arranged in sequence, each clock line is connected to the scan drive circuit through a signal transmission line, the clock signal line is used to transmit a clock signal to the scan drive circuit, and the clock signal is used to drive the scan drive circuit to output a scan signal. The array substrate also includes a substrate, in the non-display area, the clock line and the signal transmission line are arranged on the same layer on the surface of the substrate, the clock line includes a notch at the position where the clock line and the signal transmission line intersect, the clock line and the signal transmission line are insulated from each other at the notch position, and the clock line is electrically connected to each other via a conductive layer at the notch position. By arranging the clock line and the signal transmission line on the same layer, the parasitic capacitance between the clock line and the signal transmission line can be effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] GOA technology (Gate On Array) means that the scan drive circuit is made on the array substrate, so that it can replace the external integrated circuit board (IC) to complete the drive of the horizontal scan line. GOA technology can reduce the bonding process of the external IC, improve production capacity and reduce product costs, and make the display panel more suitable for the production of narrow-border or borderless display products.

[0003] However, since the scan driving circuit needs to set up a large number of clock lines for transmitting clock signals, and the clock lines will be set across lines during the arrangement process, resulting in a large parasitic capacitance between the clock lines, which in turn causes a large clock signal delay, thereby affecting the driving capability of the scan driving circuit. Therefore, how to reduce the parasitic capacitance between the clock lines is an issue that needs to be urgently addressed. Summary of the invention

[0004] In view of the shortcomings of the above technical problems, the present application provides an array substrate and a display panel that can effectively reduce the parasitic capacitance between clock lines.

[0005] The present application discloses an array substrate, including a display area and a non-display area, wherein an array-arranged pixel unit is arranged in the display area, and a scanning drive circuit is arranged in the non-display area, wherein the scanning drive circuit is connected to the pixel unit and is used to output a scanning signal to control the pixel unit to receive a data signal for image display to display an image. In the non-display area, a plurality of clock lines extending along a first direction and arranged in sequence along a second direction and a plurality of signal transmission lines extending along a second direction and arranged in sequence along the first direction are also arranged, wherein each clock line is connected to the scanning drive circuit through a signal transmission line, wherein the clock signal line is used to transmit a clock signal to the scanning drive circuit, and the clock signal is used to drive the scanning drive circuit to output a scanning signal. The array substrate also includes a substrate, wherein in the non-display area, the clock line and the signal transmission line are arranged on the same layer on the substrate surface, wherein the clock line includes a notch at the position where the clock line and the signal transmission line intersect, wherein the clock line and the signal transmission line are insulated from each other at the notch position, and wherein the clock line is electrically connected to each other via a conductive layer at the notch position.

[0006] Optionally, the clock line includes multiple sub-clock line segments along the first direction, any two adjacent sub-clock line segments are spaced a preset distance apart to form a gap, and the two adjacent sub-clock line segments are connected at the gap through a conductive layer; the conductive layer is stacked at the gap through an insulating layer.

[0007] Optionally, the array substrate further includes a first insulating layer and a second insulating layer, the first insulating layer is arranged between the base and the clock line, the second insulating layer is arranged on the surface of the clock line, and the conductive layer is arranged on the base surface of the second insulating layer.

[0008] Optionally, the conductive layer includes a plurality of mutually insulated conductors, and the plurality of conductors are respectively arranged opposite to the plurality of notches. The second insulating layer is provided with two through holes corresponding to each conductor, and the two through holes are arranged opposite to each other at two ends of the conductor. At the notch position, the conductors are electrically connected to two adjacent sub-clock line segments through the through holes.

[0009] Optionally, along the first direction, the clock line includes a gaps and a+1 sub-clock line segments, the a+1 sub-clock line segments are arranged in sequence along the first direction, the 1st sub-clock line segment is connected to a preset conductor, the a+1th sub-clock line segment is a preset conductor, and the 1st sub-clock line segment and the a+1th sub-clock line segment are electrically connected through the preset conductor.

[0010] Optionally, each clock line is correspondingly provided with a first through hole and a second through hole, the first through hole is arranged opposite to the 1st sub-clock line segment, the second through hole is arranged opposite to the a+1th sub-clock line segment, the 1st sub-clock line segment is connected to the preset conductor through the first through hole, and the a+1th sub-clock line segment is connected to the preset conductor through the second through hole.

[0011] Optionally, a preset conductor is correspondingly arranged for each clock line, and the preset conductor extends from the position of the first notch to the position of the ath notch along the first direction.

[0012] Optionally, in the display area, the pixel unit includes a thin film transistor and a pixel electrode, the gate of the thin film transistor is located between the first insulating layer and the substrate, the source and drain of the thin film transistor are located in the same layer as the clock line, and the pixel electrode is located in the same layer as the conductive layer. The thin film transistor is used to transmit a data signal to the pixel electrode under the control of a scanning signal, and the pixel electrode drives the display medium to display an image according to the data signal.

[0013] Optionally, the scan driving circuit includes a plurality of scan driving units, each of which is connected to a corresponding signal transmission line and is used for receiving a clock signal from the signal transmission line and outputting a scan signal according to the clock signal.

[0014] The embodiment of the present application further discloses a display panel, including a counter substrate, a display medium layer and the aforementioned array substrate, wherein the array substrate cooperates with the counter substrate to drive the display medium in the display medium layer to display images.

[0015] Compared with the existing technical problems, the present application sets the clock line and the signal transmission line on the same layer and sets a gap in the clock line, so that the signal transmission line is connected to the scanning drive circuit through the gap. At the same time, the clock line is electrically connected at the gap through a conductive layer set on a different layer, so that the clock line and the signal transmission line do not affect each other during the signal transmission process. Moreover, since the clock line and the signal transmission line are set on the same layer, the parasitic capacitance between the clock line and the signal transmission line is effectively eliminated, thereby eliminating the influence of the parasitic capacitance on the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of the structure of a display device provided in one embodiment of the present application;

[0018] Figure 2 for Figure 1 The middle shows the schematic diagram of the side structure of the panel;

[0019] Figure 3 for Figure 2 A schematic diagram of the plane layout of an array substrate in the display panel shown;

[0020] Figure 4 for Figure 3 Schematic diagram of the plan layout of the Central Africa display area;

[0021] Figure 5 for Figure 2 A schematic diagram of the cross-sectional structure of the non-display area of ​​the array substrate;

[0022] Figure 6 is a schematic cross-sectional structure diagram of an array substrate in a second embodiment of the present application;

[0023] Figure 7 for Figure 6 A schematic diagram of the planar layout of the non-display area of ​​the middle array substrate;

[0024] Figure 8 for Figure 7 A magnified schematic diagram of the conductor connection area;

[0025] Fig. 9 for Figure 8 Schematic diagram of the structure along the AA section;

[0026] Fig.10 The third embodiment of the present application provides Figure 6Schematic diagram of clock line connection;

[0027] Fig.11 for Fig.10 A magnified schematic diagram of the conductor connection area.

[0028] Description of reference numerals:

[0029] Display device-100, display panel-10, power module-20, display area-10a, non-display area-10b, array substrate-10c, opposite substrate-10d, display medium layer-10e, m data lines-S1~Sm, n scanning lines-G1~Gn, first direction-F1, second direction-F2, timing control circuit-11, data driving circuit-12, scanning driving circuit-13, pixel unit-16, scanning driving unit-130, clock line-14, signal transmission line-15, through hole-H, substrate-101, first insulating layer- 102, first metal layer-M1, passivation layer-103, second metal layer-M2, second insulating layer-104, metal layer-M, conductive layer-IT, conductor-105, notch-K, thin film transistor-TFT, source-s, drain-d, gate-g, pixel electrode-161, first through hole-H1, second through hole-H2, first sub-clock line segment-141, second sub-clock line segment-142, first notch-K1, second notch-K2, first sub-clock line segment-14A, second sub-clock line segment-14B, third sub-clock line segment-14C. DETAILED DESCRIPTION

[0030] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0031] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be used to implement. The serial numbers for the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present application, unless otherwise specified, include direct and indirect connections (couplings). The directional terms mentioned in the present application, such as "upper", "lower", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0032] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be internal communication between two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the specification, claims, and drawings of the present application are used to distinguish different objects, rather than to describe a specific order.

[0033] In addition, the terms "include", "may include", "contain", or "may include" used in the present application indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit one or more other functions, operations, elements, etc. In addition, the terms "include" or "contain" indicate the existence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions. In addition, when describing the embodiments of the present application, "may" is used to indicate "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0035] See also Figure 1 , Figure 1 The first embodiment of the present application provides a structural schematic diagram of a display device 100. The display device 100 includes a display panel 10 and a power module 20. The power module 20 is disposed on the back side of the display panel 10, that is, the non-display side of the display panel 10. The power module 20 is used to provide driving power for the display panel 10 to display images.

[0036] See also Figure 2 , Figure 2 for Figure 1 FIG. 1 is a schematic diagram of the side structure of the display panel 10.

[0037] like Figure 2As shown, the display panel 10 includes an image display area 10a and a non-display area 10b. The display area 10a is used to perform image display, and the non-display area 10b is arranged around the display area 10a to set other auxiliary components or modules. Specifically, the display panel 10 includes an array substrate 10c and an opposing substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the opposing substrate 10d. The array substrate 10c and the opposing substrate 10d cooperate to drive the display medium in the display medium layer 10e to display images. In this embodiment, the display medium in the display medium layer 10e can be liquid crystal molecules, and of course it can also be other light-emitting materials such as OLED, Micro LED, Mini LED, LED, etc.

[0038] See also Figure 3 , Figure 3 for Figure 2 FIG. 1 is a schematic diagram of the planar layout of the array substrate 10c in the display panel 10. Figure 3 As shown, the array substrate 10c corresponding to the image display area 10a includes a plurality of m*n pixel units 16 arranged in a matrix, m data lines S1-Sm and n scanning lines G1-Gn, where m and n are natural numbers greater than 1.

[0039] The n scan lines G1-Gn extend along the second direction F2 and are insulated from each other and arranged in parallel along the first direction F1. The m data lines S1-Sm extend along the first direction F1 and are insulated from each other and arranged in parallel along the second direction F2. The first direction F1 is perpendicular to the second direction F2.

[0040] Corresponding to the non-display area 10b of the display panel 10 ( Figure 2 ), the display device 100 further includes a timing control circuit 11 for driving the pixel unit to display an image, a data driving circuit 12, and a scanning driving circuit 13 arranged on the array substrate 10c.

[0041] Among them, the timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13, and is used to control the working timing of the data driving circuit 12 and the scan driving circuit 13, that is, outputting corresponding timing control signals to the data driving circuit 12 to the scan driving circuit 13 to control when to output corresponding scan signals and data signals.

[0042] The data driving circuit 12 is electrically connected to the m data lines S1 ˜Sm, and is used to transmit data signals (Data) to be displayed to the plurality of pixel units 16 in the form of data voltages through the m data lines S1 ˜Sm.

[0043] The scan driving circuit 13 is used to be electrically connected to the n scan lines G1-Gn, and is used to output scan signals through the n scan lines G1-Gn for controlling when the pixel unit 16 receives the data signal. The scan driving circuit 13 outputs scan signals from the n scan lines G1-Gn in sequence according to the scan cycle.

[0044] In this embodiment, the circuit elements in the scan driving circuit 13 and the pixel units 16 in the array substrate 10 c are manufactured in the array substrate 10 c in the same process, which is also the GOA (Gate Driver on Array) technology.

[0045] See also Figure 4 , Figure 4 for Figure 3 Schematic diagram of the floor plan layout of the Central Africa display area.

[0046] like Figure 4 As shown, a plurality of clock lines 14 and a plurality of signal transmission lines 15 are arranged at a position adjacent to the scan driving circuit 13 in the non-display area 10b. The plurality of clock lines 14 extend along a first direction F1 and are arranged in sequence along a second direction F2. The plurality of signal transmission lines 15 extend along the second direction F2 and are arranged in sequence along the first direction F1. Each clock line 14 is electrically connected to a signal transmission line 15 and is connected to the scan driving circuit 13 via the signal transmission line 15 for transmitting a clock signal to the scan driving circuit 13. The scan driving circuit 13 outputs a scan signal to the pixel unit 16 according to the clock signal.

[0047] Among them, the clock line 14 and the signal transmission line 15 are arranged in different layers, that is, they are arranged in different layer structures. Along the thickness direction of the array substrate 10c, the clock line 14 and the signal transmission line 15 at least partially overlap, and a through hole H is arranged at the overlapping position. The clock line 14 is electrically connected to the signal transmission line 15 through the through hole H.

[0048] The scan driving circuit 13 includes a plurality of cascaded scan driving units 130 , each of which is connected to a clock line 14 via at least one signal transmission line 15 , and is used to receive a clock signal from the clock line 14 and output at least one scan signal according to the clock signal.

[0049] In an exemplary embodiment, the plurality of scan driving units 130 in the scan driving circuit 13 may be controlled to output scan signals by eight clock signals, or may be controlled by two clock signals, four clock signals, or six clock signals, which is not limited in the present application.

[0050] See also Figure 5 , Figure 5 for Figure 2Schematic diagram of the cross-sectional structure of the non-display area of ​​the array substrate.

[0051] like Figure 5 As shown, in the non-display area 10b, the array substrate 10c includes a substrate 101, a first insulating layer 102, a first metal layer M1, a passivation layer 103, a second metal layer M2 and a second insulating layer 104, wherein a plurality of clock lines 14 made of the first metal layer M1 are stacked on the substrate 101, and the first insulating layer 102 is stacked on the substrate 101 and covers the clock lines 14. A signal transmission line 15 made of the second metal layer M2 is stacked on the side of the first insulating layer 102 away from the substrate 101, and the signal transmission line 15 passes through the first insulating layer 102 through a hole H and is connected to the clock line 14. The passivation layer 103 is stacked on the first insulating layer 102 and covers the signal transmission line 15. The second insulating layer 104 is stacked on the side of the passivation layer 103 away from the first insulating layer 102.

[0052] Among them, since the signal transmission line 15 extends along the second direction F2 across multiple clock lines 14, parasitic capacitance is formed between the clock line 14 and the signal transmission line 15. Due to the existence of the parasitic capacitance, the clock line 14 and the signal transmission line 15 have a large delay when transmitting the clock signal, which in turn causes the driving capability of the scan driving unit 130 to be reduced.

[0053] Please also read Figure 6 and Figure 7 , Figure 6 This is a schematic diagram of the cross-sectional structure of an array substrate in the second embodiment of the present application. Figure 7 for Figure 6 Schematic diagram of the plane layout of the non-display area of ​​the array substrate. Figure 6 Shown and Figure 7 As shown, the array substrate 10c includes a base 101, a first insulating layer 102, a metal layer M, a passivation layer 103, a second insulating layer 104 and a conductive layer IT, wherein the first insulating layer 102 is stacked on the base 101 along the thickness direction of the array substrate 10c, and the metal layer M is stacked on the side of the first insulating layer 102 away from the base 101.

[0054] In the non-display area 10b, a plurality of clock lines 14 ( Figure 7 ) and a plurality of signal transmission lines 15( Figure 7 ) is arranged on the metal layer M and is made of the metal layer M, that is, multiple clock lines 14 and multiple signal transmission lines 15 are made in the same layer structure. The passivation layer 103 is stacked and arranged on the side of the metal layer M away from the first insulating layer 102, and covers the clock line 14 and the signal transmission line 15. The second insulating layer 104 is stacked and arranged on the side of the passivation layer 103 away from the metal layer M. The conductive layer IT is stacked and arranged on the side of the second insulating layer 104 away from the passivation layer 103.

[0055] In the display area 10a, the pixel unit 16 ( Figure 3 ) includes a thin film transistor TFT and a pixel electrode 161. The gate g of the thin film transistor TFT is arranged between the substrate 101 and the first insulating layer 102, and the source s and the drain d are arranged on the metal layer M and are made of the metal layer M, that is, the source s and the drain d are arranged on the same layer structure as the clock line 14 and the signal transmission line 15. The pixel electrode 161 is arranged on the side of the second insulating layer 104 away from the substrate 101, and is arranged on the same layer structure as the conductive layer IT. The gate g of the thin film transistor TFT is connected to the scanning line, the source s is connected to the data line, and the drain is connected to the pixel electrode 161, which is used to transmit the data signal in the data line to the pixel electrode 161 under the control of the scanning signal, and the pixel electrode 161 drives the display medium layer 10e ( Figure 2 ) to display the image on the display medium.

[0056] In an exemplary embodiment, the conductive layer IT and the pixel electrode 161 may be made of the same transparent electrode. Of course, they may also be made of different electrodes according to specific needs, and the present application does not impose any limitation on this.

[0057] The second insulating layer 104 is provided with a through hole H, and the clock line 14 in the metal layer M is connected to the conductive layer IT through the through hole H. The thickness of the second insulating layer 104 can be increased as needed to reduce the parasitic capacitance between the metal layer M and the conductive layer IT. According to the capacitance formula C=ε*δ*S / d, ε and δ are constants related to the dielectric, so the capacitance value C is inversely proportional to the thickness d, so the thickness of the first insulating layer 102 can be adjusted to reduce the parasitic capacitance. In the display area 10a, the conductive layer IT can be used to make the pixel electrode of the pixel unit 16.

[0058] See also Figure 8 and Fig. 9 , Figure 8 for Figure 7 A magnified schematic diagram of the conductor connection area. Fig. 9 for Figure 8 Schematic diagram of the structure along the AA section.

[0059] like Figure 8 and Fig. 9 As shown, at the intersection of the clock line 14 and the signal transmission line 15, each clock line 14 is provided with a gap K of a preset length along the first direction F1, and the signal transmission line 15 passes through a plurality of gaps K along the second direction F2 to be connected to the scan driving unit 130, that is, the signal transmission line 15 is insulated from the clock line 14 at the intersection.

[0060] It should be noted that each signal transmission line 15 is correspondingly connected to a clock line 14 at a preset position, for example, the first clock line is correspondingly connected to the first signal transmission line, the second clock line is correspondingly connected to the second transmission line, etc. The connection position of the signal transmission line 15 and the clock line 14 at the preset position is not an intersection position, that is, the connection position of the signal transmission line 15 and the clock line 14 at the preset position is not provided with a gap K, and the intersection positions of the signal transmission line 15 and the remaining clock lines 14 are all provided with a gap K, and the signal transmission line 15 passes through the gap K along the second direction F2 to connect to the scan drive unit 130.

[0061] A conductor 105 is provided at the position corresponding to each notch K in the conductive layer IT. The conductor 105 is arranged opposite to the notch K along the thickness direction of the array substrate 10c. The clock lines 14 disconnected at the notch K are respectively connected to the same conductor 105 through the through holes H to be electrically connected through the conductor 105.

[0062] For example, the clock line 14 includes a first sub-clock line segment 141 and a second sub-clock line segment 142, which are respectively located on both sides of the gap K along the first direction F1, that is, the clock line 14 is disconnected at the gap K to form the first sub-clock line segment 141 and the second sub-clock line segment 142.

[0063] The first sub-clock line segment 141 is connected to the conductor 105 through the first through hole H1 along the thickness direction of the array substrate 10c, and the second sub-clock line segment 142 is connected to the conductor 105 through the second through hole H2 along the thickness direction of the array substrate 10c, that is, the first sub-clock line segment 141 is electrically connected to the second sub-clock line segment 142 through the conductor 105.

[0064] The multiple sub-clock line segments in each clock line 14 are electrically connected through the conductor 105 at the position of the notch K along the first direction F1, and each signal transmission line 15 is connected to the scan driving unit 130 through the multiple notches K. Due to the arrangement of the notches K and the conductor 105, the multiple clock lines 14 and the multiple signal transmission lines 15 in the same metal layer M do not affect each other during the signal transmission process, and because the clock line 14 and the signal transmission line 15 are arranged in the same layer, the parasitic capacitance between the clock line 14 and the signal transmission line 15 is effectively eliminated, thereby eliminating the influence of the parasitic capacitance on the clock signal.

[0065] See also Fig.10 and Fig.11 , Fig.10 The third embodiment of the present application provides Figure 6 Schematic diagram of clock line connection. Fig.11 for Fig.10 A magnified schematic diagram of the conductor connection area.

[0066] like Fig.10 and Fig.11 As shown, at the intersection of the clock line 14 and the signal transmission line 15, each clock line 14 is provided with a gap K of a preset distance along the first direction F1, and the signal transmission line 15 passes through the gaps K of multiple clock lines 14 along the second direction F2 to be connected to the scan driving unit 130, that is, the signal transmission line 15 is not electrically connected to the clock line 14 at the intersection.

[0067] It should be noted that each signal transmission line 15 is correspondingly connected to a clock line 14 at a preset position, for example, the first clock line is correspondingly connected to the first signal transmission line, the second clock line is correspondingly connected to the second transmission line, etc. The connection position of the signal transmission line 15 and the clock line 14 at the preset position is not an intersection position, that is, the connection position of the signal transmission line 15 and the clock line 14 at the preset position is not provided with a gap K, and the intersection positions of the signal transmission line 15 and the remaining clock lines 14 are all provided with a gap K, and the signal transmission line 15 passes through the gap K along the second direction F2 to connect to the scan drive unit 130.

[0068] A conductor 105 is disposed at a position corresponding to each notch K in the conductive layer IT, and the conductor 105 is disposed facing the notch K along the thickness direction of the array substrate 10 c .

[0069] Along the first direction F1, the clock line includes a notches K, where a is greater than or equal to 1, and the clock line is divided into a+1 sub-clock line segments by a notches K, and the a+1 sub-clock line segments extend along the first direction F1 and are sequentially arranged along the first direction F1, wherein the 1st clock line is connected to the conductor 105 via a through hole H, and the a+1th clock line is connected to the conductor 105 via another through hole H, that is, the 1st clock line and the a+1th clock line are electrically connected to the same conductor 105 via different through holes, for transmitting clock signals across the notches K through the conductor 105. The conductor extends along the first direction F1 from the position of the 1st notch K to the position of the ath notch K.

[0070] For example, the clock line 14 includes two notches K, namely the first notch K1 and the second notch K2. The clock line 14 is divided into three sub-clock line segments by the first notch K1 and the second notch K2, namely the first sub-clock line segment 14A, the second sub-clock line segment 14B and the third sub-clock line segment 14C. The plurality of through holes H include a first through hole H1 and a second through hole H2. The first through hole H1 corresponds to the first notch K1 and is disposed adjacent to the first sub-clock line segment 14A. The second through hole H2 corresponds to the second notch K2 and is disposed adjacent to the third sub-clock line segment 14C. The first sub-clock line segment 14A is connected to the conductor 105 through the first through hole H1, the third sub-clock line segment 14C is connected to the conductor 105 through the second through hole H2, and the first sub-clock line segment 14A and the third sub-clock line segment 14C are electrically connected through the conductor 105. The conductive body 105 extends along the first direction F1 from the position of the first notch K1 to the position of the second notch K2 .

[0071] In this embodiment, the sub-clock line segment between the 1st gap and the ath gap can be cancelled as needed, that is, the 1st sub-clock line segment, the conductor 105 and the a+1th sub-clock line segment constitute the transmission path of the clock signal.

[0072] The multiple sub-clock line segments in each clock line 14 are electrically connected through the conductor 105 at the position of the notch K along the first direction F1, and each signal transmission line 15 is connected to the scan driving unit 130 through the multiple notches K. Due to the arrangement of the notches K and the conductor 105, the multiple clock lines 14 and the multiple signal transmission lines 15 in the same metal layer M do not affect each other during the signal transmission process, and because the clock line 14 and the signal transmission line 15 are arranged in the same layer, the parasitic capacitance between the clock line 14 and the signal transmission line 15 is effectively eliminated, thereby eliminating the influence of the parasitic capacitance on the clock signal.

[0073] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. An array substrate, comprising a display area and a non-display area, wherein the display area is provided with pixel units arranged in an array, and the non-display area is provided with a scanning driving circuit, wherein the scanning driving circuit is connected to the pixel units and is used to output a scanning signal to control the pixel units to receive a data signal for image display to display an image; It is characterized in that A plurality of clock lines extending along the first direction and arranged in sequence along the second direction and a plurality of signal transmission lines extending along the second direction and arranged in sequence along the first direction are also provided in the non-display area, each of the clock lines is connected to the scan drive circuit through one of the signal transmission lines, the clock line is used to transmit a clock signal to the scan drive circuit, and the clock signal is used to drive the scan drive circuit to output the scan signal; The array substrate also includes a substrate, and in the non-display area, the clock line and the signal transmission line are arranged in the same layer on the surface of the substrate, the clock line includes a notch at the position where the clock line and the signal transmission line intersect, the clock line and the signal transmission line are insulated from each other at the position of the notch, and the clock lines are electrically connected to each other via a conductive layer at the position of the notch, the clock line includes a plurality of sub-clock line segments along the first direction, any two adjacent sub-clock line segments are spaced a preset distance apart to form the notch, two adjacent sub-clock line segments are connected at the position of the notch through the conductive layer, and the conductive layer is stacked at the notch through an insulating layer.

2. The array substrate according to claim 1, characterized in that: The array substrate further comprises a first insulating layer and a second insulating layer, wherein the first insulating layer is arranged between the base and the clock line, the second insulating layer is arranged on the surface of the clock line, and the conductive layer is arranged on the base surface of the second insulating layer.

3. The array substrate according to claim 2, characterized in that: The conductive layer includes a plurality of mutually insulated conductive bodies, and the plurality of conductive bodies are respectively arranged opposite to the plurality of notches one by one; The second insulating layer is provided with two through holes corresponding to each of the conductors, and the two through holes are arranged opposite to the two ends of the conductor. At the position of the notch, the conductor is electrically connected to two adjacent sub-clock line segments through the through holes.

4. The array substrate according to claim 3, characterized in that: Along the first direction, the clock line includes a gaps and a+1 sub-clock line segments, the a+1 sub-clock line segments are arranged in sequence along the first direction, the 1st sub-clock line segment is connected to a preset conductor, the a+1th sub-clock line segment is the preset conductor, and the 1st sub-clock line segment is electrically connected to the a+1th sub-clock line segment through the preset conductor.

5. The array substrate according to claim 4, characterized in that: Each clock line is correspondingly provided with a first through hole and a second through hole, the first through hole is arranged opposite to the first sub-clock line segment, the second through hole is arranged opposite to the a+1th sub-clock line segment, the first sub-clock line segment is connected to the preset conductor through the first through hole, and the a+1th sub-clock line segment is connected to the preset conductor through the second through hole.

6. The array substrate according to claim 5, characterized in that: A preset conductor is correspondingly arranged for each of the clock lines, and the preset conductor extends along the first direction from the position of the first notch to the position of the ath notch.

7. The array substrate according to any one of claims 2 to 6, characterized in that: In the display area, the pixel unit includes a thin film transistor and a pixel electrode, the gate of the thin film transistor is located between the first insulating layer and the substrate, the source and drain of the thin film transistor are located in the same layer as the clock line, and the pixel electrode is located in the same layer as the conductive layer; The thin film transistor is used to transmit the data signal to the pixel electrode under the control of the scanning signal, and the pixel electrode drives the display medium to display an image according to the data signal.

8. The array substrate according to claim 7, characterized in that: The scan driving circuit includes a plurality of scan driving units, each of which is connected to a corresponding signal transmission line and is used for receiving the clock signal from the signal transmission line and outputting the scan signal according to the clock signal.

9. A display panel, characterized in that: It comprises a counter substrate, a display medium layer and the array substrate according to any one of claims 1 to 8, wherein the array substrate cooperates with the counter substrate to drive the display medium in the display medium layer to display images.

Images