IGBT semiconductor structure and manufacturing method thereof

Abstract

The invention relates to an IGBT semiconductor structure and a manufacturing method thereof; the structure comprises a semiconductor substrate, wherein a drift region and a main region are arranged in the semiconductor substrate, wherein a source region is embedded in the main region, and an enhancement region is arranged below the main region; an anode layer and a buffer layer on the back of the semiconductor substrate; a gate trench structure, comprising a gate trench, wherein the gate trench surrounds the main region, the source region and the enhancement region, wherein a dielectric layer is arranged in the gate trench, and the gate trench is electrically isolated from the semiconductor by the dielectric layer, and a source contact for device connection is arranged on the source region; a floating p-well, wherein the floating p-well forms a junction with the drift region; a source contact, and a dummy trench structure, wherein a dummy contact is arranged in the main region of the dummy trench structure; through the design of an IGBT semiconductor structure, the diffusion depths of the enhancement region and the floating p-well can be freely set, thereby increasing the selectivity of device design.

Description

Technical Field

[0001] The invention relates to the technical field of power semiconductors, and in particular to an IGBT semiconductor structure and a manufacturing method thereof. Background Art

[0002] Semiconductor power devices with a trench gate structure, in particular trench IGBTs (insulated gate bipolar transistors). These devices have a gate contact that is electrically isolated from the rest of the transistor structure by a suitable dielectric material (e.g. silicon dioxide) that is used to control the device and switch it from a blocking state to a conducting state and vice versa. Modern IGBT designs can include many different design elements to achieve the desired device. For example, cells without a MOS channel formed (inactive cells), areas with a floating p-well layer, or additional trenches that are not connected to the gate potential (dummy trenches).

[0003] Currently, if Figure 1a , Figure 1b and Figure 1c , different layouts for dummy trenches, gate trenches and p-wells have been disclosed, specifically, Figure 1a The semiconductor structure includes a dummy trench 901, a gate trench 906, a floating p-well 907, an inactive mesa 904, an active mesa 905, a source 902, and a contact 903; Figure 1b The semiconductor structure includes a dummy trench 911, a gate trench 916, a floating p-well 917, an inactive mesa 914, an active mesa 915, a source 912, and a contact 913; Figure 1c The semiconductor structure includes a virtual trench 921, a gate trench 926, a floating p-well 927, an inactive table 924, an active table 925, a source 922, and a contact 923; the purpose of the above structure design is to provide protection for the electric field at the bottom of the gate trench and improve the switching behavior. However, the existing technical problem is that the diffusion enhancement and floating p-well are diffused in the same step, and there is no way to independently control the diffusion depth of the enhancement region and the floating p-well, which limits the design options. In addition, if there is a virtual trench structure with a "hole path", the current technology does not allow the "carrier confinement" in the gate trench structure and the virtual trench structure to be independently adjusted, that is, the freedom of carriers to flow into the hole path and the active contact.

[0004] The present invention is in urgent need of providing an IGBT semiconductor structure and a manufacturing method thereof. Summary of the invention

[0005] The object of the present invention is to provide an IGBT semiconductor structure and a method for manufacturing the same, which solves the existing technical problem that the diffusion enhancement and floating p-well are diffused in the same step, and there is no way to independently control the diffusion depth of the enhancement area and the floating p-well, which limits the selectivity of device design through the design of an IGBT semiconductor structure.

[0006] The present invention provides an IGBT semiconductor structure, comprising:

[0007] A semiconductor substrate, wherein a drift region of a first conductivity type is provided on the semiconductor substrate;

[0008] A main region of the second conductivity type is provided in the drift region;

[0009] The main body region (102) is embedded with a source region of a first conductivity type;

[0010] An enhancement region of the first conductivity type located below the main region (2);

[0011] an anode layer of a second conductivity type disposed on the back side of the semiconductor substrate;

[0012] A buffer layer of a first conductivity type is provided on the anode layer;

[0013] A gate trench structure, comprising a gate trench, the gate trench surrounds the main region, the source region and the enhancement region, a dielectric layer is provided in the gate trench, the gate trench is electrically isolated from the semiconductor by the dielectric layer, and a source contact for device connection is provided on the source region;

[0014] The highly doped region of the second conductivity type is electrically floating, i.e., a floating p-well, which exists on either side of the gate trench structure, and forms a junction with the drift region; the maximum depth of the junction extension is L1, which is greater than the depth of the gate trench, and the maximum depth position of the junction extension is far away from the gate trench; near the trench, the junction appears at a depth of L2, which is flush with the bottom of the gate trench; the connection line between L1 and L2 follows a smooth s-curve;

[0015] a source contact disposed within the source region, the source contact connecting the semiconductor substrate to an emitter potential on a top side of the device;

[0016] A dummy trench structure includes a dummy trench, the dummy trench surrounds the main region and the enhancement region, a dielectric layer is provided in the dummy trench, the dummy trench is electrically isolated from the semiconductor by the dielectric layer in the dummy trench, and is connected to the emitter contact of the device;

[0017] A dummy contact is disposed in the body region of the dummy trench structure, the dummy contact connecting the semiconductor material to an emitter potential on the top side of the device;

[0018] The above structures are arranged into stripes in the longitudinal direction, wherein the dummy trench structures and the gate trench structures can be arranged in any combination in the horizontal direction, and a floating p-well exists between any two of the dummy trench structures and the gate trench structures.

[0019] Preferably, the source region in the gate trench structure is interrupted at any ratio in the longitudinal direction.

[0020] Preferably, the depth of the enhancement region in the gate trench structure is different from the depth of the enhancement region in the dummy trench structure;

[0021] Alternatively, no enhancement region is provided in the gate trench structure or the dummy trench structure;

[0022] Alternatively, the depth of the enhancement region in the gate trench structure and the depth of the enhancement region in the dummy trench structure in the longitudinal direction can be adjusted.

[0023] Preferably, the main body region in the gate trench structure and the main body region in the dummy trench structure have different depths.

[0024] Preferably, the source contact in the dummy trench structure is interrupted at any ratio in the vertical direction.

[0025] Preferably, the width of the dummy trench is greater than the width of the gate trench; or the depth of the dummy trench is greater than the depth of the gate trench.

[0026] Preferably, a local oxidation of silicon (LOCOS) process is used to process the dummy trench structure region of the semiconductor substrate to form a recess, so that the dummy trench structure is deeper than the gate trench structure in the semiconductor device.

[0027] Preferably, a local oxidation of silicon (LOCOS) process is used to process the gate trench structure region of the semiconductor substrate to form a recess, so that the gate trench structure region is deeper than the dummy trench structure region in the semiconductor device.

[0028] Preferably, the dummy trench is not connected to the emitter and remains floating.

[0029] Preferably, the dummy trench is not connected to the emitter but is connected to the gate, and has a feature that the gate trench structure does not have a source region.

[0030] Preferably, the dummy trench structure forms a Schottky contact between the emitter electrode and the semiconductor material, and the main body region in the dummy trench structure does not embed an electrode.

[0031] The present invention also provides an IGBT semiconductor structure, comprising:

[0032] A semiconductor substrate, wherein a drift region of a first conductivity type is provided on the semiconductor substrate;

[0033] A main region of the second conductivity type is provided in the drift region;

[0034] A source region is embedded in the main body region;

[0035] An enhancement region of a first conductivity type is provided below the main region;

[0036] An anode layer of a second conductivity type is provided on the back side of the semiconductor substrate;

[0037] Disposing a buffer layer on the anode layer;

[0038] A gate trench structure, comprising a gate trench, the gate trench surrounds the main region, the source region and the enhancement region, a dielectric layer is provided in the gate trench, the gate trench is electrically isolated from the semiconductor by the dielectric layer, and a source contact for device connection is provided on the source region;

[0039] The highly doped region of the second conductivity type is electrically floating, i.e., a floating p-well, which exists on either side of the gate trench structure, and forms a junction with the drift region; the maximum depth of the junction is L1, which is greater than the depth of the trench, and the maximum depth of the junction is far away from the trench; near the trench, the junction appears at a depth of L2, which is flush with the bottom of the gate trench; the connection line between L1 and L2 follows a smooth s-curve;

[0040] a source contact disposed within the source region, the source contact connecting the semiconductor material to an emitter potential on a top side of the device;

[0041] a dummy trench structure consisting of a single wide and deep dummy trench covered by a thin dielectric film and filled with a conductive material connected to the emitter contact of the device;

[0042] a contact region at the bottom of the dummy trench structure, wherein the thin dielectric film is locally removed and the contact region is formed in the semiconductor device;

[0043] A CT implant region of a second conductivity type directly below the contact region at the bottom of the dummy trench;

[0044] The above structure is arranged into stripes in the longitudinal direction, wherein the dummy trenches and gate trench structures can be arranged in any combination in the horizontal direction, and a p-well region exists between any two of the dummy trenches and gate trench structures.

[0045] Preferably, the source region in the gate trench structure is interrupted at any ratio in the longitudinal direction.

[0046] Preferably, the contact area at the bottom of the dummy groove is interrupted at any ratio in the longitudinal direction.

[0047] Preferably, a local oxidation of silicon (LOCOS) process is used to form a depression in the dummy trench region on the surface of the semiconductor substrate, so that the dummy trench is deeper than the gate trench structure in the semiconductor device;

[0048] Alternatively, no dummy trench is provided, and the contact region is formed in the recessed region.

[0049] Preferably, a local oxidation of silicon (LOCOS) process is used to form a recess in the gate trench structure region of the semiconductor substrate, so that the gate trench structure region is deeper than the dummy trench in the semiconductor device.

[0050] Preferably, the contact region at the bottom of the dummy trench forms a Schottky contact between the metal and the semiconductor.

[0051] The present invention also provides an IGBT semiconductor structure, comprising

[0052] A semiconductor substrate, wherein a drift region of a first conductivity type is provided on the semiconductor substrate;

[0053] A main region of the second conductivity type is provided in the drift region;

[0054] A source region of the first conductivity type is embedded in the body region;

[0055] An enhancement region of the first conductivity type is provided below the main region;

[0056] An anode layer of a second conductivity type is provided on the back side of the semiconductor substrate;

[0057] A buffer layer is provided on the anode layer;

[0058] an auxiliary gate trench extending in a stripe pattern on the top surface of the device in the vertical (y) direction and electrically isolated from the semiconductor by a dielectric layer and connected to a gate contact of the device;

[0059] A gate trench structure, comprising a gate trench, the gate trench surrounds the main region, the source region and the enhancement region, a dielectric layer is provided in the gate trench, the gate trench is electrically isolated from the semiconductor layer by the dielectric layer, extends perpendicularly to the auxiliary gate trench in a longitudinal direction (y), and is connected to the auxiliary gate trench;

[0060] a plurality of gate trench structures arranged between two adjacent auxiliary trenches;

[0061] The highly doped region of the second conductivity type is electrically floating, i.e., a floating p-well, which exists on either side of the gate trench structure, and forms a junction with the drift region; the maximum depth of the junction is L1, which is greater than the depth of the trench, and the maximum depth of the junction is far away from the trench; near the trench, the junction appears at a depth of L2, which is flush with the bottom of the gate trench; the connection line between L1 and L2 follows a smooth s-curve;

[0062] a source contact within the gate trench structure that connects the semiconductor material to the emitter potential on the front side of the device;

[0063] A dummy trench structure, comprising a dummy trench, a dielectric layer is disposed in the dummy trench, the dummy trench surrounds the main region and the enhancement region, the dielectric layer of the dummy trench is connected to the emitter contact of the device, and extends in the vertical (X) direction of the device;

[0064] a contact region within the dummy trench structure that connects the semiconductor material to an emitter potential on the top side of the device;

[0065] A plurality of dummy trench structures and gate trench structures are arranged in a vertical (X) direction, wherein the dummy trench structures and gate trench structures may be alternated in any combination, and wherein a floating p-well exists between adjacent dummy trench structures and gate trench structures.

[0066] Preferably, the source region may be omitted in some gate trench structures, or in cases where the source region is discontinuous within a single gate trench structure, or any combination thereof.

[0067] Preferably, there is no floating p-well between the gate trench structures when viewed in the vertical direction, but rather spaced gate trenches extend along the length of the auxiliary trenches.

[0068] Preferably, the contact region within the dummy trench structure is interrupted at any ratio in the vertical direction.

[0069] Preferably, the enhancement layer in the gate trench structure and the enhancement region of the dummy trench structure have different depths; or the enhancement layer is omitted in the gate trench structure or the dummy trench structure.

[0070] Preferably, a local oxidation of silicon (LOCOS) process is used so that a recess is formed in the surface of the semiconductor substrate in the region of the gate trench structure.

[0071] Preferably, a local oxidation of silicon (LOCOS) process is used to form a recess in the region of the dummy trench structure on the surface of the semiconductor substrate.

[0072] Preferably, the contact region in the dummy trench forms a Schottky contact between the emitter electrode and the semiconductor material.

[0073] The present invention also provides a method for manufacturing an IGBT semiconductor structure according to any one of the above, comprising the following steps:

[0074] Using a semiconductor substrate doped with a first conductivity type material;

[0075] Using a mask to cover the semiconductor substrate, implanting a second conductive type dopant into a P-well region on the front side of the semiconductor substrate to form a floating P-well;

[0076] After a first high temperature treatment, the floating P-well diffuses into the semiconductor substrate, and the first high temperature treatment lasts for t1min;

[0077] Using a mask process on the front side of the semiconductor substrate, the semiconductor substrate is polarly etched to obtain a gate trench and a dummy trench, wherein the gap between the gate trench and the edge of the floating p-well region is Δpa, and the gap between the edge of the dummy trench and the edge of the floating p-well region is Δpd;

[0078] Injecting a first conductive type material into the front surface of the semiconductor substrate to form a first conductive type enhancement layer;

[0079] After a second high temperature treatment, the second high temperature treatment lasts for t2min, driving the floating p-well region and the enhancement layer to continue to penetrate, so that the bottom of the floating p-well region forms an S shape;

[0080] Injecting a second conductive type material from the front side of the semiconductor substrate to form a body layer;

[0081] After a third high temperature treatment, the third high temperature treatment lasts for t3min, driving the floating p-well, the enhancement layer and the main region to continue to penetrate, and obtaining a final desired pattern;

[0082] Using a mask process, forming a source region and a source contact on the front side of the semiconductor substrate, and depositing a metal layer on the front side of the semiconductor substrate;

[0083] The back side of the semiconductor substrate is polished, and after polishing, an anode layer and a buffer layer are sequentially arranged on the back side of the semiconductor substrate;

[0084] An annealing process is used to treat the anode layer and the buffer layer to activate the anode layer and the buffer layer;

[0085] A metal layer is deposited on the buffer layer.

[0086] Preferably, Δpd and t1 are selected in such a way that after the dummy trench etching; the dopants implanted in the p-well remain between the dummy trenches and partially compensate the dopants.

[0087] Preferably, Δpa and t1 are chosen in such a way that after the gate trench etching; the p-well implanted dopants remain between the gate trenches and partially compensate the dopants.

[0088] Preferably, the position of the reinforcement layer in the longitudinal direction varies.

[0089] The IGBT semiconductor structure and the manufacturing method thereof provided by the present invention have the following improvements compared with the prior art:

[0090] 1. In the IGBT semiconductor structure provided by the present invention, the distance between the gate trench and the dummy trench can be used to adjust the resistance of the hole path, which can reduce the carrier confinement in the dummy trench structure, thereby adjusting the efficiency of carrier confinement, while maintaining the same in the gate trench structure, which is beneficial to improving the static and dynamic performance of the device.

[0091] 2. The IGBT semiconductor structure provided by the present invention forms an S-shape at the bottom of the floating p-well region, which helps to form a smooth electric field in static and dynamic blocking conditions, improves the protection of the bottom of the gate trench, and reduces local long peaks and unnecessary carrier generation (dynamic avalanche). The bottom of the gate trench is where the electric field is most likely to cause local breakdown, avalanche carrier generation, and hot carrier injection into the gate oxide.

[0092] 3. The dummy trench of the present invention is replaced by a single large dummy trench, which is connected to the semiconductor at the bottom, and the high doping area with the opposite conductivity type to the drift region is placed directly under the contact to avoid collector emitter short circuit, thereby improving the hole extraction efficiency. It reduces the field peak problem of the gate trench structure manager and avoids moving the dummy trench that is often moved to the less sensitive emitter dummy bias.

[0093] 4. The design of the auxiliary gate trench in this embodiment can achieve a very small distance between two adjacent gate trench structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] Figure 1a : Schematic diagram of the structure of a conventional trench device with a stripe layout (top view);

[0095] Figure 1b : A schematic diagram of the structure of a conventional trench device with a dummy trench structure (top view);

[0096] Figure 1c : A schematic diagram of the structure of an existing conventional trench device with a dummy trench structure (a top view, wherein the dummy trench structure has an emitter contact);

[0097] Figure 2 A schematic diagram (cross-sectional view) of the IGBT semiconductor structure described in Example 1;

[0098] Figure 3a A schematic diagram of the IGBT semiconductor structure described in Example 1 (top view, with wider and deeper dummy trenches);

[0099] Figure 3b for Figure 3a A cross-sectional view of the drawn section line;

[0100] Figure 4a This is a schematic diagram of the IGBT semiconductor structure described in Example 1 (top view, with a recessed dummy trench structure);

[0101] Figure 4b for Figure 4a A cross-sectional view of the drawn section line;

[0102] Figure 5a This is a schematic diagram of the IGBT semiconductor structure described in Example 1 (top view, with a Schott contact in the dummy trench structure);

[0103] Figure 5b for Figure 5a A cross-sectional view of the drawn section line;

[0104] Figure 6 FIG1 is a diagram of the steps for preparing the IGBT semiconductor structure of Example 1 (I);

[0105] Figure 7 FIG2 is a step diagram of preparing the IGBT semiconductor structure of Example 1;

[0106] Figure 8 FIG3 is a step diagram of preparing the IGBT semiconductor structure of Example 1;

[0107] Fig. 9 FIG4 is a step diagram of preparing the IGBT semiconductor structure of Example 1;

[0108] Fig.10 FIG5 is a step diagram of preparing the IGBT semiconductor structure of Example 1;

[0109] Fig.11 FIG6 is a step diagram of preparing the IGBT semiconductor structure of Example 1;

[0110] Fig.12 FIG1 is a diagram of the steps for preparing the IGBT semiconductor structure of Example 2 (I);

[0111] Fig.13 FIG2 is a step diagram of preparing the IGBT semiconductor structure of Example 2;

[0112] Fig.14 FIG3 is a step diagram of preparing the IGBT semiconductor structure of Example 2;

[0113] Fig.15 FIG4 is a step diagram of preparing the IGBT semiconductor structure of Example 2;

[0114] Fig.16 FIG5 is a step diagram of preparing the IGBT semiconductor structure of Example 2;

[0115] Fig.17 FIG6 is a step diagram for preparing the IGBT semiconductor structure of Example 2;

[0116] Fig.18a Schematic diagram of the IGBT semiconductor structure of Embodiment 3 (top view, single dummy trench with contact area);

[0117] Fig.18b for Fig.18a A cross-sectional view of the drawn section line;

[0118] Fig.19a This is a schematic diagram of the IGBT semiconductor structure of Example 4 (top view, a single dummy trench with a contact area);

[0119] Fig.19b This is a schematic diagram of the IGBT semiconductor structure of Example 4 (top view, a single dummy trench with a contact area); DETAILED DESCRIPTION

[0120] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solution of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0121] Embodiment 1

[0122] like Figure 2As shown, the present invention provides an IGBT semiconductor structure, including a semiconductor substrate, a drift region 108 of a first conductivity type is provided on the semiconductor substrate; a main region 105 of a second conductivity type is provided in the drift region 108; a source region 103 of a first conductivity type is embedded in the main region 105; an enhancement region 106 of a first conductivity type is located below the main region 105; an anode layer of a second conductivity type is provided on the back side of the semiconductor substrate; a buffer layer of a first conductivity type is provided on the anode layer; a gate trench structure, including a gate trench The gate trench 102 surrounds the main region 105, the source region 103 and the enhancement region 106. A dielectric layer is provided in the gate trench 102, which is electrically isolated from the semiconductor. A source contact 104 for device connection is provided on the source region 103. A highly doped region of the second conductivity type is electrically floating, i.e., a floating p-well 107. The floating p-well 107 exists on either side of the gate trench structure 102. The floating p-well 107 forms a junction with the drift region 108. The maximum depth of the junction is L1. The junction extends The maximum depth of the junction line is greater than the depth of the gate trench 102, and the maximum depth position of the junction line is far away from the gate trench; near the gate trench, the junction line appears at a depth L2, and the depth L2 is flush with the bottom of the gate trench; the connection line between L1 and L2 follows a smooth s-curve; a source contact 104 is set in the source region 103, and the source contact 104 connects the semiconductor substrate to the emitter potential on the top side of the device; a dummy trench structure includes a dummy trench 101, and the dummy trench 101 surrounds the main region 105 and the enhancement region 106 A dielectric layer is provided in the dummy trench 101, which is electrically isolated from the semiconductor by the dielectric layer in the dummy trench and connected to the emitter contact of the device; a dummy contact is provided in the main region 105 in the dummy trench structure, and the dummy contact connects the semiconductor material to the emitter potential on the top side of the device; the above structure is arranged into stripes in the longitudinal (y) direction, wherein the dummy trench structure and the gate trench structure can be arranged in any combination in the horizontal direction (x), and a floating p-well 107 is present between any two of the dummy trench structures and the gate trench structures.

[0123] In the IGBT semiconductor structure provided by the present invention, the distance between the gate trench and the dummy trench can be used to adjust the resistance of the hole path, which can reduce the carrier confinement in the dummy trench structure, thereby adjusting the efficiency of the carrier confinement, while maintaining the same in the gate trench structure, which is beneficial to improving the static and dynamic performance of the device.

[0124] The IGBT semiconductor structure provided by the present invention forms an S-shape at the bottom of the floating p-well region, which helps to form a smooth electric field in static and dynamic blocking conditions, improves the protection of the bottom of the gate trench, and reduces local long peaks and unnecessary carrier generation (dynamic avalanche). The bottom of the gate trench is where the electric field is most likely to cause local breakdown, avalanche carrier generation and hot carrier injection into the gate oxide.

[0125] In the present invention, L2 is less than L1; specifically, the value of L1 is 5-8 μm, and L2 is 4.5-7.5 μm.

[0126] The source region 103 in the gate trench structure is interrupted at any ratio in the longitudinal direction (y-axis direction).

[0127] The depth of the enhancement region 106 in the gate trench structure is different from the depth of the enhancement region in the dummy trench structure; or, no enhancement region is provided in the gate trench structure or the dummy trench structure;

[0128] Alternatively, the depth of the enhancement region in the gate trench structure and the depth of the enhancement region in the dummy trench structure in the longitudinal direction (y-axis direction) can be adjusted.

[0129] The body region 105 in the gate trench structure has a different depth from that in the dummy trench structure.

[0130] The source contact 104 in the dummy trench structure is interrupted at any ratio in the vertical direction (y-axis direction).

[0131] like Figure 3a and Figure 3b The width of the dummy trench 101 is greater than the width of the gate trench 102 ; or the depth of the dummy trench 101 is greater than the depth of the gate trench 102 .

[0132] like Figure 4a and Figure 4b As shown, the dummy trench structure region of the semiconductor substrate is processed using a local oxidation of silicon (LOCOS) process to form a recess 108, so that the dummy trench structure is deeper than the gate trench structure region in the semiconductor device.

[0133] The dummy trench structure of the present invention is deeper in the semiconductor device than the gate trench structure area, which allows the dummy unit to enter the device deeper and be exposed to a higher electric field, which can better protect the gate trench and the robustness of the device (the robustness of a power semiconductor device means its ability to keep the system stable and operate normally under abnormal and dangerous conditions) because carriers can be generated in the event of a transient voltage peak.

[0134] The gate trench structure region of the semiconductor substrate is processed by using a local oxidation of silicon (LOCOS) process to form a recess, so that the gate trench structure region is deeper than the dummy trench structure region in the semiconductor device.

[0135] The dummy trench is not connected to the emitter and remains floating.

[0136] The dummy trench is not connected to the emitter but is connected to the gate, and has a feature that the gate trench structure does not have a source region.

[0137] like Figure 5a and Figure 5b As shown, the dummy trench structure forms a Schottky contact between the emitter electrode 109 and the semiconductor material, and the main region in the dummy trench structure does not embed an electrode.

[0138] like Figure 6-Figure 11 As shown, the present invention also provides a method for manufacturing an IGBT semiconductor structure, comprising the following steps:

[0139] S1) using a semiconductor substrate doped with a first conductivity type material;

[0140] S2) using a mask to cover the semiconductor substrate, and injecting a second conductive type dopant into the P-well region on the front side of the semiconductor substrate to form a floating P-well 107;

[0141] S3) performing a first high temperature treatment so that the floating P-well diffuses into the semiconductor substrate, and the first high temperature treatment lasts for t1 min; wherein the first high temperature is 800-1300° C. and lasts for t1 for 20-100 min;

[0142] S4) using a mask process on the front side of the semiconductor substrate to perform polarity etching on the semiconductor substrate to obtain a gate trench 102 and a dummy trench 101, wherein a gap between the gate trench 102 and an edge of the floating p-well region 107 is Δpa, and a gap between an edge of the dummy trench and an edge of the floating p-well region is Δpd; wherein a Δpa value is 100nm-3μm, and a Δpd value is 100-500nm;

[0143] S5) injecting a first conductive type material into the front surface of the semiconductor substrate to form a first conductive type enhancement layer 106;

[0144] S6) performing a second high temperature treatment, the second high temperature treatment lasting t2 min, driving the floating p-well region and the enhancement layer to continue to penetrate, so that the bottom of the floating p-well region forms an S shape; wherein the second high temperature is 800-1300° C., and t2 is 200-800 min;

[0145] S7) injecting a second conductive type material from the front side of the semiconductor substrate to form a body layer 105;

[0146] S8) performing a third high temperature treatment, the third high temperature treatment lasting t3 hours, driving the floating p-well, the enhancement layer and the main region to continue to penetrate, and obtaining the final desired pattern; wherein the third high temperature is 800-1300° C., t3 is 20-150 min, and further, t1+t2+t3=400-1000 min;

[0147] S9) using a mask process to form a source region 103 and a source contact 104 on the front side of the semiconductor substrate, and depositing a metal layer on the front side of the semiconductor substrate;

[0148] S10) grinding the back side of the semiconductor substrate, and after grinding, sequentially disposing an anode layer and a buffer layer on the back side of the semiconductor substrate;

[0149] S11) treating the anode layer and the buffer layer with an annealing process to activate the anode layer and the buffer layer;

[0150] S12) depositing a metal layer on the buffer layer to obtain an IGBT semiconductor structure.

[0151] Specifically, Δpd and t1 are selected in such a way that after the dummy trench etching; the dopants implanted in the p-well remain between the dummy trenches and partially compensate the dopants.

[0152] Specifically, Δpa and t1 are selected in such a way that after the gate trench etching; the p-well implanted dopants remain between the gate trenches and partially compensate the dopants.

[0153] Specifically, the position of the reinforcement layer in the longitudinal direction is varied.

[0154] Specifically, the semiconductor substrate is silicon, silicon carbide, gallium oxide or other semiconductor as a base material, and the dopant is phosphorus or arsenic for N-type and boron for P-type;

[0155] Specifically, the dopant is phosphorus or arsenic for N-type, or boron for P-type; for a standard n-channel IGBT, the first conductivity type is n-type, and the second conductivity type is P-type.

[0156] Figure 6-Figure 11 , a method for a device is disclosed, wherein the enhancement layer, the body layer and the p-well layer are diffused independently. In addition, the dummy trench and the gate trench act as diffusion barriers for the respective layers.

[0157] like Fig.11The characteristic "S-shape" of the floating p-well region is achieved by the above manufacturing method because the p-well driver is divided into parts before and after the dummy trench and gate trench etching. After the dummy trench and gate trench etching, the dopant is blocked by the dummy trench and gate trench walls and cannot diffuse further, resulting in a more "flat" doping gradient near the dummy trench and gate trench.

[0158] In the above figure Indicates the width, and the width is adjustable.

[0159] Embodiment 2

[0160] This embodiment is an improvement on the first embodiment, and the contents disclosed in the first embodiment will not be repeated in this embodiment.

[0161] like Figure 12-Figure 17 As shown, a method for preparing an IGBT semiconductor structure is disclosed, which allows independent adjustment of enhancement layers in a dummy trench structure and a gate trench structure without additional manufacturing steps, allowing independent modulation of majority and minority carrier accumulation in the device.

[0162] Embodiment 3

[0163] This embodiment is an improvement on the first embodiment, and the contents disclosed in the first embodiment will not be repeated in this embodiment.

[0164] like Fig.18a and Fig.18b This embodiment provides a semiconductor structure, comprising: a semiconductor substrate, a drift region of a first conductivity type is provided on the semiconductor substrate; a main body region 202 of a second conductivity type is provided in the drift region; a source region 203 is embedded in the main body region; an enhancement region 204 of a first conductivity type is provided below the main body region; an anode layer of a second conductivity type is provided on the back of the semiconductor substrate; and a buffer layer is provided on the anode layer;

[0165] A gate trench structure, including a gate trench 205, the gate trench 205 surrounds the main region 202, the source region 203 and the enhancement region 204, a dielectric layer is provided in the gate trench, and the gate trench is electrically isolated from the semiconductor by the dielectric layer, and a source contact 206 for device connection is provided on the source region 203;

[0166] The highly doped region of the second conductivity type is electrically floating, i.e., a floating p-well 207. The floating p-well exists on either side of the gate trench structure, and the floating p-well forms a junction with the drift region. The maximum depth of the junction is L1, which is greater than the depth of the trench, and the maximum depth of the junction is far away from the trench. Near the trench, the junction appears at a depth of L2, which is flush with the bottom of the gate trench. The connection line between L1 and L2 follows a smooth s-curve.

[0167] a source contact disposed within the source region, the source contact connecting the semiconductor material to an emitter potential on a top side of the device;

[0168] a dummy trench structure consisting of a single wide and deep dummy trench 208 covered by a thin dielectric film and filled with a conductive material connected to the emitter contact of the device;

[0169] a contact region 209 at the bottom of the dummy trench 208 structure, wherein the thin dielectric film is locally removed and a contact region is formed in the semiconductor device;

[0170] A CT implant region of a second conductivity type directly below the contact region at the bottom of the dummy trench;

[0171] The above structure is arranged into stripes in the longitudinal (y) direction, wherein the dummy trench and gate trench structures can be arranged in any combination in the horizontal (x) direction, and a p-well region exists between any two of the dummy trench and gate trench structures.

[0172] The dummy trench of the present invention is replaced by a single large dummy trench, which is connected to the semiconductor at the bottom, and the high doping area with the opposite conductivity type to the drift region is placed directly under the contact to avoid collector emitter short circuit, thereby improving the hole extraction efficiency. The field peak problem of the gate trench structure manager is reduced, and the dummy trench that is often moved to the less sensitive emitter dummy bias is avoided.

[0173] The source region in the gate trench structure is interrupted at any ratio in the vertical direction.

[0174] The contact area at the bottom of the dummy trench is interrupted at any ratio in the longitudinal (y) direction.

[0175] On a semiconductor substrate, a local oxidation of silicon (LOCOS) process is used to form a depression on the semiconductor substrate surface in the dummy trench structure area, so that the dummy trench structure is deeper than the gate trench structure, or the dummy trench structure may not be provided and a contact area is formed in the depression area.

[0176] Alternatively, on a semiconductor substrate, a local oxidation of silicon (LOCOS) process is used to form a depression on the surface of the semiconductor substrate in the gate trench structure area, so that the gate trench structure is deeper than the dummy trench structure, or a dummy trench structure may not be provided and a contact area is formed in the depression area.

[0177] The contact region at the bottom of the dummy trench forms a Schottky contact between the metal and the semiconductor, and no CT implant is disposed under the contact.

[0178] The preparation process of the second conductive type implantation area is as follows: after etching the dummy trench, etching the bottom of the trench through a masking process to form an opening at the bottom of the trench, injecting a second conductive type dopant at the opening, and activating the dopant through an annealing process or a rapid annealing process.

[0179] The Schottky contact can be defined to allow only one type of carrier to flow through the dummy trench structure, thereby improving the control of the plasma distribution in the device.

[0180] The CT implantation area of ​​this embodiment can help extract more holes.

[0181] Embodiment 4

[0182] This embodiment is an improvement on the first embodiment, and the contents disclosed in the first embodiment will not be repeated in this embodiment.

[0183] like Fig.19a , Fig.19b As shown, this embodiment provides an IGBT semiconductor structure, including a semiconductor substrate, a drift region 301 of a first conductivity type is provided on the semiconductor substrate; a body region 302 of a second conductivity type is provided in the drift region 301; a source region 303 of a first conductivity type is embedded in the body region 302; an enhancement region 304 of a first conductivity type is provided below the body region; an anode layer of a second conductivity type is provided on the back of the semiconductor substrate; and a buffer layer is provided on the anode layer;

[0184] auxiliary gate trenches 310 extending in a stripe pattern on the top surface of the device in the vertical (y) direction and electrically isolated from the semiconductor by a dielectric layer and connected to the gate contact of the device;

[0185] A gate trench structure, comprising a gate trench 305, the gate trench 305 surrounds the main region, the source region and the enhancement region, a dielectric layer is provided in the gate trench, the gate trench is electrically isolated from the semiconductor layer by the dielectric layer, extends perpendicularly to the auxiliary gate trench in the longitudinal direction (y), and is connected to the auxiliary gate trench;

[0186] a plurality of gate trench structures arranged between two adjacent auxiliary trenches;

[0187] The highly doped region of the second conductivity type is electrically floating, i.e., a floating p-well 306. The floating p-well exists on either side of the gate trench structure, and the floating p-well forms a junction with the drift region. The maximum depth of the junction is L1, which is greater than the depth of the trench, and the maximum depth of the junction is far away from the trench. Near the trench, the junction appears at a depth of L2, which is flush with the bottom of the gate trench. The connection line between L1 and L2 follows a smooth s-curve.

[0188] a source contact 307 within the gate trench structure, which connects the semiconductor material to the emitter potential on the front side of the device;

[0189] A dummy trench structure, comprising a dummy trench 308, a dielectric layer is disposed in the dummy trench, the dummy trench surrounds the main region and the enhancement region, the dielectric layer of the dummy trench is connected to the emitter contact of the device, and extends in the vertical (X) direction of the device;

[0190] a contact region 309 within the dummy trench structure that connects the semiconductor material to the emitter potential on the top side of the device;

[0191] A plurality of dummy trench structures and gate trench structures are arranged in a vertical (X) direction, wherein the dummy trench structures and gate trench structures may alternate in any combination, and wherein a floating p-well exists between adjacent dummy trench structures and gate trench structures.

[0192] In some embodiments, the source region may be omitted in some gate trench structures, or may be discontinuous within a single gate trench structure, or any combination thereof.

[0193] In some embodiments, there is no floating p-well between the gate trench structures when viewed in the vertical direction, but rather spaced gate trenches extend along the length of the auxiliary trenches.

[0194] In some embodiments, the contact regions within the dummy trench structure are interrupted at any ratio in the vertical direction.

[0195] In some embodiments, the enhancement region in the gate trench structure and the enhancement layer in the dummy trench structure have different depths; or the enhancement layer is omitted in the gate trench structure or the dummy trench structure.

[0196] In some embodiments, a local oxidation of silicon (LOCOS) process is used to form a recess in the surface gate trench structure of the semiconductor substrate.

[0197] In some embodiments, a local oxidation of silicon (LOCOS) process is used to form a recess in the surface of the semiconductor substrate in the region of the dummy trench structure.

[0198] In some embodiments, the contact region in the dummy trench forms a Schottky contact between the emitter electrode and the semiconductor material.

[0199] The design of the auxiliary gate trench 310 in this embodiment can achieve a very small distance between two adjacent gate trench structures.

[0200] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. An IGBT semiconductor structure, characterized in that: include A semiconductor substrate, wherein a drift region of a first conductivity type is provided on the semiconductor substrate; A main region of a second conductivity type is provided in the drift region; The body region is embedded with a source region of a first conductivity type; an enhancement region of the first conductivity type located below the main region; an anode layer of a second conductivity type disposed on the back side of the semiconductor substrate; A buffer layer of a first conductivity type is provided on the anode layer; A gate trench structure, comprising a gate trench, the gate trench surrounds the main region, the source region and the enhancement region, a dielectric layer is provided in the gate trench, the gate trench is electrically isolated from the semiconductor by the dielectric layer, and a source contact for device connection is provided on the source region; The highly doped region of the second conductivity type is electrically floating, i.e., a floating p-well, which exists on either side of the gate trench structure, and forms a junction with the drift region; the maximum depth of the junction extension is L1, which is greater than the depth of the gate trench, and the maximum depth position of the junction extension is far away from the gate trench; near the trench, the junction appears at a depth of L2, which is flush with the bottom of the gate trench; the connection line between L1 and L2 follows a smooth s-curve; a source contact disposed within the source region, the source contact connecting the semiconductor substrate to an emitter potential on a top side of the device; A dummy trench structure includes a dummy trench, the dummy trench surrounds the main region and the enhancement region, a dielectric layer is provided in the dummy trench, the dummy trench is electrically isolated from the semiconductor by the dielectric layer in the dummy trench, and is connected to the emitter contact of the device; A dummy contact is disposed in the body region of the dummy trench structure, the dummy contact connecting the semiconductor material to an emitter potential on the top side of the device; The above structures are arranged into stripes in the longitudinal direction, wherein the dummy trench structures and the gate trench structures can be arranged in any combination in the horizontal direction, and a floating p-well is provided between any two of the dummy trench structures and the gate trench structures; The dummy trench structure region of the semiconductor substrate is processed by using a local oxidation of silicon (LOCOS) process to form a recess, so that the dummy trench structure is deeper than the gate trench structure in the semiconductor device.

2. The IGBT semiconductor structure according to claim 1, characterized in that: The source region in the gate trench structure is interrupted at any ratio in the vertical direction.

3. The IGBT semiconductor structure according to claim 1 or 2, characterized in that: The depth of the enhancement region in the gate trench structure is different from the depth of the enhancement region in the dummy trench structure; Alternatively, no enhancement region is provided in the gate trench structure or the dummy trench structure; Alternatively, the depth of the enhancement region in the gate trench structure and the depth of the enhancement region in the dummy trench structure in the longitudinal direction can be adjusted.

4. The IGBT semiconductor structure according to claim 3, characterized in that: The body region in the gate trench structure and the body region in the dummy trench structure have different depths.

5. The IGBT semiconductor structure according to claim 4, characterized in that: The source contact in the dummy trench structure is interrupted at any ratio in the vertical direction.

6. The IGBT semiconductor structure according to claim 5, characterized in that: The width of the dummy trench is greater than the width of the gate trench; or the depth of the dummy trench is greater than the depth of the gate trench.

7. The IGBT semiconductor structure according to claim 6, characterized in that: The gate trench structure region of the semiconductor substrate is processed by using a local oxidation process of silicon to form a recess, so that the gate trench structure region is deeper than the dummy trench structure region in the semiconductor device.

8. The IGBT semiconductor structure according to claim 6, characterized in that: The dummy trench is not connected to the emitter and remains floating.

9. The IGBT semiconductor structure according to claim 6, characterized in that: The dummy trench is not connected to the emitter but is connected to the gate, and has a feature that the gate trench structure does not have a source region.

10. The IGBT semiconductor structure according to claim 6, characterized in that: The dummy trench structure forms a Schottky contact between the emitter electrode and the semiconductor material, and the body region in the dummy trench structure does not embed an electrode.

11. A method for manufacturing an IGBT semiconductor structure according to any one of claims 1 to 10, characterized in that: The steps include: Using a semiconductor substrate doped with a first conductivity type material; Using a mask to cover the semiconductor substrate, implanting a second conductive type dopant into a P-well region on the front side of the semiconductor substrate to form a floating P-well; After a first high temperature treatment, the floating P-well diffuses into the semiconductor substrate, and the first high temperature treatment lasts for t1min; Using a mask process on the front side of the semiconductor substrate, the semiconductor substrate is polarly etched to obtain a gate trench and a dummy trench, wherein the gap between the gate trench and the edge of the floating p-well region is Δpa, and the gap between the edge of the dummy trench and the edge of the floating p-well region is Δpd; Injecting a first conductive type material into the front surface of the semiconductor substrate to form a first conductive type enhancement layer; After a second high temperature treatment, the second high temperature treatment lasts for t2min, driving the floating p-well region and the enhancement layer to continue to penetrate, so that the bottom of the floating p-well region forms an S shape; Injecting a second conductive type material from the front side of the semiconductor substrate to form a body layer; After a third high temperature treatment, the third high temperature treatment lasts for t3min, driving the floating p-well, the enhancement layer and the main region to continue to penetrate, and obtaining a final desired pattern; Using a mask process, forming a source region and a source contact on the front side of the semiconductor substrate, and depositing a metal layer on the front side of the semiconductor substrate; The back side of the semiconductor substrate is polished, and after polishing, an anode layer and a buffer layer are sequentially arranged on the back side of the semiconductor substrate; An annealing process is used to treat the anode layer and the buffer layer to activate the anode layer and the buffer layer; A metal layer is deposited on the buffer layer.

12. The manufacturing method according to claim 11, characterized in that: Δpd and t1 are chosen in such a way that after the dummy trench etching; the dopants implanted in the p-well remain between the dummy trenches and partially compensate the dopants.

13. The manufacturing method according to claim 12, characterized in that: Δpa and t1 are chosen in such a way that after the gate trench etching; the p-well implanted dopants remain between the gate trenches and partially compensate the dopants.

14. The manufacturing method according to claim 13, characterized in that: The position of the reinforcement layer in the longitudinal direction is varied.

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