A dynamic comparator circuit with a wide input common-mode voltage range applied to a SAR ADC

Abstract

The present invention discloses a dynamic comparator circuit with a wide input common-mode voltage range applied to a SAR ADC, including: a preamplifier, a latch, and a power supply terminal VDD; both ends of the power supply terminal VDD are respectively connected to PM1 and PM2, PM1 is connected to an input pair transistor NM1, the input pair transistor NM1 is connected to VINN, PM2 is connected to an input pair transistor NM2, the input pair transistor NM2 is connected to VINP, a connection line between PM1 and the input pair transistor NM1 is connected to a comparator LATCH, and the comparator LATCH is connected to VOUTN− and VOUTP+. The novel dynamic comparator circuit applied to the SAR ADC proposed by the present invention broadens the input common-mode voltage of the comparator, weakens the performance degradation caused by input common-mode offset in the actual application of the ADC, and also weakens the channel length modulation effect of MOS devices under PVT conditions, making the performance of the dynamic comparator more stable under PVT conditions, which has engineering significance.

Description

Technical Field

[0001] The present invention relates to the technical field of comparators, and specifically to a dynamic comparator circuit with a wide input common-mode voltage range applied to a SAR ADC. Background Art

[0002] Currently, high-speed dynamic comparator circuits are widely used in high-precision SAR ADCs. The performance of the dynamic comparator directly affects the final quantization accuracy and linearity of the ADC. Under the actual working conditions of the ADC, traditional high-speed dynamic comparators are extremely vulnerable to the MOS devices operating in the non-saturation region due to the offset of the ADC input common-mode voltage, resulting in a decline in the performance of the comparator.

[0003] In view of the above problems, for this reason, we propose a dynamic comparator circuit with a wide input common-mode voltage range applied to a SAR ADC. Summary of the Invention

[0004] The purpose of the present invention is to provide a dynamic comparator circuit with a wide input common-mode voltage range applied to a SAR ADC, which solves the existing problems.

[0005] To achieve the above purpose, the present invention provides the following technical solutions:

[0006] A dynamic comparator circuit with a wide input common-mode voltage range applied to a SAR ADC, comprising:

[0007] A preamplifier and a latch,

[0008] And a power supply terminal VDD;

[0009] Both ends of the power supply terminal VDD are respectively connected to PM1 and PM2. PM1 is connected to the input pair transistor NM1. The input pair transistor NM1 is connected to VINN. PM2 is connected to the input pair transistor NM2. The input pair transistor NM2 is connected to VINP. The connection line between PM1 and the input pair transistor NM1 is connected to the comparator LATCH. The comparator LATCH is connected to VOUTN- and VOUTP+.

[0010] Preferably, the middle of the connection line between PM1 and PM2 is connected to resistor R1 and resistor R2. The gates and drains of PM1 and PM2 are connected through resistor R1 and resistor R2.

[0011] Preferably, the VFB point between resistor R1 and resistor R2 is connected to the source of PM3. PM3 is connected to resistor R3.

[0012] Preferably, the gates of PM1 and PM2 are connected to the drain of PM3. The drain and gate of PM3 are connected through R3.

[0013] Preferably, one ends of the capacitors C1 and C2 are respectively connected to the drains of the first-stage NM1 and NM2, and the other ends are connected to the input end of the latch.

[0014] Preferably, the gates and drains of the PM1 and PM2 are cross-connected to the PM3 and PM4, and the PM3 and PM4 are connected in a diode form.

[0015] Preferably, the gate and drain of the PM3 are connected to the PM5, and the gate and drain of the PM5 are connected to both ends of the resistor R1.

[0016] Preferably, the gate and drain of the PM4 are connected to the PM6, and the gate and drain of the PM6 are connected to both ends of the resistor R2.

[0017] Preferably, one ends of the capacitors C1 and C2 are respectively connected to the drains of the first-stage NM1 and NM2, and the other ends are connected to the input end of the latch.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0019] The novel dynamic comparator circuit applied to the SAR ADC proposed by the present invention broadens the input common-mode voltage of the comparator, weakens the performance degradation caused by the input common-mode offset in the actual application of the ADC, and also weakens the channel length modulation effect of the MOS device under the PVT conditions, making the performance of the dynamic comparator more stable under the PVT conditions, which has engineering significance. Description of the Drawings

[0020] Figure 1 It is a schematic structural diagram of the present invention;

[0021] Figure 2 It is a schematic circuit structure diagram of Embodiment 2 of the present invention;

[0022] Figure 3 It is a schematic circuit structure diagram of Embodiment 3 of the present invention;

[0023] Figure 4 It is a schematic circuit structure diagram of Embodiment 4 of the present invention;

[0024] Figure 5 It is a comparative schematic diagram of the present invention. Detailed Embodiments

[0025] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments.

[0026] Based on the dynamic comparator structure of the traditional "preamplifier + latch", the present invention broadens the input common-mode voltage range of the first-stage preamplifier and uses the capacitor-coupled Auto-zero technology to avoid the influence of the input common-mode voltage on the second-stage latch.

[0027] Taking the preamplifier with NMOS as the input pair transistors as an example, the traditional preamplifier has a load in the form of a diode-connected (gate-drain self-biased connection). When the MOS device in the diode-connected mode operates in the saturation region, its source-drain voltage (V DS ) must be at least greater than a threshold voltage (V TH ). Therefore, for the input pair transistors, in order to keep them operating in the saturation region, their gate voltages must be lower than the power supply voltage (V DD ) minus a threshold voltage, which is the upper limit of the input common-mode level.

[0028] On this basis, the present invention leads the gates and drains of the diode-connected MOS devices to another current branch, connects them to the source and drain of another MOS device, and the gate of this MOS device is self-biased through an adjustable resistor connected to the drain. By designing the current of this branch, the width-length ratio of this MOS device, and the value of this resistor, the drain voltage of the original diode-connected MOS device is adjusted. In this way, the V DS of the original diode-connected MOS device only needs to lose a V DSsat (=V GS - V TH ) voltage to work normally, and the upper limit of the common-mode level of the input pair transistors is thus extended to V DD - V Dsat instead of losing a V TH . In the deep sub-micron CMOS process, using this structure not only broadens the common-mode input but also weakens the channel length modulation effect of the MOS device under PVT, making the performance such as the gain bandwidth of the first-stage preamplifier more stable.

[0029] The output of the first stage is capacitively coupled to the input of the second-stage latch, and the switch-controlled Auto-zero technology is used at the input of the latch, so that the offset of the input common-mode level of the first stage does not affect the input common-mode of the second stage, and effectively reduces the offset of the first-stage preamplifier.

[0030] Embodiment 1:

[0031] As Figure 1 shown, a dynamic comparator circuit with a wide input common-mode voltage range applied to SAR ADC. Since the gates and drains of PM1 / PM2 are connected through resistors R1 / R2, the input common-mode voltage of NM1 and NM2 needs to be less than V DD-V TH .

[0032] Embodiment 2:

[0033] As Figure 2 shown, based on the specific Embodiment 1, connect the VFB point between R1 and R2 to the source of PM3, connect the gates of PM1 / PM2 to the drain of PM3, connect the drain and gate of PM3 through R3, and by adjusting the current of this branch, the size of PM3 and the resistance value of R3, while ensuring that the common-mode feedback function of the original circuit remains unchanged, effectively increase the maximum common-mode level of the input pair transistors NM1 / NM2 to V DD -V DSsat . At the same time, add the circuit in the yellow box before the second-stage latch. One end of capacitors C1 and C2 is connected to the drains of the first-stage NM1 and NM2, and the other end is connected to the input of the latch. Add a switch-controlled Auto-zero circuit, so that the input common-mode level of the latch is independently controlled by VCM_AZ and is not affected by the input common-mode voltage of the first stage, effectively expanding the input common-mode voltage range of the entire dynamic comparator.

[0034] Figure 5 Shows the comparison of the dynamic comparators with the traditional structure and the patented structure in terms of some amplifier performances. It can be clearly seen that the performances of using this patent are flatter with the change of the input common-mode level.

[0035] Embodiment 3:

[0036] As Figure 3 shown, based on the specific Embodiment 1, since the gates and drains of PM1 and PM2 are cross-connected, and PM3 and PM4 are connected in a diode form, the input common-mode voltage of NM1 and NM2 needs to be less than V DD -V TH .

[0037] Embodiment 4:

[0038] As Figure 4 shown, based on the specific Embodiment 3, by the same connection method as Figure 1 , add PM5 and R1 to change the connection method of the gates and drains of PM1 and PM3, add PM6 and R2 to change the connection method of the gates and drains of PM2 and PM4, while ensuring that the hysteresis function of the original circuit remains unchanged, effectively increase the maximum common-mode level of the input pair transistors NM1 / NM2 to V DD -V DSsat .

[0039] Although embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A dynamic comparator circuit for wide input common mode voltage range in SAR ADC, characterized in that: include: Pre-amplifier and latch, and a power supply terminal VDD; The two ends of the power supply terminal VDD are connected to PM1 and PM2 respectively, PM1 is connected to the input pair tube NM1, the input pair tube NM1 is connected to VINN, PM2 is connected to the input pair tube NM2, the input pair tube NM2 is connected to VINP, the connection line between PM1 and the input pair tube NM1 is connected to the comparator LATCH, and the comparator LATCH is connected to VOUTN- and VOUTP+; The middle part of the PM1 and PM2 connection line is connected to resistors R1 and R2, and the gates and drains of PM1 and PM2 are connected through resistors R1 and R2; A VFB point between the resistor R1 and the resistor R2 is connected to the source of PM3, and PM3 is connected to the resistor R3.

2. A dynamic comparator circuit for wide input common mode voltage range in SAR ADC according to claim 1, characterized in that: The gates of PM1 and PM2 are connected to the drain of PM3, and the drain and gate of PM3 are connected via R3.

3. The dynamic comparator circuit for wide input common mode voltage range in SAR ADC according to claim 1, characterized in that: One end of the capacitor C1 and the capacitor C2 are connected to the drain of the first stage NM1 and NM2 respectively, and the other end is connected to the input end of the latch.

4. A dynamic comparator circuit for wide input common mode voltage range in SAR ADC, characterized in that: include: Pre-amplifier and latch, and a power supply terminal VDD; The two ends of the power supply terminal VDD are connected to PM1 and PM2 respectively, PM1 is connected to the input pair tube NM1, the input pair tube NM1 is connected to VINN, PM2 is connected to the input pair tube NM2, the input pair tube NM2 is connected to VINP, the connection line between PM1 and the input pair tube NM1 is connected to the comparator LATCH, and the comparator LATCH is connected to VOUTN- and VOUTP+; The gates and drains of PM1 and PM2 are cross-connected to PM3 and PM4, and PM3 and PM4 are connected in the form of diodes.

5. A dynamic comparator circuit for wide input common mode voltage range in SAR ADC according to claim 4, characterized in that: The gate and drain of PM3 are connected to PM5, and the gate and drain of PM5 are connected to two ends of the resistor R1.

6. A dynamic comparator circuit for wide input common mode voltage range in SAR ADC according to claim 4, characterized in that: The gate and drain of PM4 are connected to PM6, and the gate and drain of PM6 are connected to two ends of resistor R2.

7. The dynamic comparator circuit for wide input common mode voltage range in SAR ADC according to claim 4, characterized in that: One end of the capacitor C1 and the capacitor C2 are connected to the drain of the first stage NM1 and NM2 respectively, and the other end is connected to the input end of the latch.

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