Quantum bit interface circuit and quantum bit computing system

Abstract

The application provides a quantum bit interface circuit and a quantum bit computing system. The quantum bit interface circuit comprises a controller, a bit state control circuit and a bit state readout circuit. The controller is configured to generate a state control parameter and a state readout parameter according to a control instruction. The bit state control circuit is configured to output a state control signal to a quantum bit device according to the state control parameter, and the state control signal is configured to set a first state of a plurality of quantum bits. The bit state readout circuit is configured to output an excitation signal to the quantum bit device according to the state readout parameter, and receive a reflection signal of the plurality of quantum bits. The bit state readout circuit is further configured to determine a second state of the plurality of quantum bits according to the excitation signal and the reflection signal. The application communicates with a quantum computing device through the controller, obtains a control instruction, and controls the bit state control circuit and the bit state readout circuit to work according to the control instruction, so as to realize state control and state readout of the quantum bit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of quantum information, and in particular to a quantum bit interface circuit and a quantum bit computing system. BACKGROUND

[0002] The biggest challenge of large-scale quantum computing at present is how to further increase the number of integrated quantum bits and reduce the volume of quantum computing platforms. At present, quantum bits in quantum computing platforms need to work in an ultra-low temperature environment, while quantum bit state control and readout devices with a large volume need to work at room temperature. Therefore, a cross-temperature interconnection line needs to be set between the quantum bits and the quantum bit state control and readout devices to realize the normal operation of the two. In this way, the occupied space of the quantum computing platform is further increased. SUMMARY

[0003] In order to solve the problems in the prior art, the present application provides a quantum bit interface circuit and a quantum bit computing system.

[0004] The present application provides a quantum bit interface circuit electrically connected with a quantum bit device, the quantum bit device comprising a plurality of quantum bits, and the quantum bit interface circuit comprising:

[0005] a controller configured to receive a control instruction and generate a state control parameter and a state readout parameter according to the control instruction;

[0006] a bit state control circuit configured to output a state control signal to the quantum bit device according to the state control parameter, the state control signal being configured to set a first state of the plurality of quantum bits;

[0007] a bit state readout circuit configured to output an excitation signal to the quantum bit device according to the state readout parameter and receive a reflection signal of the plurality of quantum bits, and determine a second state of the plurality of quantum bits according to the excitation signal and the reflection signal.

[0008] In an embodiment, the bit state readout circuit comprises:

[0009] a local oscillator generation circuit configured to generate a carrier signal of a first preset frequency;

[0010] an excitation signal generation circuit electrically connected with the local oscillator generation circuit and the quantum bit device, respectively, and configured to generate a plurality of excitation signals according to the carrier signal;

[0011] a reflection signal receiving circuit electrically connected with the local oscillator generation circuit and the quantum bit device, and configured to receive a reflection signal of the plurality of quantum bits;

[0012] bit state detection circuit, electrically connected with the excitation signal generation circuit and the reflection signal receiving circuit respectively, for determining second states of the plurality of quantum bits according to the excitation signal and the reflection signal.

[0013] In an embodiment, the excitation signal generation circuit comprises:

[0014] a plurality of excitation signal baseband circuits, the plurality of excitation signal baseband circuits being configured to generate a plurality of single-tone excitation baseband signals with different frequencies according to the state readout parameter; the number of the excitation signal baseband circuits being consistent with the number of the quantum bits;

[0015] a first mixer, electrically connected with the local oscillator generation circuit and the plurality of excitation signal baseband circuits respectively; the first mixer being configured to generate a multi-tone excitation signal according to the carrier signal and the plurality of single-tone excitation baseband signals, and output to the quantum bit device.

[0016] In an embodiment, the excitation signal baseband circuit comprises:

[0017] a phase-locked loop, configured to generate a plurality of clock signals with different phases according to the state readout parameter, and output to the bit state detection circuit;

[0018] a plurality of first amplifiers, electrically connected with the phase-locked loop respectively; the first amplifiers being configured to convert the plurality of clock signals into a plurality of current signals, and output to the first mixer, the first mixer;

[0019] The plurality of excitation signal baseband circuits are configured to generate the plurality of current signals with different frequencies; and the first mixer is configured to generate the multi-tone excitation signal based on the carrier signal and the plurality of current signals with different frequencies.

[0020] In an embodiment, the reflection signal receiving circuit comprises:

[0021] a second mixer, electrically connected with the local oscillator generation circuit, configured to receive a plurality of reflection signals of the plurality of quantum bits and the carrier signal, and perform a down-conversion operation based on the plurality of reflection signals and the carrier signal, and output a plurality of reflection baseband signals;

[0022] a plurality of reflection signal baseband circuits, respectively electrically connected with the second mixers, and respectively electrically connected with the plurality of phase-locked loops one by one; the plurality of reflection signal baseband circuits are used for filtering a plurality of reflection baseband signals output by the second mixers, separating the plurality of reflection baseband signals according to different frequencies, and outputting the separated plurality of reflection baseband signals to the bit state detection circuit; the number of the reflection signal baseband circuits is consistent with the number of the quantum bits;

[0023] The bit state readout circuit is used for determining the second state of the corresponding quantum bit according to the excitation signal and the reflection signal under the same frequency.

[0024] In an embodiment, the reflection signal baseband circuit comprises:

[0025] An N-channel filter, respectively electrically connected with the phase-locked loop and the second mixer, is used for filtering the plurality of reflection baseband signals;

[0026] A second amplifier is used for amplifying the reflection baseband signals filtered by the N-channel filter.

[0027] In an embodiment, the number of the quantum bits is N, N is greater than 1 and is an integer, the number of the bit state detection circuits is consistent with the number of the quantum bits, and the plurality of bit state detection circuits are respectively and electrically connected with the plurality of excitation signal baseband circuits and the plurality of reflection signal baseband circuits one by one; the bit state detection circuit comprises:

[0028] A first frequency divider, electrically connected with the Nth excitation signal baseband circuit, is used for reducing the frequency of the Nth excitation baseband signal output by the Nth excitation signal baseband circuit;

[0029] A second frequency divider, electrically connected with the Nth reflection signal baseband circuit, is used for reducing the frequency of the Nth reflection baseband signal output by the Nth reflection signal baseband circuit;

[0030] A time data converter, respectively electrically connected with the first frequency divider and the second frequency divider, is used for detecting the phase difference between the Nth excitation baseband signal and the Nth reflection baseband signal;

[0031] A state decision circuit, electrically connected with the time data converter, is used for determining the second state of the corresponding quantum bit according to the phase difference.

[0032] In an embodiment, the bit state control circuit comprises:

[0033] An XY-axis controller, the XY-axis controller is used for outputting an XY-axis control signal to the quantum bit device according to the state control parameter.

[0034] a Z-axis controller configured to output a Z-axis control signal to the qubit device according to the state control parameter.

[0035] In an embodiment, the qubit interface circuit further comprises a communication interface.

[0036] The communication interface is electrically connected with the controller, and is configured to receive the control instruction and output a parameter representing the second state.

[0037] The present application also provides a qubit computing system, which comprises a qubit device, a quantum computing device and the qubit interface circuit.

[0038] The qubit device comprises a plurality of qubits, the quantum computing device is configured to output a control instruction according to a preset state parameter of the plurality of qubits, the control instruction is configured to control the qubit interface circuit to output a state control parameter and a state readout parameter, the state control parameter is configured to control a first state of the plurality of qubits in the qubit device, the state readout parameter is configured to detect a second state of the plurality of qubits, and the qubit interface circuit is further configured to output a parameter representing the second state of the plurality of qubits to the quantum computing device.

[0039] The quantum computing device is further configured to determine that the corresponding qubit state is normal when the preset state parameter is consistent with the parameter corresponding to the second state, and determine that the corresponding qubit state is abnormal when the preset state parameter is inconsistent with the parameter corresponding to the second state.

[0040] The present application communicates with the quantum computing device through the controller, obtains the control instruction, and controls the bit state control circuit and the bit state readout circuit to work according to the control instruction. The state control signal is output through the bit state control circuit to set the first state of the qubit. The second state of the qubit is read through the bit state readout circuit. By integrating the controller, the bit state control circuit and the bit state readout circuit in one circuit, it can work directly in an ultra-low temperature environment or at room temperature, while realizing the control and state readout of the qubit. The number of room temperature devices and the number of cross-temperature interconnection lines required for the measurement and control of the qubit are reduced, thereby effectively reducing the volume of the existing quantum computing system. In addition, by simultaneously reading out the readout of a plurality of qubits through the bit state readout circuit, the bit state readout time can be shortened and the power consumption can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 FIG. 1 is a structural schematic diagram of a qubit interface circuit according to an embodiment of the present application.

[0042] Figure 2 Structure diagram of a bit state control circuit according to an embodiment of the present application.

[0043] Figure 3 Structure diagram of a bit state readout circuit according to an embodiment of the present application.

[0044] Figure 4 Structure diagram of an excitation signal generation circuit and a reflected signal receiving circuit according to an embodiment of the present application.

[0045] Figure 5 Structure diagram of a bit state detection circuit according to an embodiment of the present application.

[0046] Explanation of main component symbols

[0047] Quantum bit interface circuit 10 Controller 11 Bit state control circuit 12 Bit state readout circuit 13

[0048] XY-axis controller 121 Z-axis controller 122

[0049] Local oscillator generation circuit 131 Excitation signal generation circuit 132 Reflected signal receiving circuit 133 Bit state detection circuit 134 Excitation signal baseband circuit 1321 First mixer 1322

[0050] Driver 1323 Phase-locked loop PLL

[0051] First amplifier Q1 First filter T1

[0052] Second mixer 1331 Reflected signal baseband circuit 1332

[0053] Low-noise amplifier 1334 Transconductance amplifier 1335

[0054] N-channel filter TN Second amplifier Q2

[0055] Second filter T2 First frequency divider 1341

[0056] Second frequency divider 1342 Time data converter 1343

[0057] State decision circuit 1344 Quantum bit computing system 1

[0058] Quantum bit device 20 Quantum computing apparatus 30

[0059] Rat race 40 Communication interface 14

[0060] The following detailed description will further describe the present application with reference to the above mentioned figures. DETAILED DESCRIPTION

[0061] The following description will refer to the accompanying drawings, which are meant to further describe the present application. The drawings presented herein are examples of the present application. However, the present application can be implemented in many different forms and should not be interpreted as limited to the exemplary embodiments set forth herein. These exemplary embodiments are provided in order to give a thorough and complete disclosure of the present application and to convey the scope of the present application to those skilled in the art. Like reference numerals refer to like or similar components throughout.

[0062] With reference to Figure 1 The present application proposes a quantum bit interface circuit 10, which is electrically connected with a quantum bit device 20, the quantum bit device 20 comprises a plurality of quantum bits, the quantum bit interface circuit 10 comprises a controller 11, a bit state control circuit 12 and a bit state readout circuit 13. The controller 11 is configured to receive a control instruction and generate a state control parameter and a state readout parameter according to the control instruction. The bit state control circuit 12 is configured to output a state control signal to the quantum bit device 20 according to the state control parameter, the state control signal is configured to set a first state of the plurality of quantum bits. The bit state readout circuit 13 is configured to output an excitation signal to the quantum bit device 20 according to the state readout parameter, and receive a reflection signal of the plurality of quantum bits; the bit state readout circuit 13 is further configured to determine a second state of the plurality of quantum bits according to the excitation signal and the reflection signal.

[0063] In an embodiment, the quantum bit interface circuit 10 further comprises a communication interface 14. The communication interface 14 is electrically connected with the controller 11; the communication interface 14 is configured to receive the control instruction, and output a parameter for representing the second state.

[0064] In this embodiment, the quantum bit interface circuit 10 can be an integrated circuit, for example, various elements in the quantum bit interface circuit 10 are integrated on a circuit board. The controller 11 can be an on-chip controller. The control instruction can be output by the quantum computing device 30. The user can set the state parameters of the plurality of quantum bits in the quantum computing device 30, and the quantum computing device 30 generates the corresponding control instruction according to the state parameters of the plurality of quantum bits, and transmits it to the controller 11 through the communication interface 14. The controller 11 generates the state control parameter according to the control instruction, and outputs it to the bit state control circuit 12, so as to control the bit state control circuit 12 to output the state control signal to the quantum bit device 20, and then adjust the state of the plurality of quantum bits to the first state. The controller 11 can also generate a state readout parameter according to the control instruction to control the bit state readout circuit 13 to output an excitation signal to the quantum bit device 20. Because the state of the quantum bit will affect the phase and amplitude of the input excitation signal, and then generate different reflection signals. The bit state readout circuit 13 can determine the second state of the plurality of quantum bits according to the difference between the excitation signal and the reflection signal. The controller 11 is also used to generate a plurality of second state parameters according to the second state of the plurality of quantum bits, and transmit them to the quantum computing device 30 through the communication interface 14. The quantum computing device 30 can compare the second state parameters of the plurality of quantum bits with the pre-set state parameters of the plurality of quantum bits, if they are consistent, it means that the corresponding quantum bit completes the state adjustment. If they are not consistent, it means that the corresponding quantum bit does not realize the expected state adjustment.

[0065] Referring to Figure 2 In an embodiment, the bit state control circuit 12 includes an XY-axis controller 121 and a Z-axis controller 122. The XY-axis controller 121 is used to output an XY-axis control signal to the quantum bit device 20 according to the state control parameter. The Z-axis controller 122 is used to output a Z-axis control signal to the quantum bit device 20 according to the state control parameter.

[0066] In this embodiment, the XY-axis control signal and the Z-axis control signal can be pulse signals, and the XY-axis control signal can include a phase parameter, a frequency parameter and an envelope parameter. The Z-axis control signal can include a duty cycle parameter and an envelope parameter. In this way, under the action of the XY-axis control signal and the Z-axis control signal, the state control of the quantum bit is realized.

[0067] Referring to Figure 3In an embodiment, the bit state readout circuit 13 comprises a local oscillator generating circuit 131, an excitation signal generating circuit 132, a reflected signal receiving circuit 133, and a bit state detecting circuit 134. The local oscillator generating circuit 131 is configured to generate a carrier signal with a first preset frequency. The excitation signal generating circuit 132 is electrically connected to the local oscillator generating circuit 131 and the quantum bit device 20, respectively, and configured to generate the plurality of excitation signals according to the carrier signal. The reflected signal receiving circuit 133 is electrically connected to the quantum bit device 20 and configured to receive a plurality of reflected signals of the quantum bits. The bit state detecting circuit 134 is electrically connected to the excitation signal generating circuit 132 and the reflected signal receiving circuit 133, respectively, and configured to determine the second states of the plurality of quantum bits according to the excitation signals and the reflected signals.

[0068] In the embodiment, the local oscillator generating circuit 131 can generate a carrier signal with a first preset frequency (e.g., 6-10 GHz) according to the state readout parameters, and output to the excitation signal generating circuit 132 and the reflected signal receiving circuit 133, respectively. The excitation signal generating circuit 132 generates a plurality of excitation signals according to the carrier signal and outputs to the quantum bit device 20. The quantum bit device 20 further comprises a resonant cavity. Since the state of the quantum bit directly affects the characteristic change of the resonant cavity, it further causes the phase and amplitude change of the input excitation signal, and generates a reflected signal. The reflected signal receiving circuit 133 receives the reflected signal, and outputs to the bit state detecting circuit 134 after processing the reflected signal according to the carrier signal. The bit state detecting circuit 134 determines the state of the plurality of quantum bits according to the phase difference between the excitation signal and the reflected signal. For example, the phase difference information distribution of different quantum bit states can be determined by multiple measurements, and then a threshold phase difference is determined, which is used as a judgment basis. For the quantum bit with a phase difference greater than the threshold phase difference, it is determined that the quantum bit is in the |1> state (|0> state); for the quantum bit with a phase difference less than the threshold phase difference, it is determined that the quantum bit is in the |0> state (|1> state).

[0069] Reference Figure 4 In an embodiment, the excitation signal generating circuit 132 comprises a plurality of excitation signal baseband circuits 1321 and a first frequency mixer 1322. The number of the excitation signal baseband circuits 1321 is consistent with the number of the quantum bits. The plurality of excitation signal baseband circuits 1321 are configured to generate a plurality of single-tone excitation baseband signals with different frequencies according to the state readout parameters. The first frequency mixer 1322 is electrically connected to the local oscillator generating circuit 131 and the plurality of excitation signal baseband circuits 1321, respectively. The first frequency mixer 1322 is configured to generate a multi-tone excitation signal according to the carrier signal and the plurality of single-tone excitation baseband signals, and output to the quantum bit device 20.

[0070] In this embodiment, the number of excitation signal baseband circuits 1321 can be set according to the number of qubits. The state readout parameters can control the plurality of excitation signal baseband circuits 1321 to generate a plurality of single-tone excitation baseband signals of different frequencies according to the characteristics of a plurality of qubits. The frequency of the single-tone excitation baseband signal can be determined according to the characteristics of the corresponding qubit. The first mixer 1322 first performs an up-conversion operation on a plurality of single-tone excitation baseband signals, superimposes a plurality of single-tone excitation baseband signals with a carrier signal to form a plurality of excitation signals of different frequencies, so as to increase the frequency of the excitation signal to a frequency that can be received by the qubit device 20. For example, the number of excitation signal baseband circuits 1321 is N, the frequency of the single-tone excitation baseband signal is f bb,N , and the frequency of the superimposed single-tone excitation signal is f bb,N +f LO . Then, the first mixer 1322 synthesizes a plurality of single-tone excitation signals to form a multi-tone excitation signal. In this way, through a plurality of excitation signal baseband circuits 1321 and a first mixer 1322, a multi-tone excitation signal can be output to the qubit device 20, so that the multi-tone excitation signal simultaneously acts on a plurality of qubits, and a plurality of qubits are excited to generate reflection signals, thereby realizing simultaneous readout of a plurality of qubit states, reducing the readout time of a plurality of qubit states, and reducing the readout power consumption.

[0071] In an embodiment, the excitation signal generation circuit 132 further includes a driver 1323. The driver 1323 is electrically connected to the first mixer 1322 and the qubit device 20, respectively. The driver 1323 is used to improve the driving capability of the multi-tone excitation signal, thereby improving the accuracy of the qubit state readout.

[0072] In an embodiment, the excitation signal baseband circuit 1321 includes a phase-locked loop (PLL) and a plurality of first amplifiers Q1. The phase-locked loop (PLL) is used to generate a plurality of clock signals of different phases according to the state readout parameters and output to the bit state detection circuit 134. The plurality of first amplifiers Q1 are electrically connected to the phase-locked loop (PLL), respectively. The first amplifiers Q1 are used to convert the clock signals into current signals and output to the first mixer 1322. A plurality of excitation signal baseband circuits 1321 are used to generate a plurality of current signals of different frequencies. The first mixer 1322 is used to generate the multi-tone excitation signal based on the carrier signal and the plurality of current signals of different frequencies.

[0073] In this embodiment, the phase-locked loop (PLL) can be implemented based on a circuit topology of a multi-phase ring oscillator. The operating frequency of the phase-locked loop (PLL) can be set to f bb,N. Thus, the phase-locked loop PLL generates a plurality of clock signals with different phases, which are amplified by a plurality of first amplifiers Q1 respectively, to form a plurality of current signals with different phases and a frequency of f bb,N , i.e. single-tone excitation baseband signals. The excitation signal baseband circuit 1321 generates current signals with different frequencies. The current signals with different frequencies are superimposed with the carrier signal in the first frequency mixer 1322 to form multi-tone excitation signals.

[0074] In an embodiment, the excitation signal baseband circuit 1321 can further include a first filter T1. Each first filter T1 is electrically connected to the phase-locked loop PLL and a first amplifier Q1 respectively. The first filter T1 can be implemented by a Chebyshev third-order filter. The first filter T1 performs harmonic suppression on the clock signal generated by the phase-locked loop PLL to ensure that the single-tone excitation baseband signal achieves a high harmonic suppression rate. The first amplifier Q1 is used to convert the voltage domain signal output by the filter into a current domain signal, and to realize the synthesis of a plurality of single-tone excitation baseband signals with different frequencies in the first frequency mixer 1322 to generate frequency division multiplexing multi-tone excitation signals.

[0075] Referring to Figure 4 , in an embodiment, the reflected signal receiving circuit 133 includes a second frequency mixer 1331 and a plurality of reflected signal baseband circuits 1332. The number of reflected signal baseband circuits 1332 is consistent with the number of quantum bits. The plurality of reflected signal baseband circuits 1332 are electrically connected to the second frequency mixer 1331, and the plurality of reflected signal baseband circuits 1332 are also electrically connected to the plurality of phase-locked loops PLL one by one. The plurality of reflected signal baseband circuits 1332 are used to filter a plurality of reflected baseband signals, to separate the plurality of reflected baseband signals according to different frequencies, and to output the separated reflected baseband signals to the corresponding bit state detection circuit 134 one by one. The bit state readout circuit 13 is used to determine the second state of the corresponding quantum bit according to the excitation signal and the reflected signal under the same frequency.

[0076] In this embodiment, the second frequency mixer 1331 receives a plurality of reflected signals of the plurality of quantum bits and the carrier signal output by the local oscillator generation circuit 131, performs down-conversion operation on the reflected signals, and outputs the reflected signals to the plurality of reflected signal baseband circuits 1332 to reduce the frequency of the reflected signals to a frequency that can be received by the reflected signal baseband circuit 1332. Then, the plurality of reflected signal baseband circuits 1332 perform filtering to determine the frequency of the reflected signal, and output the reflected signal to the bit state detection circuit 134. For example, the number of reflected signal baseband circuits 1332 is N, and the frequency of the reflected signal of the Nth quantum bit is f q,N , and the frequency of the Nth reflected baseband signal after down-conversion is f q,N -f LOThe filter frequency of the plurality of reflection signal baseband circuits 1332 can be set to be the same as the frequency of the plurality of single-tone excitation baseband signals. The frequency of the plurality of reflection signals generated by the plurality of quantum bits for the multi-tone excitation signal after down-conversion is consistent with the frequency of the plurality of single-tone excitation baseband signals. In this way, the reflection signal with the first frequency can only pass through the reflection signal baseband circuit 1332 with the first frequency band-pass filtering characteristic, so that the reflection signal with the first frequency can be separated from the plurality of reflection signals, so that the bit state detection circuit 134 can calculate the excitation signal and the reflection signal with the same frequency to determine the state of the corresponding quantum bit.

[0077] In an embodiment, the reflection signal receiving circuit 133 further includes a low noise amplifier 1334 and a transconductance amplifier 1335, and the quantum bit device 20, the low noise amplifier 1334 and the transconductance amplifier 1335 are electrically connected in sequence. The low noise amplifier 1334 is used to receive the plurality of reflection signals of the plurality of quantum bits, reduce the overall noise figure of the reflection signal receiving circuit 133, improve the sensitivity, provide gain to amplify the weak reflection signal. The transconductance amplifier 1335 is used to further amplify the reflection signal output by the low noise amplifier 1334, improve the gain of the front end of the second mixer 1331, suppress the noise of the latter stage, and at the same time improve the driving ability of the reflection signal to drive the latter stage of the mixer circuit.

[0078] In an embodiment, the reflection signal baseband circuit 1332 includes an N-channel filter TN and a second amplifier Q2. The N-channel filter TN is electrically connected to the phase-locked loop PLL and the second mixer 1331 respectively, and is used to filter the plurality of reflection baseband signals and output the reflection baseband signal of the second preset frequency. The second amplifier Q2 is used to amplify the reflection baseband signal filtered by the N-channel filter TN.

[0079] In this embodiment, the N-channel filter TN samples under the control of the clock signal of a specific phase output by the phase-locked loop PLL. For example, the phase-locked loop PLL outputs a first clock signal to the N-channel filter TN of the first reflection signal baseband circuit 1332, outputs a second clock signal to the N-channel filter TN of the second reflection signal baseband circuit 1332, and so on. In this way, the N-channel filter TN under the reflection signal baseband circuit 1332 can realize the suppression of other channel reflection signals. The second amplifier Q2 is used to amplify the signal output by the N-channel filter TN and convert it into a full-swing signal, which is convenient for the bit state detection circuit 134 to process.

[0080] In an embodiment, the reflection signal baseband circuit 1332 further includes a second filter T2, which is used to effectively suppress the out-of-band harmonic signal output by the N-channel filter TN and improve the signal-to-noise ratio of the useful signal. The second filter T2 can be implemented by a third-order low-pass filter.

[0081] In an embodiment, the number of quantum bits is N, N is greater than 1 and is an integer, the number of bit state detection circuits 134 is consistent with the number of quantum bits, and the plurality of bit state detection circuits 134 are respectively and one-to-one electrically connected with the plurality of excitation signal baseband circuits 1321 and the plurality of reflection signal baseband circuits 1332. Referring to Figure 5 , the bit state detection circuit 134 includes a first frequency divider 1341, a second frequency divider 1342, a time data converter 1343, and a state decision circuit 1344. The first frequency divider 1341 is electrically connected with the Nth excitation signal baseband circuit 1321, and is used to reduce the frequency of the Nth excitation baseband signal output by the Nth excitation signal baseband circuit 1321. The second frequency divider 1342 is electrically connected with the Nth reflection signal baseband circuit 1332, and is used to reduce the frequency of the Nth reflection baseband signal output by the Nth reflection signal baseband circuit 1332. The time data converter 1343 is respectively electrically connected with the first frequency divider 1341 and the second frequency divider 1342, and is used to detect the phase difference of the Nth excitation baseband signal and the Nth reflection baseband signal. The state decision circuit 1344 is electrically connected with the time data converter 1343, and is used to determine the second state of the corresponding quantum bit according to the phase difference.

[0082] In this embodiment, the first frequency divider 1341 and the second frequency divider 1342 are respectively used for frequency division processing of the Nth excitation baseband signal and the Nth reflection baseband signal. Since the bit state detection circuit 134 is mainly used for signal phase difference detection, the frequency division processing does not change the phase relationship of the two signals. In this way, after frequency division processing, it can not only ensure the normal work of the later stage circuit, but also reduce the power consumption of the later stage circuit. The time data converter 1343 quantizes the phase difference of the two signals in the time domain, obtains the phase difference information, and inputs it to the state decision circuit 1344. The state decision circuit 1344 determines the second state of the quantum bit to be measured according to the received phase difference and the threshold phase difference. The measurement of the quantum bit can be performed multiple times to realize the average processing of multiple measurement results and improve the measurement accuracy.

[0083] The application communicates with the quantum computing device 30 through the controller 11, acquires a control instruction, and controls the bit state control circuit 12 and the bit state readout circuit 13 to work according to the control instruction. The state control signal is output through the bit state control circuit 12 to set the first state of the quantum bit. The second state of the quantum bit is read out through the bit state readout circuit 13. By integrating the controller 11, the quantum bit interface circuit 10 and the bit state readout circuit 13 in one circuit, it can work directly in an ultra-low temperature environment or at room temperature, while realizing the state control and state readout of the quantum bit. The number of room temperature devices and the number of cross-temperature interconnection lines required for quantum bit measurement and control are reduced, thereby effectively reducing the volume of the existing quantum computing system. In addition, the bit state readout circuit 13 can realize the readout of multiple quantum bits at the same time, which can shorten the bit state readout time and reduce the power consumption.

[0084] The application also proposes a quantum bit computing system 1, which comprises a quantum bit device 20, a quantum computing device 30 and the above-mentioned quantum bit interface circuit 10. The quantum bit device 20 comprises a plurality of quantum bits, the quantum computing device 30 is used for outputting a control instruction according to a preset state parameter of the plurality of quantum bits, the control instruction is used for controlling the quantum bit interface circuit 10 to output a state control parameter and a state readout parameter; the state control parameter is used for controlling the first state of the plurality of quantum bits in the quantum bit device 20; the state readout parameter is used for detecting the second state of the plurality of quantum bits; and the quantum bit interface circuit 10 is further used for outputting a parameter for representing the second state of the plurality of quantum bits to the quantum computing device 30. The quantum computing device 30 is further used for determining that the corresponding quantum bit state is normal when the preset state parameter and the parameter corresponding to the second state are consistent, that is, the quantum bit has completed the state setting according to the preset state parameter and can be used for subsequent quantum computing. The quantum computing device 30 is further used for determining that the corresponding quantum bit state is abnormal when the preset state parameter and the parameter corresponding to the second state are inconsistent, that is, the quantum bit has not completed the state setting according to the preset state parameter. At this time, the quantum computing device 30 can output an abnormal prompt for the staff to overhaul.

[0085] The detailed structure of the quantum bit computing system 1 can refer to the above-mentioned embodiments, which will not be described here again; it can be understood that, since the above-mentioned quantum bit computing system 1 is used in the quantum bit interface circuit 10 of the application, the embodiments of the quantum bit interface circuit 10 of the application include all the technical solutions of all the embodiments of the above-mentioned quantum bit computing system 1, and the technical effects achieved are also completely the same, which will not be described here again.

[0086] In one embodiment, the qubit device 20 further includes a circulator 40. The circulator 40 is used to receive an excitation signal and output it to a plurality of qubits; and to receive a reflected signal and output it to the qubit interface circuit 10.

[0087] In one embodiment, there can be multiple qubit interface circuits 10. Since the qubit interface circuits 10 have a unified communication interface 14, they can be matrix-reused in large-scale quantum computing systems, thereby achieving large-scale integration of the qubit interface circuits 10.

[0088] The specific embodiments of this application have been described above with reference to the accompanying drawings. However, those skilled in the art will understand that various changes and substitutions can be made to the specific embodiments of this application without departing from the spirit and scope of this application. All such changes and substitutions fall within the scope defined by this application.

Claims

1. A quantum bit interface circuit, electrically connected to a quantum bit device, the quantum bit device comprising a plurality of quantum bits, characterized in that, The quantum bit interface circuit includes: The controller is used to receive control commands and generate status control parameters and status readout parameters based on the control commands. A bit state control circuit is provided, which is used to output a state control signal to the quantum bit device according to the state control parameters; the state control signal is used to set a first state for a plurality of the quantum bits. A bit state readout circuit is configured to output an excitation signal to the qubit device according to the state readout parameters, and to receive reflected signals from a plurality of qubits; the bit state readout circuit is further configured to determine a second state of the plurality of qubits based on the excitation signal and the reflected signal. The bit state readout circuit includes: a local oscillator generation circuit for generating a carrier signal of a first preset frequency; an excitation signal generation circuit electrically connected to the local oscillator generation circuit and the quantum bit device, for generating the excitation signal based on the carrier signal; a reflection signal receiving circuit electrically connected to the local oscillator generation circuit and the quantum bit device, for receiving reflection signals from a plurality of quantum bits; and a bit state detection circuit electrically connected to the excitation signal generation circuit and the reflection signal receiving circuit, for determining a second state of the plurality of quantum bits based on the excitation signal and the reflection signal. The excitation signal generation circuit includes: multiple excitation signal baseband circuits, which are used to generate multiple single-tone excitation baseband signals of different frequencies according to the state readout parameters; the number of excitation signal baseband circuits is consistent with the number of qubits; a first mixer is electrically connected to the local oscillator generation circuit and the multiple excitation signal baseband circuits respectively; the first mixer is used to generate a multi-tone excitation signal according to the carrier signal and the multiple single-tone excitation baseband signals, and output it to the qubit device; The reflected signal receiving circuit includes: a second mixer electrically connected to the local oscillator generating circuit, used to receive multiple reflected signals from multiple qubits and the carrier signal, and perform down-conversion operation based on the multiple reflected signals and the carrier signal to output multiple reflected baseband signals; multiple reflected signal baseband circuits electrically connected to the second mixer respectively, and the multiple reflected signal baseband circuits are also electrically connected to multiple phase-locked loops one-to-one; the multiple reflected signal baseband circuits are used to filter the multiple reflected baseband signals output by the second mixer to separate the multiple reflected baseband signals according to different frequencies, and output the separated multiple reflected baseband signals to the bit state detection circuit; the number of reflected signal baseband circuits is consistent with the number of qubits; the bit state readout circuit is used to determine the second state of the corresponding qubit according to the excitation signal and the reflected signal at the same frequency.

2. The quantum bit interface circuit as described in claim 1, characterized in that, The excitation signal baseband circuit includes: A phase-locked loop is used to generate multiple clock signals with different phases based on the state readout parameters and output them to the bit state detection circuit. Multiple first amplifiers are electrically connected to the phase-locked loop, respectively; the first amplifiers are used to convert the clock signal into a current signal and output it to the first mixer; Multiple excitation signal baseband circuits are used to generate multiple current signals of different frequencies; the first mixer is used to generate the multi-tone excitation signal based on the carrier signal and the multiple current signals of different frequencies.

3. The quantum bit interface circuit as described in claim 1, characterized in that, The reflected signal baseband circuit includes: An N-channel filter, electrically connected to the phase-locked loop and the second mixer respectively, is used to filter the plurality of reflected baseband signals; The second amplifier is used to amplify the reflected baseband signal after it has been filtered by the N-channel filter.

4. The quantum bit interface circuit as described in claim 1, characterized in that, The number of qubits is N, where N is greater than 1 and is an integer. The number of bit state detection circuits is the same as the number of qubits. The multiple bit state detection circuits are electrically connected to the multiple excitation signal baseband circuits and the multiple reflection signal baseband circuits in a one-to-one correspondence. The bit state detection circuit includes: The first frequency divider is electrically connected to the Nth excitation signal baseband circuit and is used to reduce the frequency of the Nth excitation baseband signal output by the Nth excitation signal baseband circuit. The second frequency divider is electrically connected to the Nth reflected signal baseband circuit and is used to reduce the frequency of the Nth reflected baseband signal output by the Nth reflected signal baseband circuit. A time-to-data converter, electrically connected to the first frequency divider and the second frequency divider respectively, is used to detect the phase difference between the Nth excitation baseband signal and the Nth reflection baseband signal; A state decision circuit, electrically connected to the time-data converter, is used to determine the second state of the corresponding quantum bit based on the phase difference.

5. The quantum bit interface circuit as described in claim 1, characterized in that, The bit state control circuit includes: An XY axis controller is configured to output an XY axis control signal to the quantum bit device according to the state control parameters. A Z-axis controller is configured to output a Z-axis control signal to the quantum bit device based on the state control parameters.

6. The quantum bit interface circuit as described in claim 1, characterized in that, The quantum bit interface circuit also includes a communication interface; The communication interface is electrically connected to the controller; the communication interface is used to receive the control command and output parameters to characterize the second state.

7. A quantum bit computing system, characterized in that, The quantum bit computing system includes a quantum bit device, a quantum computing equipment, and a quantum bit interface circuit as described in any one of claims 1 to 6; The qubit device includes multiple qubits. The quantum computing device outputs control commands based on preset state parameters of the multiple qubits. The control commands control the qubit interface circuit to output state control parameters and state readout parameters. The state control parameters control a first state of the multiple qubits in the qubit device. The state readout parameters detect a second state of the multiple qubits. The qubit interface circuit also outputs parameters characterizing the second state of the multiple qubits to the quantum computing device. The quantum computing device is further configured to determine that the corresponding qubit is in a normal state when the preset state parameter is consistent with the parameter corresponding to the second state; and to determine that the corresponding qubit is in an abnormal state when the preset state parameter is inconsistent with the parameter corresponding to the second state.

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