Array substrate and manufacturing method thereof, and display panel

Abstract

The present application relates to an array substrate, a method for manufacturing the same, and a display panel. The method comprises: sequentially depositing a patterned first metal layer, a gate insulating layer, and a first semiconductor layer on a base substrate; forming a sacrificial layer on the first semiconductor layer; depositing a second semiconductor layer on the sacrificial layer; forming a transparent second metal layer on the second semiconductor layer; coating the second metal layer with a photoresist layer, exposing and developing the photoresist layer to form a photoresist pattern; wet-etching the second metal layer using the photoresist pattern as a shield; dry-etching the film layer between the second semiconductor layer and the first semiconductor layer using the photoresist pattern as a shield to partially etch away the thickness of the first semiconductor layer; irradiating the sacrificial layer corresponding to the channel region with a laser to decompose the sacrificial layer; and stripping off the second semiconductor layer, the second metal layer, and the photoresist pattern corresponding to the channel region. The present application can simplify the yellow light process and reduce production costs.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] With the development of optoelectronic display technology and semiconductor manufacturing technology, liquid crystal display panels (TFT-LCD) or organic light emitting diode display panels (TFT-OLED) equipped with thin film transistors (TFT) have become the mainstream of display devices.

[0003] To reduce the number of photomask processes, array substrates for display panels are typically manufactured using a four-pass process. This involves simultaneously fabricating the semiconductor layer and the metal layer containing the source, drain, and data lines, thereby reducing costs, shortening process time, and increasing production capacity. However, in the existing four-pass process, the second metal layer M2, which serves as the TFT source and drain layers, requires two dry and two wet etching passes using a halftone mask (HTM). This process, generally referred to in the industry as a 2W2D process, requires the simultaneous formation of the M2 and semiconductor layer patterns, thereby eliminating the semiconductor layer photomask process. The HTM is more expensive than conventional photomasks, and the 2W2D process is also more complex. Summary of the Invention

[0004] The present application aims to provide a method for preparing an array substrate, an array substrate and a display panel, which can eliminate the need for a semi-transparent mask plate and can prepare the array substrate through four yellow light processes using only one wet etching and one dry etching, thereby reducing production costs.

[0005] In a first aspect, an embodiment of the present application proposes a method for preparing an array substrate, comprising: forming a patterned first metal layer on a base substrate, the first metal layer including a gate; depositing a gate insulating layer on the first metal layer; depositing a first semiconductor layer on the gate insulating layer; forming a sacrificial layer on the first semiconductor layer; depositing a second semiconductor layer on the sacrificial layer; forming a patterned and transparent second metal layer on the second semiconductor layer; coating a photoresist layer on the second metal layer, exposing and developing the photoresist layer to form a photoresist pattern; wet etching the second metal layer using the photoresist pattern as a shield to form a source electrode, The drain electrode and the channel region between the source electrode and the drain electrode are provided with gaps respectively; the film layer between the second semiconductor layer and the first semiconductor layer is dry-etched with the photoresist pattern as a shield, so as to cleanly etch the film layer outside the channel region that is not shielded by the photoresist pattern and the second metal layer, and partially etch away the thickness of the first semiconductor layer corresponding to the gap; the sacrificial layer corresponding to the channel region is irradiated with a laser so that the laser is reflected by the gate and focused on the sacrificial layer, so as to decompose the sacrificial layer above the channel region corresponding to the gate; and the second semiconductor layer, the second metal layer and the photoresist pattern corresponding to the channel region are peeled off.

[0006] In a possible implementation, the material of the sacrificial layer includes heavily doped semiconductor or conductive polyimide.

[0007] In a possible implementation, the thickness of the first semiconductor layer is 100 μm-1000 μm.

[0008] In a possible implementation, the gap between the source and the channel region and the gap between the channel region and the drain is less than 1 μm.

[0009] In a possible implementation, the wet etching acid solution is any one of oxalic acid, sulfuric acid, and hydrochloric acid.

[0010] In a possible implementation, the etching gas used in the dry etching is at least one of sulfur hexafluoride, chlorine, oxygen, and nitrogen trifluoride.

[0011] In a possible implementation, after depositing the second semiconductor layer on the sacrificial layer and before forming the patterned second metal layer on the second semiconductor layer, the preparation method further includes: depositing a heavily doped semiconductor layer on the second semiconductor layer.

[0012] In one possible embodiment, after stripping off the second semiconductor layer, the second metal layer and the photoresist pattern corresponding to the channel region, the preparation method further includes: depositing a passivation layer on the second metal layer; depositing a conductive film on the passivation layer, and forming a pixel electrode through dry etching the conductive film.

[0013] In a second aspect, an embodiment of the present application further proposes an array substrate, which is prepared using the aforementioned method for preparing the array substrate.

[0014] In a third aspect, an embodiment of the present application further proposes a display panel, comprising: the array substrate as described above; an opposing substrate disposed opposite to the array substrate; and a liquid crystal layer disposed between the array substrate and the opposing substrate.

[0015] The array substrate, preparation method thereof, and display panel provided in embodiments of the present application are characterized by disposing a sacrificial layer between a first semiconductor layer and a second semiconductor layer, forming a patterned and transparent second metal layer on the second semiconductor layer, coating a photoresist layer on the second metal layer, exposing and developing the photoresist layer to form a photoresist pattern, and performing a wet etching of the second metal layer using the photoresist pattern as a barrier, and performing a dry etching of the film layer between the second semiconductor layer and the first semiconductor layer. Laser light is then irradiated onto the sacrificial layer, causing the laser light to be reflected by a gate and focused on the sacrificial layer, thereby decomposing the sacrificial layer above the channel region corresponding to the gate, and stripping off the second semiconductor layer, the second metal layer, and the photoresist pattern corresponding to the channel region, thereby completing the preparation of the second metal layer and the semiconductor layer. Compared with the related art process using a halftone mask and two dry etching and two wet etching (2W2D), the present application can omit the halftone mask and only use one dry etching and one wet etching (1W1D). The array substrate can be prepared using a four-pass yellow light process, thereby reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The features, advantages, and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, identical components are denoted by the same reference numerals. The drawings are not drawn to scale and are intended only to illustrate relative positions. Layer thicknesses in certain locations are exaggerated for ease of understanding, and the layer thicknesses depicted in the drawings do not necessarily represent actual layer thickness proportions.

[0017] Figure 1 A flowchart illustrating a method for preparing an array substrate according to an embodiment of the present application is shown;

[0018] Figure 2 (a) to (e) show Figure 2 Schematic diagram of the preparation process of the array substrate shown;

[0019] Figure 3 A schematic structural diagram of a display panel provided in an embodiment of the present application is shown.

[0020] Description of reference numerals:

[0021] 10. Base substrate; 11. First metal layer; 12. Gate insulating layer; 13. First semiconductor layer; 14. Sacrificial layer; 15. Second semiconductor layer; 16. Second metal layer; PR, photoresist layer; G, gate; S, source; D, drain; 17, heavily doped semiconductor layer; 18, passivation layer; 19, pixel electrode;

[0022] 100 , array substrate; 200 , counter substrate; 300 , liquid crystal layer. DETAILED DESCRIPTION

[0023] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are set forth in order to provide a comprehensive understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be implemented without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the well-known structures and techniques are not shown in order to avoid unnecessary ambiguity in the present application; and, for clarity, the sizes of regional structures may be exaggerated. In addition, the features, structures, or characteristics described below may be combined in any suitable manner in one or more embodiments.

[0024] like Figures 1 to 2 As shown, an embodiment of the present application provides a method for manufacturing an array substrate. The array substrate includes sequentially forming a first metal layer 11, a gate insulating layer 12, a first semiconductor layer 13, a sacrificial layer 14, a second semiconductor layer 15, and a second metal layer 16 on a base substrate 10. The method for manufacturing the array substrate provided in the embodiment of the present application includes the following steps S1 to S11. The specific preparation process of each step is described in detail below.

[0025] Step S1: forming a patterned first metal layer 11 on a base substrate 10 , wherein the first metal layer 11 includes a gate G.

[0026] The first metal layer 11 can be a metal material or alloy material such as Cu, Mo, Ti, Al, Cr, Mg, Ag, Au, etc. The first metal layer 11 can be formed on the base substrate 10 by a physical vapor deposition (PVD) method or an evaporation method, and a gate G and a scan line (not shown in the figure) can be formed by a patterning process. In one example, the first metal layer 11 is made of Cu with a thickness of 300 nm, is formed by a magnetron sputtering method, and is patterned by wet etching (copper acid).

[0027] Step S2 : forming a gate insulating layer 12 by deposition on the first metal layer 11 .

[0028] The gate insulating layer 12 may be a stacked structure of one or more insulating dielectric materials such as SiOx, SiNx, HfO2, and Al2O3. The gate insulating layer 12 may be formed by chemical vapor deposition (CVD). In one example, the gate insulating layer 12 is a stacked structure of SiNx and SiOx, with the SiNx having a thickness of 100 nm and the SiOx having a thickness of 300 nm, and is formed by plasma-enhanced chemical vapor deposition (PECVD).

[0029] Step S3 : forming a first semiconductor layer 13 by deposition on the gate insulating layer 12 .

[0030] The material of the first semiconductor layer 13 can be an organic semiconductor material, an oxide semiconductor material, or even amorphous silicon (A-Si). When forming the channel region, the corresponding semiconductor layer can be etched or not, depending on the material of the semiconductor layer. Optionally, the thickness of the first semiconductor layer 13 is 100 μm to 1000 μm. This thickness is required for the subsequent preparation of the channel F of the semiconductor layer.

[0031] Step S4: Forming a sacrificial layer 14 on the first semiconductor layer 13. The sacrificial layer 14 may be made of heavily doped GaN or conductive polyimide (PI). The sacrificial layer 14 may be formed by evaporation, CVD, or other methods. The thickness of the sacrificial layer 14 may be 1 μm to 500 μm, and the sacrificial layer 14 may be decomposed by laser.

[0032] Step S5 : depositing a second semiconductor layer 15 on the sacrificial layer 14 .

[0033] The material of the second semiconductor layer 15 can be an organic semiconductor material, an oxide semiconductor material, or even amorphous silicon (A-Si). When forming the channel region, the corresponding semiconductor layer can be etched or not depending on the material of the semiconductor layer. The sum of the thicknesses of the first semiconductor layer 13 and the second semiconductor layer 15 is the thickness of the semiconductor layer in the existing process.

[0034] Step S6 : forming a transparent second metal layer 16 on the second semiconductor layer 15 .

[0035] In this embodiment, the second metal layer 16 can be one or more transparent metal oxide conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), indium gallium zinc oxide (IGZO), and zinc tin oxide (ZTO), and is formed through a single patterning process. The second metal layer 16 is a transparent layer, allowing the laser to penetrate the second metal layer 14 to illuminate the sacrificial layer 14 and decompose the sacrificial layer 14 at a specific location.

[0036] Step S7: coating a photoresist layer on the second metal layer 16, exposing and developing the photoresist layer to form a photoresist pattern.

[0037] Optionally, the photoresist layer PR is a layered photoresist. Photoresist is an organic compound and is classified into positive and negative photoresists based on the relationship between the crosslinking reaction within the photoresist and ultraviolet light. In positive photoresists, the photoresist undergoes a crosslinking and decomposition reaction in areas exposed to ultraviolet light, making these areas soluble in the developer. In negative photoresists, the photoresist undergoes a crosslinking and decomposition reaction in areas exposed to ultraviolet light, making these areas difficult to dissolve in the developer. In this embodiment, the photoresist layer PR is a positive photoresist.

[0038] Step S8: Wet-etching the second metal layer 16 using the photoresist pattern as a mask to form a source electrode, a drain electrode, and a channel region between the source electrode and the drain electrode, with gaps formed between the source electrode, the channel region, and the drain electrode. Optionally, the wet etching acid is any one of oxalic acid, sulfuric acid, and hydrochloric acid.

[0039] Step S9: Dry-etch the film layer between the second semiconductor layer 15 and the first semiconductor layer 13 using the photoresist pattern as a shield, so as to completely etch the film layer outside the channel area that is not blocked by the photoresist pattern and the second metal layer, and etch away part of the thickness of the first semiconductor layer 13 corresponding to the gap.

[0040] Optionally, the etching gas used in the dry etching is at least one of sulfur hexafluoride, chlorine, oxygen, and nitrogen trifluoride. Optionally, the gap between the source and the channel region and between the channel region and the drain is less than 1 μm.

[0041] After wet etching, the second metal layer and photoresist remain in the source and drain parts and the channel area, and a very small gap is left directly between the source and drain and the channel area. Then dry etching is performed again to completely etch away the second semiconductor layer 15 and other parts outside the channel that are not blocked by the photoresist and the second metal layer 16. The gap between the channel area and the source and drain is very small, and the amount of dry etching gas entering will be smaller than that of other positions. The dry etching rate at this position is slower, so that when the second semiconductor layer 15 and the first semiconductor layer 13 outside the channel area are completely etched away, after the sacrificial layer 14 is etched away at the channel area position, a certain thickness of the first semiconductor layer 13 is still left. Therefore, the channel F can be prepared by controlling the gap size and adjusting the dry etching gas flow rate and power.

[0042] Step S10 : using laser to irradiate the sacrificial layer 14 corresponding to the channel region, so that the laser is reflected by the gate G and focused on the sacrificial layer 14 , thereby decomposing the sacrificial layer 14 above the channel region corresponding to the gate G.

[0043] Step S11 : stripping off the second semiconductor layer 15 , the second metal layer 16 and the photoresist pattern corresponding to the channel region.

[0044] Laser is used to irradiate from the light-emitting side, and the laser focus is set to be focused on the sacrificial layer 14 after being reflected by the gate G of the first metal layer 11. At the same time, the laser energy is controlled so that only the sacrificial layer 14 in the channel area corresponding to the gate G is decomposed, and the rest of the layer will not be decomposed. In this way, the sacrificial layer 14, the second semiconductor layer 15, the second metal layer 16 and the photoresist in the channel area can be removed, and then the photoresist is removed, so that the patterning of the second metal layer 16 and the semiconductor layer can be completed by one dry etching and one wet etching (1W1D) without the need for a half-tone mask.

[0045] The method for preparing an array substrate provided in an embodiment of the present application comprises the following steps: providing a sacrificial layer 14 between a first semiconductor layer 13 and a second semiconductor layer 15, forming a patterned and transparent second metal layer 16 on the second semiconductor layer 15, coating a photoresist layer PR on the second metal layer 16, exposing and developing the photoresist layer PR to form a photoresist pattern, performing a wet etching on the second metal layer 16 using the photoresist pattern as a shield, and performing a dry etching on the film layer between the second semiconductor layer 15 and the first semiconductor layer 13; then irradiating the sacrificial layer 14 with a laser, The laser is reflected by the gate G and focused on the sacrificial layer 14, so as to decompose the sacrificial layer 14 above the channel region corresponding to the gate G, and peel off the second semiconductor layer 15, the second metal layer 16 and the photoresist pattern corresponding to the channel region, thereby completing the preparation of the second metal layer 16 and the semiconductor layer. Compared with the process of using a half-tone mask and two dry etchings and two wet etchings (2W2D) in the related art, the present application can omit the half-tone mask and only use one dry etching and one wet etching (1W1D), and can prepare the array substrate through a four-step yellow light process, thereby reducing the production cost.

[0046] In some embodiments, the method for preparing the array substrate further includes:

[0047] After depositing the second semiconductor layer 15 on the sacrificial layer 14 and before forming the patterned second metal layer 16 on the second semiconductor layer 15, the method further includes:

[0048] Step S50 : forming a heavily doped semiconductor layer 17 by deposition on the second semiconductor layer 15 .

[0049] In this embodiment, a heavily doped semiconductor layer 17 is provided between the second semiconductor layer 15 and the second metal layer 16 to reduce resistance.

[0050] Furthermore, the method for preparing the array substrate provided in the embodiment of the present application further includes, after step S11, that is, after stripping off the second semiconductor layer 15, the second metal layer 16, and the photoresist pattern corresponding to the channel region:

[0051] Step S12: Depositing a passivation layer 18 on the second metal layer 16. Plasma-enhanced chemical vapor deposition (PECVD) is typically used to deposit the passivation layer 18. The passivation layer 18 is made of silicon nitride. In addition to covering the second metal layer 16, it also covers the gate insulating layer 12 and first semiconductor layer 13 exposed by dry etching. Using silicon nitride to form the passivation layer prevents water vapor, sodium ions, and oxygen impurities from invading the device. Of course, in this embodiment, the passivation layer 18 can also be made of other organic insulating materials, which is not a limitation here.

[0052] Step S13: depositing a conductive film on the passivation layer 18, and forming the pixel electrode 19 through dry etching of the conductive film.

[0053] A conductive film is deposited on the passivation layer 18 by magnetron sputtering or thermal evaporation. The conductive film can be made of indium tin oxide or indium zinc oxide. In this way, a pixel electrode is formed by dry etching, and the pixel electrode 19 can be electrically connected to the drain through the via hole of the passivation layer 18.

[0054] It should be noted that the composition process described in this application may include a photolithography process, or include a photolithography process and an etching step, and may also include other processes such as printing and inkjet for forming a predetermined pattern; wherein, the photolithography process refers to a process including film formation, exposure, development and other processes using photoresist, mask template, exposure machine and the like, and the corresponding composition process can be selected according to the structure formed in this application.

[0055] In addition, an embodiment of the present application further provides an array substrate, which is prepared using the aforementioned method for preparing the array substrate.

[0056] In addition, if Figure 3 As shown, an embodiment of the present application further provides a display panel comprising an array substrate 100, an opposing substrate 200 disposed opposite the array substrate 100, and a liquid crystal layer 300 disposed between the array substrate 100 and the opposing substrate 200. The array substrate 100 is manufactured using the array substrate manufacturing method described above. The liquid crystal layer 3 comprises a plurality of liquid crystal molecules, which are typically rod-shaped and can flow like a liquid while also possessing certain crystalline characteristics. When the liquid crystal molecules are exposed to an electric field, their arrangement direction changes according to changes in the electric field.

[0057] The array substrate 100 has transparent pixel electrodes 19 disposed on its base substrate 10, and a common electrode 202 disposed on its counter substrate 200. If a color resist layer is disposed on one side of the counter substrate 200, the counter substrate 200 can also be a color filter substrate. When the thin-film transistors of the array substrate 100 are turned on by a signal applied to the gate electrode G, the signal applied to the data line is applied to the pixel electrode 19. This generates an electric field of predetermined strength between the pixel electrode 19 and the common electrode 202. Applying different voltages can change the orientation of the liquid crystal molecules, thereby adjusting the light transmittance and displaying an image.

[0058] It can be understood that the technical solutions of the array substrate provided in each embodiment of the present application can be widely used in various liquid crystal display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, and MVA (Multi-Domain Vertical Alignment) display panel.

[0059] It should be readily understood that “on,” “above,” and “over” in this application should be interpreted in the broadest manner, such that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers therebetween, and “above” or “over” includes not only the meaning of “above” or “over,” but also includes the meaning of “above” or “over” with no intervening features or layers therebetween (i.e., directly on something).

[0060] As used herein, the term "layer" may refer to a portion of a material comprising an area having a certain thickness. A layer may extend over the entire underlying structure or overlying structure, or may have an extent smaller than the extent of the underlying or overlying structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure whose thickness is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pairs of lateral planes at the top and bottom surfaces. A layer may extend laterally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers located thereon, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and a contact layer (within which contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing an array substrate, characterized in that: include: forming a patterned first metal layer on a base substrate, wherein the first metal layer includes a gate; depositing a gate insulating layer on the first metal layer; depositing a first semiconductor layer on the gate insulating layer; forming a sacrificial layer on the first semiconductor layer; depositing a second semiconductor layer on the sacrificial layer; forming a transparent second metal layer on the second semiconductor layer; coating a photoresist layer on the second metal layer, and exposing and developing the photoresist layer to form a photoresist pattern; Wet-etching the second metal layer using the photoresist pattern as a shield to form a source electrode, a drain electrode, and a channel region between the source electrode and the drain electrode, with gaps formed between the source electrode, the channel region, and the drain electrode; Using the photoresist pattern as a shield, dry-etching the film layer between the second semiconductor layer and the first semiconductor layer is performed to completely etch the film layer outside the channel region that is not shielded by the photoresist pattern and the second metal layer, and to etch away a portion of the thickness of the first semiconductor layer corresponding to the gap; irradiating the sacrificial layer corresponding to the channel region with a laser, so that the laser is focused on the sacrificial layer after being reflected by the gate, thereby decomposing the sacrificial layer above the channel region corresponding to the gate; The second semiconductor layer, the second metal layer and the photoresist pattern corresponding to the channel region are stripped off.

2. The preparation method according to claim 1, characterized in that The material of the sacrificial layer includes heavily doped semiconductor or conductive polyimide.

3. The preparation method according to claim 1, characterized in that The thickness of the first semiconductor layer is 100 μm-1000 μm.

4. The preparation method according to claim 1, characterized in that The gaps between the source and the channel region and between the channel region and the drain are less than 1 μm.

5. The preparation method according to claim 1, characterized in that The wet etching acid solution is any one of oxalic acid, sulfuric acid and hydrochloric acid.

6. The preparation method according to claim 1, characterized in that The etching gas used in the dry etching is at least one of sulfur hexafluoride, chlorine, oxygen, and nitrogen trifluoride.

7. The preparation method according to claim 1, characterized in that After depositing a second semiconductor layer on the sacrificial layer and before forming a patterned second metal layer on the second semiconductor layer, the method further includes: A heavily doped semiconductor layer is deposited on the second semiconductor layer.

8. The preparation method according to claim 1, characterized in that After stripping off the second semiconductor layer, the second metal layer and the photoresist pattern corresponding to the channel region, the preparation method further includes: depositing a passivation layer on the second metal layer; A conductive film is deposited on the passivation layer, and the conductive film is formed into a pixel electrode by dry etching.

9. An array substrate, characterized in that: The array substrate is manufactured by the method for manufacturing the array substrate according to any one of claims 1 to 8.

10. A display panel, characterized in that: include: The array substrate according to claim 9; an opposing substrate, arranged opposite to the array substrate; as well as The liquid crystal layer is disposed between the array substrate and the opposing substrate.

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