Filter and method for preparing the same

Abstract

The embodiment of the present application relates to a filter and a preparation method thereof, the preparation method comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other; converting a portion of the material on the first surface side of the semiconductor substrate into a sacrificial layer material, and making the top surface of the sacrificial layer material coplanar with the first surface of the semiconductor substrate to form a sacrificial layer embedded in the semiconductor substrate; forming a piezoelectric stack structure on the first surface of the semiconductor substrate, the piezoelectric stack structure comprising a first electrode layer, a piezoelectric layer and a second electrode layer stacked in sequence, and the piezoelectric stack structure covering the sacrificial layer; removing the sacrificial layer to form a cavity below the piezoelectric stack structure. Thus, the sacrificial layer is prevented from having steps, causing the piezoelectric layer to undergo crystallization degradation at the steps, affecting the device performance; and, there is no need to etch the semiconductor substrate to pre-form a cavity and then fill the sacrificial layer, saving processes and avoiding the influence of the etching process on the mechanical strength of the semiconductor substrate.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a filter and a method for preparing the same. Background Art

[0002] With the rapid development of mobile communication technology, the performance requirements for filters in mobile communication devices are becoming increasingly higher. Among them, Bulk Acoustic Wave Filter (BAW) filters are widely used due to their advantages such as high Q value, low insertion loss, and integration. There are two main construction methods: air gap type and solid assembly type (Solidly Mounted Resonator, SMR). Among them, the air gap type BAW filter uses the silicon surface process in the micro-electromechanical system (MEMS) processing technology to form a cavity on the upper surface of the silicon wafer, which confines the sound wave in the piezoelectric stack structure.

[0003] At present, the preparation of the cavity is mainly through forming a sacrificial layer on the upper surface of the substrate to occupy the position of the cavity, then forming a piezoelectric stack structure covering the sacrificial layer, and then removing the sacrificial layer to form a cavity between the piezoelectric stack structure and the substrate. However, when the sacrificial layer is formed on the upper surface of the substrate, there is an obvious step at the edge of the sacrificial layer, which causes the crystallization degradation of the piezoelectric layer in the piezoelectric stack structure formed at the step, affecting the film quality of the piezoelectric layer at the edge of the sacrificial layer, resulting in the degradation of the resonance characteristics of the bulk acoustic wave at the edge, affecting the performance of the device.

[0004] Therefore, how to avoid crystal degradation of the piezoelectric layer is an urgent problem to be solved in this field. Summary of the invention

[0005] In view of this, the embodiments of the present application provide a filter and a method for manufacturing the same in order to solve at least one problem existing in the background technology.

[0006] In a first aspect, an embodiment of the present application provides a method for preparing a filter, the method comprising:

[0007] providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other;

[0008] Converting a portion of the material on the first surface side of the semiconductor substrate into a sacrificial layer material, and making the top surface of the sacrificial layer material coplanar with the first surface of the semiconductor substrate to form a sacrificial layer embedded in the semiconductor substrate;

[0009] forming a piezoelectric stacked structure on the first surface of the semiconductor substrate, the piezoelectric stacked structure comprising a first electrode layer, a piezoelectric layer, and a second electrode layer stacked in sequence, the piezoelectric stacked structure covering the sacrificial layer;

[0010] The sacrificial layer is removed to form a cavity below the piezoelectric stack structure.

[0011] In combination with the first aspect of the present application, in an optional embodiment, converting a portion of the material on the first surface side of the semiconductor substrate into a sacrificial layer material includes: performing an ion implantation process to form an ion implantation layer in the semiconductor substrate; performing an annealing process to activate the ion implantation layer to convert a portion of the material of the semiconductor substrate into the sacrificial layer material.

[0012] In combination with the first aspect of the present application, in an optional implementation manner, before performing the ion implantation process, the method further includes: forming a mask layer covering the first surface of the semiconductor substrate;

[0013] During the ion implantation process, ions penetrate the mask layer and are implanted into the semiconductor substrate;

[0014] After performing the annealing process, the method further includes: removing the mask layer.

[0015] In combination with the first aspect of the present application, in an optional implementation, during the ion implantation process, the implanted ions include oxygen ions; and the sacrificial layer is an oxide layer.

[0016] In combination with the first aspect of the present application, in an optional embodiment, converting a portion of the material on the first surface side of the semiconductor substrate into a sacrificial layer material includes: performing a local oxidation process to oxidize a portion of the material of the semiconductor substrate into a sacrificial layer material; performing a planarization process so that the top surface of the sacrificial layer material is coplanar with the first surface of the semiconductor substrate.

[0017] In combination with the first aspect of the present application, in an optional implementation manner, the depth of the sacrificial layer is less than or equal to 0.5 μm.

[0018] In conjunction with the first aspect of the present application, in an optional implementation, forming a piezoelectric stack structure on the first surface of the semiconductor substrate includes: forming the piezoelectric stack structure under certain pressure conditions so that the piezoelectric stack structure has a compressive stress;

[0019] After the sacrificial layer is removed, the portion of the piezoelectric stack structure corresponding to the sacrificial layer is arched in a dome shape in a direction away from the first surface under the action of compressive stress;

[0020] The cavity includes a lower half cavity below the first surface of the semiconductor substrate and an upper half cavity beyond the first surface of the semiconductor substrate, and the upper half cavity is dome-shaped.

[0021] In combination with the first aspect of the present application, in an optional implementation, the maximum height of the upper half cavity is in the range of 1.5 μm to 2 μm.

[0022] In a second aspect, an embodiment of the present application provides a filter, which is prepared using a filter preparation method as described in any one of the first aspects above.

[0023] In a third aspect, an embodiment of the present application provides a filter, including:

[0024] a semiconductor substrate including a first surface and a second surface opposite to each other;

[0025] A piezoelectric stack structure, the piezoelectric stack structure is located on the first surface of the semiconductor substrate, and the piezoelectric stack structure includes a first electrode layer, a piezoelectric layer, and a second electrode layer stacked in sequence;

[0026] A cavity is located between the semiconductor substrate and the piezoelectric stack structure, the cavity includes a lower half cavity lower than the first surface of the semiconductor substrate and an upper half cavity exceeding the first surface of the semiconductor substrate and protruding toward the piezoelectric stack structure; wherein the upper half cavity is defined by the lower surface of the piezoelectric stack structure, and the upper half cavity is dome-shaped.

[0027] In conjunction with the third aspect of the present application, in an optional embodiment, the stress on the portion of the piezoelectric stack structure that is used to define the upper half cavity is a compressive stress.

[0028] In conjunction with the third aspect of the present application, in an optional implementation manner, the depth of the lower half cavity is less than or equal to 0.5 μm.

[0029] In conjunction with the third aspect of the present application, in an optional implementation, the maximum height of the upper half cavity is in the range of 1.5 μm to 2 μm.

[0030] On the one hand, the filter and the preparation method thereof provided in the embodiments of the present application convert a portion of the material on the first surface side of the semiconductor substrate into a sacrificial layer material, and make the top surface of the sacrificial layer material coplanar with the first surface of the semiconductor substrate, thereby forming a sacrificial layer embedded in the semiconductor substrate, thereby avoiding the appearance of steps in the sacrificial layer, causing the piezoelectric layer to undergo crystalline degradation at the steps, thereby affecting the performance of the device; and, there is no need to etch the semiconductor substrate to pre-form a cavity and then fill the sacrificial layer, thereby saving process and avoiding the influence of the etching process on the mechanical strength of the semiconductor substrate. On the other hand, the filter provided in the embodiment of the present application includes: a semiconductor substrate, the semiconductor substrate includes a first surface and a second surface opposite to each other; a piezoelectric stack structure, the piezoelectric stack structure is located on the first surface of the semiconductor substrate, and the piezoelectric stack structure includes a first electrode layer, a piezoelectric layer, and a second electrode layer stacked in sequence; a cavity, the cavity is located between the semiconductor substrate and the piezoelectric stack structure, the cavity includes a lower half cavity lower than the first surface of the semiconductor substrate and an upper half cavity that exceeds the first surface of the semiconductor substrate and protrudes toward the piezoelectric stack structure; wherein the upper half cavity is defined by the lower surface of the piezoelectric stack structure, and the upper half cavity is dome-shaped, thereby not only avoiding crystallization degradation of the piezoelectric layer, but also the cavity size is large, which can meet the working requirements of the device.

[0031] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0033] Figure 1 A schematic diagram of a process for preparing a filter according to an embodiment of the present application;

[0034] Figures 2 to 9 A schematic diagram of the cross-sectional structure of the filter provided in an embodiment of the present application during the preparation process;

[0035] Figure 10 to Figure 11 A schematic diagram of the cross-sectional structure of a filter in the related art during the preparation process;

[0036] Fig.12 for Fig.11 A local enlarged structural schematic diagram of the filter shown;

[0037] Fig.13 for Figure 8 A schematic diagram of a local enlarged structure of the filter shown;

[0038] Fig.14 for Fig. 9 A locally enlarged structural schematic diagram of the filter shown. DETAILED DESCRIPTION

[0039] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0040] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0041] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0042] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0043] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0044] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0046] The present invention provides a method for preparing a filter. Figure 1 , the preparation method comprises:

[0047] S101: providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other;

[0048] S102: converting a portion of the material on the first surface side of the semiconductor substrate into a sacrificial layer material, and making the top surface of the sacrificial layer material coplanar with the first surface of the semiconductor substrate to form a sacrificial layer embedded in the semiconductor substrate;

[0049] S103: forming a piezoelectric stacked structure on the first surface of the semiconductor substrate, the piezoelectric stacked structure comprising a first electrode layer, a piezoelectric layer, and a second electrode layer stacked in sequence, the piezoelectric stacked structure covering the sacrificial layer;

[0050] S104: removing the sacrificial layer to form a cavity below the piezoelectric stack structure.

[0051] A sacrificial layer embedded in the semiconductor substrate is formed by converting a portion of the material on the first surface side of the semiconductor substrate into a sacrificial layer material, and making the top surface of the sacrificial layer material coplanar with the first surface of the semiconductor substrate, thereby avoiding the appearance of steps in the sacrificial layer, which would cause crystallization degradation of the piezoelectric layer at the steps and affect the performance of the device; and, there is no need to etch the substrate to form a cavity in advance and then fill the sacrificial layer, thus saving process and avoiding the influence of the etching process on the mechanical strength of the substrate.

[0052] Figures 2 to 9 The cross-sectional structure diagram of the filter provided in the embodiment of the present application during the preparation process. Figures 2 to 9 The preparation method of the filter provided in the embodiment of the present application is described in detail.

[0053] The filter in the embodiment of the present application is specifically a gap-type film bulk acoustic wave filter (Film Bulk Acoustic Resonator, FBAR).

[0054] In step S101, please refer to Figure 2 , a semiconductor substrate 100 is provided, and the semiconductor substrate 100 includes a first surface 101 and a second surface 102 opposite to each other.

[0055] The semiconductor substrate 100 provides a process platform for subsequent steps.

[0056] In this embodiment, the semiconductor substrate 100 can be any suitable semiconductor substrate, such as a bulk silicon substrate, and it can also be at least one of the following materials: SiGe, SiC, SiGeC, TnAs, GaAs, InP or other Group III and Group V compound semiconductors, including multilayer structures formed by these semiconductors, etc., or silicon on insulator (SOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP).

[0057] In step S102, please refer to Figure 3, a portion of the material on the first surface 101 side of the semiconductor substrate 100 is converted into a sacrificial layer material, and the top surface 121 of the sacrificial layer material is made coplanar with the first surface 102 of the semiconductor substrate 100, so as to form a sacrificial layer 120 embedded in the semiconductor substrate 100. In this way, the sacrificial layer 120 is prevented from having steps, so that the piezoelectric layer 420 is crystallized and degraded at the steps, which affects the performance of the device; and the semiconductor substrate 100 is prevented from being etched to form the cavity 130 in advance and then filled with the sacrificial layer 120, which saves the process and avoids the influence of the etching process on the mechanical strength of the semiconductor substrate 100.

[0058] Optionally, the depth of the sacrificial layer 120 is less than or equal to 0.5 μm. It is understandable that in subsequent steps, the sacrificial layer 120 can be removed by VHF or HF. If the depth of the sacrificial layer 120 is too large, the removal time is too long, and VHF or HF may damage the device, thereby affecting the performance of the device; and shortening the time for removing the sacrificial layer 120 is conducive to improving production efficiency.

[0059] As an optional specific implementation, please refer to Figure 5 , converting a portion of the material on the first surface 101 side of the semiconductor substrate 100 into a sacrificial layer material includes: performing an ion implantation process to form an ion implantation layer 111 in the semiconductor substrate 100; performing an annealing process to activate the ion implantation layer 111 to convert a portion of the material of the semiconductor substrate 100 into a sacrificial layer material. Thus, by converting a portion of the material of the semiconductor substrate 100 into a sacrificial layer material through the ion implantation process and the annealing process, steps in the sacrificial layer 120 are avoided, and the process of etching the semiconductor substrate 100 in advance to form the cavity 130 is omitted, thereby saving preparation steps and further improving production efficiency.

[0060] Optionally, in this embodiment, the depth of ion implantation is less than or equal to 0.1 μm, thereby reducing the thickness of the formed sacrificial layer 120, reducing the time for subsequent removal of the sacrificial layer 120, improving production efficiency, and avoiding excessively long time for removing the sacrificial layer 120, which may damage the device.

[0061] Optionally, refer to Figure 4 and Figure 5 Before performing the ion implantation process, the preparation method further includes: forming a first mask layer 201 covering the first surface 101 of the semiconductor substrate 100; during the ion implantation process, ions penetrate the first mask layer 201 and are implanted into the semiconductor substrate 100.

[0062] The first mask layer 201 is used to protect the first surface 101 of the semiconductor substrate 100, avoid damage to the first surface 101 of the semiconductor substrate 100 during the ion implantation process, and ensure the flatness of the first surface 101 of the semiconductor substrate 100, so that the piezoelectric stack structure 400 formed in subsequent steps can be formed on a flat horizontal plane.

[0063] Optionally, during the ion implantation process, the implanted ions include oxygen ions; and the sacrificial layer 120 is an oxide layer.

[0064] Furthermore, the concentration of oxygen ions is greater than or equal to 10 18 cm -2 .

[0065] Optionally, after performing the annealing process, the preparation method further comprises: removing the first mask layer 201. Thus, when performing the annealing process, the first mask layer 201 can serve as a protective layer for the first surface 101 of the semiconductor substrate 100 to prevent the annealing process from damaging the first surface 101 of the semiconductor substrate 100.

[0066] Optionally, the process of removing the first mask layer 201 includes a CMP (Chemical Mechanical Polishing) process. Removing the first mask layer 201 by the CMP process can prevent the first mask layer 201 from remaining on the first surface 101 of the semiconductor substrate 100, and repair the flatness of the first surface 101 of the semiconductor substrate 100, so as to avoid affecting the crystal morphology of the piezoelectric layer 420 formed in subsequent steps.

[0067] Please refer to Figures 3 to 5 Specifically, the step of forming the sacrificial layer 120 embedded in the semiconductor substrate 100 may include:

[0068] A first mask layer 201 is formed to cover the first surface 101 of the semiconductor substrate 100; a photoresist layer 300 is formed to cover the first mask layer 201; a first opening 310 is formed in the photoresist layer 300 through processes such as exposure and development; an ion implantation process is performed using the photoresist layer 300 having the first opening 310 as a mask, and oxygen ions are implanted into the semiconductor substrate 100 through the first opening 310 and the first mask layer 201, thereby forming an ion implantation layer 111 in the semiconductor substrate 100; an annealing process is performed to activate the ion implantation layer 111, so as to convert a portion of the material of the semiconductor substrate 100 into a sacrificial layer material, thereby forming a sacrificial layer 120; and the first mask layer 201 is removed.

[0069] As another optional specific implementation, please refer to Figure 3 and Figure 7, converting a portion of the material on the first surface 101 side of the semiconductor substrate 100 into a sacrificial layer material includes: performing a local oxidation process to oxidize a portion of the material of the semiconductor substrate 100 into a sacrificial layer material; performing a planarization process to make the top surface 121 of the sacrificial layer material coplanar with the first surface of the semiconductor substrate 100. Thus, the process of etching the cavity 130 in the semiconductor substrate 100 in advance is avoided, the process flow is simplified, and the production efficiency is further improved; through the planarization process, the top surface 121 of the sacrificial layer material is coplanar with the first surface 101 of the semiconductor substrate 100, so that the piezoelectric stack structure 400 formed in the subsequent steps can be formed on a flat horizontal surface.

[0070] Please refer to Figure 3 , Figure 6 and Figure 7 Specifically, the step of forming the sacrificial layer 120 embedded in the semiconductor substrate 100 may include:

[0071] A second mask layer 202 is formed to cover the first surface 101 of the semiconductor substrate 100; a photoresist layer 300 is formed to cover the second mask layer 202; a first opening 310 is formed in the photoresist layer 300 through processes such as exposure and development; the second mask layer 202 is etched using the photoresist layer 300 having the first opening 310 as a mask to form the second opening 210; the photoresist layer 300 is removed; a local oxidation process is performed to oxidize a portion of the material of the semiconductor substrate 100 into a sacrificial layer material; a planarization process is performed to make the top surface 121 of the sacrificial layer material coplanar with the first surface 101 of the semiconductor substrate 100, thereby forming a sacrificial layer 120. Thus, although the sacrificial layer material protrudes from the first surface 101 of the semiconductor substrate 100 after the local oxidation process, the top surface 121 of the sacrificial layer material is finally made coplanar with the first surface 101 of the semiconductor substrate 100 by performing the planarization process.

[0072] Optionally, the planarization process includes a CMP process.

[0073] Optionally, after performing the local oxidation process, the preparation method further includes: removing the second mask layer 202 .

[0074] Optionally, the process of removing the second mask layer 202 includes a CMP process.

[0075] Understandably, please refer to Figure 7In actual preparation, after performing the local oxidation process, a portion of the material of the semiconductor substrate 100 is oxidized into a sacrificial layer material, which includes a portion 113 below the first surface of the semiconductor substrate and a portion 112 above the first surface of the semiconductor substrate. While removing the second mask layer 202 through the CMP process, the portion 112 of the sacrificial layer material above the first surface of the semiconductor substrate can be removed, so that the top surface 121 of the sacrificial layer material is coplanar with the first surface 101 of the semiconductor substrate 100, which saves processes and improves production efficiency.

[0076] In step S103, please refer to Figure 8 A piezoelectric stack structure 400 is formed on the first surface 101 of the semiconductor substrate 100 . The piezoelectric stack structure 400 includes a first electrode layer 410 , a piezoelectric layer 420 , and a second electrode layer 430 stacked in sequence. The piezoelectric stack structure 400 covers the sacrificial layer 120 .

[0077] The piezoelectric stack structure 400 is used to realize the mutual conversion between the electrical signal and the acoustic signal, so that the filter can perform filter processing on the signal.

[0078] The material of the first electrode layer 410 may be a conductive material or a semiconductor material. The conductive material may be a metal material having conductive properties, such as one or more of molybdenum (Mo), ruthenium (Ru), tungsten (Wu), titanium (Ti), aluminum (Al), gold (Au) and platinum (Pt); the semiconductor material may be Si, Ge, SiGe, SiC or SiGeC, etc.

[0079] The material of the piezoelectric layer 420 includes polycrystalline piezoelectric materials with a columnar crystal structure such as polycrystalline aluminum nitride or polycrystalline zinc oxide. In this embodiment, the material of the piezoelectric layer 420 is specifically polycrystalline aluminum nitride as an example.

[0080] The material of the second electrode layer 430 can be the same as that of the first electrode layer 410 , which will not be described in detail herein. Of course, the present application does not exclude the case where the second electrode layer 430 is made of a material different from that of the first electrode layer 410 .

[0081] Understandably, please refer to Fig.10 and Fig.11 In the related art, the top surface of the sacrificial layer 120 is higher than the first surface 101 of the semiconductor substrate 100, and a step appears on the sacrificial layer 120. The piezoelectric stack structure 400 is not formed on a flat horizontal surface. Therefore, the first electrode layer 410 has a conical shape at the step (e.g. Fig.10 As shown in the dashed box 412, the piezoelectric layer 420 undergoes crystal degradation at the step of the sacrificial layer 120. Fig.12The polycrystalline aluminum nitride has a columnar crystal structure, and the columnar crystals are perpendicular to the first surface 101 of the semiconductor substrate 100 and the top surface 411 of the first electrode layer 410, and are also perpendicular to the tapered portion of the first electrode layer 410 at the step (such as Fig.12 Therefore, the direction of the columnar crystals at the step of the piezoelectric layer 420 is inconsistent with the direction of the columnar crystals in other parts (as shown in the dashed box 412 in the middle). Fig.12 As shown in the dashed box 421, the piezoelectric layer 420 undergoes crystal degradation at the step.

[0082] Please refer to Figure 8 In this embodiment, the top surface 121 of the sacrificial layer material is coplanar with the first surface 101 of the semiconductor substrate 100, the sacrificial layer 120 has no steps, and the piezoelectric stack structure 400 is formed on a flat horizontal surface. Fig.13 and Fig.14 , the directions of the multiple columnar crystal structures in the polycrystalline aluminum nitride are consistent, and the piezoelectric layer 420 does not experience crystal degradation.

[0083] In actual process, the first electrode material layer may be formed first, and then the required first electrode layer 410 may be formed by patterning. Similarly, the piezoelectric layer 420 and the second electrode layer 430 may be formed by first forming the piezoelectric material layer and the second electrode material layer, and then patterning.

[0084] Optionally, refer to Figure 8 The piezoelectric layer 420 includes a first portion 422 covering the top surface 411 of the first electrode layer 410 and a second portion 423 covering the sidewall 413 of the first electrode layer 410, and the sidewall 413 of the first electrode layer 410 is sloped. Thus, the first electrode layer 410 is prevented from having steps, so that the piezoelectric layer 420 is crystallized and degraded at the steps of the first electrode layer 410, thereby affecting the performance of the device.

[0085] Furthermore, the angle of the slope is less than or equal to 12 degrees. Thus, the first electrode layer 410 can be better prevented from having steps, which is beneficial to ensuring the performance of the device.

[0086] Optionally, refer to Fig. 9, forming a piezoelectric stack structure 400 on the first surface 101 of the semiconductor substrate 100, including: forming the piezoelectric stack structure 400 under certain pressure conditions so that the piezoelectric stack structure 400 has compressive stress; after removing the sacrificial layer 120, a portion 440 of the piezoelectric stack structure corresponding to the sacrificial layer arches in a dome shape in a direction away from the first surface 101 under the action of the compressive stress; the cavity 130 includes a lower half cavity 131 below the first surface 101 of the semiconductor substrate 100 and an upper half cavity 132 beyond the first surface 101 of the semiconductor substrate 100, and the upper half cavity 132 is dome-shaped. Thus, the piezoelectric stack structure 400 is arched upward by compressive stress, so that the depth of the cavity 130 formed between the piezoelectric stack structure 400 and the semiconductor substrate 100 meets the requirement of the depth of the cavity 130 when the FBAR works normally; and, there is no need to form the cavity 130 that meets the requirement by performing an etching process on the semiconductor substrate 100, so that the degradation of the mechanical strength of the semiconductor substrate 100 can be avoided.

[0087] It can be understood that before the sacrificial layer 120 is removed, the portion 440 of the piezoelectric stack structure corresponding to the sacrificial layer is connected to the sacrificial layer 120, and the compressive stress in the piezoelectric stack structure 400 is difficult to exert its effect; after the sacrificial layer 120 is removed, a lower half cavity 131 is formed in the semiconductor substrate 100, and the portion 440 of the piezoelectric stack structure corresponding to the sacrificial layer loses the restraint of the sacrificial layer 120, and under the action of the compressive stress, it arches in a dome shape in a direction away from the first surface 101, thereby forming an upper half cavity 132 with a dome shape.

[0088] Optionally, the piezoelectric stack structure 400 is formed under certain pressure conditions, including: performing a sputtering process at a pressure of 0.6 Pa to 1.2 Pa to form the first electrode layer 410; performing a sputtering process at a pressure of approximately 0.3 Pa to form the piezoelectric layer 420; performing a sputtering process at a pressure of 0.6 Pa to 1.2 Pa to form the second electrode layer 430. Thus, the piezoelectric stack structure 400 has a compressive stress of -300 MPa.

[0089] Optionally, when the piezoelectric stack structure 400 is formed under a certain pressure condition, the method further includes: forming the piezoelectric stack structure 400 in an environment of protective gas, thereby protecting the stability and reliability of the formed piezoelectric stack structure 400.

[0090] Optionally, the protective gas includes Ar gas or Ar / N2 mixed gas. It can be understood that the formation of the electrode layer usually requires a stable and pure gas environment to avoid the influence of impurities on the performance of the electrode layer. Ar gas is an inert gas with stable chemical properties. It will not react with the sputtering material and can provide a more ideal sputtering environment. The formation of the piezoelectric layer 420 needs to consider the crystal structure and phase change of the material. The Ar / N2 mixed gas contains N2, which can help adjust the atmosphere composition and promote the growth of the piezoelectric layer 420.

[0091] Specifically, the steps of forming the piezoelectric stack structure 400 are as follows: in an Ar gas environment, sputtering Ru at a pressure of 0.6Pa to 1.2Pa to form a first electrode layer 410; in an Ar / N2 mixed gas environment, sputtering AlN at a pressure of approximately 0.3Pa to form a piezoelectric layer 420 on the first electrode layer 410; in an Ar environment, sputtering Ru at a pressure of 0.6Pa to 1.2Pa to form a second electrode layer 430.

[0092] After forming the piezoelectric stack structure 400, the preparation method further includes: forming a release hole (not shown in the figure), the release hole penetrates the piezoelectric stack structure 400 and exposes a portion of the sacrificial layer 120. Thus, it is convenient to remove the sacrificial layer 120 through the release hole in the subsequent steps.

[0093] It can be understood that in actual preparation, any suitable method known to those skilled in the art can be used to prepare the release holes.

[0094] In step S104, please refer to Fig. 9 , the sacrificial layer 120 is removed to form a cavity 130 located below the piezoelectric stack structure 400.

[0095] Optionally, the process of removing the sacrificial layer 120 includes a dry etching process or a wet etching process.

[0096] Furthermore, the chemical reaction gas in the dry etching process may include VHF; and the etching solution in the wet etching process may include HF solution or BOE solution.

[0097] In the optional embodiment in which the piezoelectric stack structure 400 has compressive stress, after removing the sacrificial layer 120, the portion 440 of the piezoelectric stack structure corresponding to the sacrificial layer is arched in a dome shape in a direction away from the first surface 101 under the action of the compressive stress; the cavity 130 includes a lower half cavity 131 below the first surface 101 of the semiconductor substrate 100 and an upper half cavity 132 beyond the first surface 101 of the semiconductor substrate 100, and the upper half cavity 132 is dome-shaped. As a result, the thickness of the cavity 130 formed between the piezoelectric stack structure 400 and the semiconductor substrate 100 meets the depth requirement of the cavity 130 when the FBAR works normally; and, there is no need to form the cavity 130 that meets the requirement by etching on the semiconductor substrate 100, so that the mechanical strength degradation of the semiconductor substrate 100 can be avoided.

[0098] Optionally, the maximum height of the upper cavity 132 is in the range of 1.5 μm to 2 μm. It can be understood that the maximum height of the upper cavity 132 is the distance between the arc vertex of the dome-shaped upper cavity 132 and the first surface 101 (eg, Fig. 9 The distance between the hollow cavity 130 (shown by the dotted line) Fig. 9 As shown in h2 in the figure, the upper cavity 132 satisfies the depth requirement of the cavity 130 when the FBAR works normally.

[0099] The embodiment of the present application also provides a filter, which is prepared using the filter preparation method in the above embodiment.

[0100] The present application also provides a filter, please refer to Fig. 9 , the filters include:

[0101] A semiconductor substrate 100, the semiconductor substrate 100 includes a first surface 101 and a second surface 102 opposite to each other;

[0102] A piezoelectric stack structure 400, the piezoelectric stack structure 400 is located on the first surface 101 of the semiconductor substrate 100, and the piezoelectric stack structure 400 includes a first electrode layer 410, a piezoelectric layer 420, and a second electrode layer 430 stacked in sequence;

[0103] The cavity 130 is located between the semiconductor substrate 100 and the piezoelectric stack structure 400. The cavity 130 includes a lower half cavity 131 that is lower than the first surface 101 of the semiconductor substrate 100 and an upper half cavity 132 that exceeds the first surface 101 of the semiconductor substrate 100 and protrudes toward the piezoelectric stack structure 400; wherein the upper half cavity 132 is defined by the lower surface 401 of the piezoelectric stack structure 400, and the upper half cavity 132 is dome-shaped.

[0104] It can be understood that in this embodiment, by making the piezoelectric stack structure 400 dome-shaped, a dome-shaped upper cavity 132 is formed between the semiconductor substrate 100 and the piezoelectric stack structure 400. The piezoelectric layer 420 in the piezoelectric stack structure 400 has good crystallinity, avoiding crystal degradation.

[0105] The material of the piezoelectric layer 420 includes polycrystalline piezoelectric materials with a columnar crystal structure such as polycrystalline aluminum nitride or polycrystalline zinc oxide. In this embodiment, the material of the piezoelectric layer 420 is specifically polycrystalline aluminum nitride as an example.

[0106] Optionally, the stress on the portion 440 of the piezoelectric stack structure used to define the upper half cavity is a compressive stress. Through the compressive stress, the portion 440 of the piezoelectric stack structure corresponding to the lower half cavity is arched away from the semiconductor substrate 100 to form the upper half cavity 132. It can be understood that in this embodiment, the portion 440 of the piezoelectric stack structure used to define the upper half cavity is the portion of the piezoelectric stack structure corresponding to the lower half cavity. In the actual preparation process, the position of the lower half cavity 131 is occupied by the sacrificial layer. Before the sacrificial layer is removed, the portion of the piezoelectric stack structure corresponding to the lower half cavity is the portion of the piezoelectric stack structure corresponding to the sacrificial layer.

[0107] Please refer to Figures 10 to 13 In the related art, the portion 112 of the sacrificial layer that exceeds the first surface of the semiconductor substrate occupies the position of the upper half cavity 132. After removing the sacrificial layer 120, the upper half cavity 132 that exceeds the first surface 101 of the semiconductor substrate 100 and protrudes toward the piezoelectric stack structure 400 is formed. Fig.12 As shown, polycrystalline aluminum nitride has a columnar crystal structure, and the columnar crystals are perpendicular to the first surface 101 of the semiconductor substrate 100 and the top surface 411 of the first electrode layer 410, and are also perpendicular to the top surface of the tapered portion of the first electrode layer 410 at the step (as shown in the dotted frame 412 in the figure), so the direction of the columnar crystals of the piezoelectric layer 420 at the step is inconsistent with the direction of the columnar crystals of other parts (as shown in the dotted frame 421 in the figure). Therefore, the piezoelectric layer 420 undergoes crystal degradation at the step.

[0108] It is understandable that in the related art, due to the crystal degradation of the piezoelectric layer 420 at the step, when the piezoelectric stack structure 400 arches away from the semiconductor substrate 100 due to compressive stress to form the upper half cavity 132, the compressive stress can cause the film to rupture, easily forming ripples in the filter band.

[0109] Please refer to Fig.13In this embodiment, the directions of the multiple columnar crystal structures in the polycrystalline aluminum nitride are consistent, and the piezoelectric layer 420 does not suffer from crystal degradation. Therefore, the film rupture can be avoided, and the in-band ripple of the filter can be effectively eliminated.

[0110] Optionally, the depth of the lower half cavity 131 (eg Fig. 9 h1 in the figure) is less than or equal to 0.5 μm. It can be understood that in actual preparation, the sacrificial layer is removed by VHF or HF to form the lower half cavity 131. If the depth of the lower half cavity 131 to be formed is too large, that is, the thickness of the sacrificial layer is too large, so that the removal time is too long, VHF or HF may cause damage to the device, thereby affecting the performance of the device; and shortening the time for removing the sacrificial layer is conducive to improving production efficiency.

[0111] Optionally, the maximum height of the upper cavity 132 is in the range of 1.5 μm to 2 μm. It can be understood that the maximum height of the upper cavity 132 is the distance between the arc vertex of the dome-shaped upper cavity 132 and the first surface 101 (eg, Fig. 9 The distance between the hollow cavity 130 (shown by the dotted line) Fig. 9 As shown in h2 in the figure, the depth of the upper cavity 132 satisfies the requirement on the depth of the cavity 130 when the FBAR works normally.

[0112] Optionally, refer to Fig. 9 The piezoelectric layer 420 includes a first portion 422 covering the top surface 411 of the first electrode layer 410 and a second portion 423 covering the sidewall 413 of the first electrode layer 410, and the sidewall 413 of the first electrode layer 410 is sloped. Thus, the first electrode layer 410 is prevented from having steps, so that the piezoelectric layer 420 is crystallized and degraded at the steps of the first electrode layer 410, thereby affecting the performance of the device.

[0113] Furthermore, the angle of the slope is less than or equal to 12 degrees. Thus, the first electrode layer 410 can be better prevented from having steps, which is beneficial to ensuring the performance of the device.

[0114] It should be noted that the filter embodiments provided in this application and the filter preparation method embodiments belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the combination of the various technical features of the filter provided in the embodiments of this application can already solve the technical problem to be solved by this application; therefore, the filter provided in the embodiments of this application may not be limited by the filter preparation method provided in the embodiments of this application, and any filter prepared by the preparation method that can form the filter structure provided in the embodiments of this application is within the scope of protection of this application.

[0115] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A method for preparing a filter, characterized in that: The preparation method comprises: providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other; Converting a portion of the material on the first surface side of the semiconductor substrate into a sacrificial layer material, and making the top surface of the sacrificial layer material coplanar with the first surface of the semiconductor substrate to form a sacrificial layer embedded in the semiconductor substrate; forming a piezoelectric stack structure on the first surface of the semiconductor substrate, the piezoelectric stack structure comprising a first electrode layer, a piezoelectric layer, and a second electrode layer stacked in sequence, the piezoelectric stack structure covering the sacrificial layer, the piezoelectric stack structure being formed on a flat surface provided by the sacrificial layer and the semiconductor substrate, and the material of the piezoelectric layer comprising a polycrystalline piezoelectric material having a columnar crystal structure; The sacrificial layer is removed to form a cavity below the piezoelectric stack structure.

2. The method for preparing a filter according to claim 1, characterized in that: The converting of a portion of the material on the first surface side of the semiconductor substrate into a sacrificial layer material comprises: performing an ion implantation process to form an ion implantation layer in the semiconductor substrate; and performing an annealing process to activate the ion implantation layer to convert a portion of the material of the semiconductor substrate into the sacrificial layer material.

3. The method for preparing a filter according to claim 2, characterized in that: Before performing the ion implantation process, the method further includes: forming a mask layer covering the first surface of the semiconductor substrate; During the ion implantation process, ions penetrate the mask layer and are implanted into the semiconductor substrate; After performing the annealing process, the method further includes: removing the mask layer.

4. The method for preparing a filter according to claim 2 or 3, characterized in that: During the ion implantation process, the implanted ions include oxygen ions; and the sacrificial layer is an oxide layer.

5. The method for preparing a filter according to claim 1, characterized in that: Converting a portion of the material on the first surface side of the semiconductor substrate into a sacrificial layer material comprises: performing a local oxidation process to oxidize a portion of the material of the semiconductor substrate into a sacrificial layer material; performing a planarization process to make the top surface of the sacrificial layer material coplanar with the first surface of the semiconductor substrate.

6. The method for preparing a filter according to claim 1, characterized in that: The depth of the sacrificial layer is less than or equal to 0.5 μm.

7. The method for preparing a filter according to claim 1, characterized in that: The forming of the piezoelectric stack structure on the first surface of the semiconductor substrate comprises: forming the piezoelectric stack structure under certain pressure conditions so that the piezoelectric stack structure has compressive stress; After the sacrificial layer is removed, the portion of the piezoelectric stack structure corresponding to the sacrificial layer is arched in a dome shape in a direction away from the first surface under the action of compressive stress; The cavity includes a lower half cavity below the first surface of the semiconductor substrate and an upper half cavity beyond the first surface of the semiconductor substrate, and the upper half cavity is dome-shaped.

8. The method for preparing a filter according to claim 7, characterized in that: The maximum height of the upper cavity is in the range of 1.5 μm to 2 μm.

9. A filter, characterized in that: The filter is prepared by using the filter preparation method according to any one of claims 1 to 8.

10. A filter, characterized in that: include: a semiconductor substrate including a first surface and a second surface opposite to each other; A piezoelectric stack structure, the piezoelectric stack structure is located on the first surface of the semiconductor substrate, the piezoelectric stack structure comprises a first electrode layer, a piezoelectric layer and a second electrode layer stacked in sequence, the material of the piezoelectric layer comprises a polycrystalline piezoelectric material with a columnar crystal structure; A cavity is provided, wherein the cavity is located between the semiconductor substrate and the piezoelectric stack structure, and the cavity includes a lower half cavity which is lower than the first surface of the semiconductor substrate and an upper half cavity which exceeds the first surface of the semiconductor substrate and protrudes toward the piezoelectric stack structure; wherein the upper half cavity is defined by the lower surface of the piezoelectric stack structure, the upper half cavity is dome-shaped, and the upper half cavity is formed by the portion of the piezoelectric stack structure corresponding to the lower half cavity arching away from the semiconductor substrate under the action of compressive stress.

11. The filter according to claim 10, characterized in that The stress on the portion of the piezoelectric stack defining the upper cavity is compressive stress.

12. The filter according to claim 10, characterized in that The depth of the lower half cavity is less than or equal to 0.5 μm.

13. The filter according to claim 10, characterized in that The maximum height of the upper cavity is in the range of 1.5 μm to 2 μm.

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