Doherty amplifier and output network thereof, and design method of Doherty amplifier

Abstract

An embodiment of the present application provides an output network for a Doherty amplifier, the output network comprising a combination node, a main output network, an auxiliary output network, and a combiner matching network, wherein the main output network comprises a first sub-network and a second sub-network connected in series, the auxiliary output network comprises a third sub-network, a fourth sub-network, and a fifth sub-network connected in series, the first sub-network and the third sub-network have the same circuit topology and both comprise at least an inductor and a capacitor, the fourth sub-network is connected between the third sub-network and the fifth sub-network, the second sub-network, the fourth sub-network, and the fifth sub-network have the same circuit topology and both comprise at least at least one of an inductor, a capacitor, and a transmission line, wherein the combiner matching network is configured such that the node impedance at the combination node is a complex impedance, and the main output network and the auxiliary output network are configured such that the node impedance is matched to the target load impedance of the main amplifier and the auxiliary amplifier.

Description

Technical Field

[0001] The present application relates to the field of wireless communications, and in particular, to an output network for a Doherty amplifier, a Doherty amplifier including the output network, and a method for designing a Doherty amplifier. Background Art

[0002] With the development of wireless communication technology, the communication bandwidth required by wireless communication systems continues to grow, and the modulation signals used by wireless communication systems are becoming more and more complex. In order to meet the requirements for bandwidth, efficiency, volume, etc. of wireless communication systems, higher and higher requirements are put forward for the efficiency, back-off power range, working bandwidth, size, etc. of power amplifiers (PA) in the RF front-end system of wireless communication networks.

[0003] In the related art, Doherty amplifiers can be used in the RF front end of wireless communication systems (including base stations, broadcasting and mobile terminals, etc.) to improve the efficiency of wireless communication systems. However, due to the increasing number of RF link units (including power amplifiers and antennas, etc.) contained in the RF front end system, and the large number of components used in the Doherty amplifier and the large circuit size, it is difficult to meet the design requirements of miniaturized amplifiers. In addition, since the load modulation of the Doherty amplifier is achieved by a quarter-wavelength transmission line, this structure results in a narrow operating bandwidth of the Doherty amplifier and a small high-efficiency back-off power range. Therefore, it is difficult for wireless communication systems to meet the increasingly high requirements in terms of bandwidth, efficiency, volume, etc. through traditional Doherty amplifiers. At present, there are some methods to increase the bandwidth by improving the load modulation network of the Doherty amplifier, but this often increases the size of the Doherty amplifier, making it difficult to achieve a good balance between the amplifier's efficiency, bandwidth, back-off power range and circuit size. Summary of the invention

[0004] In view of this, the present application provides an output network for a Doherty amplifier, a Doherty amplifier including the output network, and a method for designing a Doherty amplifier, so as to alleviate, mitigate, or even eliminate the above-mentioned problems.

[0005] An embodiment of the present application provides an output network for a Doherty amplifier, the Doherty amplifier comprising a main amplifier and an auxiliary amplifier, the output network comprising: a combination node, a main output network connected between the output end of the main amplifier and the combination node, an auxiliary output network connected between the output end of the auxiliary amplifier and the combination node, and a combining matching network connected between the combination node and the radio frequency output end of the Doherty amplifier, wherein the main output network comprises a first sub-network and a second sub-network connected in series, the auxiliary output network comprises a third sub-network, a fourth sub-network and a fifth sub-network connected in series, the first sub-network and the third sub-network have the same circuit topology and both comprise at least an inductor and a capacitor, the fourth sub-network is connected between the third sub-network and the fifth sub-network, the second sub-network, the fourth sub-network and the fifth sub-network have the same circuit topology and both comprise at least at least one of an inductor, a capacitor and a transmission line, wherein the combining matching network is configured such that the node impedance at the combination node is a complex impedance, and the main output network and the auxiliary output network are configured such that the node impedance matches the target load impedance of the main amplifier and the auxiliary amplifier.

[0006] According to some embodiments of the present application, the main output network is equivalent to a first transmission line in the working frequency band, and the auxiliary output network is equivalent to a second transmission line in the working frequency band. The electrical angle θ of the first transmission line is M and the electrical angle θ of the second transmission line A Satisfies: 70° < θ M < 90°, and 135°< θ A < 180°.

[0007] According to some embodiments of the present application, the output network is configured so that the output current I M and the auxiliary amplifier output current I A Satisfaction: I M The amplitude is not greater than I A The amplitude of I M and I A The phase difference is less than 90°.

[0008] According to some embodiments of the present application, the first sub-network and the third sub-network each include a first capacitor and a first inductor, one end of the first capacitor is connected to the output of the main amplifier or the auxiliary amplifier, the other end of the first capacitor is grounded, one end of the first inductor is connected to the output of the main amplifier or the auxiliary amplifier, and the other end of the first inductor is connected to the input of the second sub-network or the fourth sub-network.

[0009] According to some embodiments of the present application, the first sub-network and the third sub-network also include a second capacitor and a third transmission line, the third transmission line is connected between the first inductor and the DC voltage terminal, one end of the second capacitor is connected to the DC voltage terminal, the other end of the second capacitor is grounded, and the DC voltage terminal is configured to provide a DC bias voltage to the main amplifier or the auxiliary amplifier via the third transmission line and the first inductor.

[0010] According to some embodiments of the present application, the first sub-network and the third sub-network each include a second inductor, a third inductor, a third capacitor and a fourth capacitor, one end of the third capacitor is connected to the output of the main amplifier or the auxiliary amplifier, the other end of the third capacitor is grounded, one end of the second inductor is connected to the output of the main amplifier or the auxiliary amplifier, the other end of the second inductor and one end of the third inductor are both connected to one end of the fourth capacitor, the other end of the fourth capacitor is grounded, and the other end of the third inductor is connected to the input of the second sub-network or the fourth sub-network.

[0011] According to some embodiments of the present application, the first sub-network and the third sub-network both include a fourth inductor, a fifth inductor, a fifth capacitor and a sixth capacitor, one end of the fifth capacitor is connected to the output end of the main amplifier or the auxiliary amplifier, the other end of the fifth capacitor is grounded, one end of the fourth inductor is connected to the output end of the main amplifier or the auxiliary amplifier, the other end of the fourth inductor is connected to a DC voltage end, one end of the sixth capacitor is connected to the DC voltage end, the other end of the sixth capacitor is grounded, one end of the fifth inductor is connected to the output end of the main amplifier or the auxiliary amplifier, the other end of the fifth inductor is connected to the input end of the second sub-network or the fourth sub-network, and the DC voltage end is configured to provide a DC bias voltage to the main amplifier or the auxiliary amplifier via the fourth inductor.

[0012] According to some embodiments of the present application, the second sub-network and the fourth sub-network both include a sixth inductor and a seventh capacitor, one end of the sixth inductor is connected to the output end of the first sub-network or the third sub-network, the other end of the sixth inductor is connected to one end of the seventh capacitor, and the other end of the seventh capacitor is grounded.

[0013] According to some embodiments of the present application, the second sub-network and the fourth sub-network each further include a seventh inductor, and the seventh inductor forms a T-type circuit with the sixth inductor and the seventh capacitor.

[0014] According to some embodiments of the present application, the second sub-network and the fourth sub-network each further include an eighth capacitor, and the eighth capacitor forms a π-type circuit with the sixth inductor and the seventh capacitor.

[0015] According to some embodiments of the present application, the second sub-network and the fourth sub-network both include a fourth transmission line.

[0016] According to some embodiments of the present application, the second sub-network and the fourth sub-network each further include a ninth capacitor, and the ninth capacitor is connected between the fourth transmission line and ground.

[0017] According to some embodiments of the present application, the combined matching network includes an eighth inductor and a tenth capacitor, one end of the eighth inductor is connected to the combined node, the other end of the eighth inductor is connected to one end of the tenth capacitor, and the other end of the tenth capacitor is grounded.

[0018] According to some embodiments of the present application, the combiner matching network also includes a ninth inductor, one end of the ninth inductor is connected between the eighth inductor and the tenth capacitor, and the other end of the ninth inductor is connected to a DC voltage terminal, and the DC voltage terminal is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the ninth inductor, the eighth inductor, the main output network and the auxiliary output network.

[0019] According to some embodiments of the present application, the combiner matching network includes a fifth transmission line, a sixth transmission line and an eleventh capacitor, one end of the fifth transmission line is connected to the combination node, the other end of the fifth transmission line is connected to one end of the sixth transmission line, the other end of the sixth transmission line is connected to the RF output end of the Doherty amplifier, one end of the eleventh capacitor is connected between the fifth transmission line and the sixth transmission line, and the other end of the eleventh capacitor is grounded.

[0020] According to some embodiments of the present application, the combiner matching network includes a seventh transmission line, an eighth transmission line, a ninth transmission line and a twelfth capacitor, one end of the seventh transmission line is connected to the combination node, the other end of the seventh transmission line is connected to one end of the eighth transmission line, the other end of the eighth transmission line is connected to a DC voltage terminal, one end of the twelfth capacitor is connected to the DC voltage terminal, the other end of the twelfth capacitor is grounded, one end of the ninth transmission line is connected between the seventh transmission line and the eighth transmission line, the other end of the ninth transmission line is connected to the RF output terminal of the Doherty amplifier, and the DC voltage terminal is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the eighth transmission line, the seventh transmission line, the main output network and the auxiliary output network.

[0021] According to some embodiments of the present application, at least one of the first to twelfth capacitors can be implemented in at least one of the following forms: PCB surface mount components, integrated circuit devices, and wherein at least one of the first to ninth inductors can be implemented in at least one of the following forms: PCB surface mount components, integrated circuit devices, bonding wires, microstrip lines, metal windings, and transmission lines.

[0022] According to some embodiments of the present application, at least one transmission line among the third to ninth transmission lines may be implemented in at least one of the following forms: a microstrip line, a stripline, a coplanar waveguide, and a substrate integrated waveguide.

[0023] Another embodiment of the present application provides a Doherty amplifier, comprising: a main amplifier; an auxiliary amplifier; and an output network according to any of the aforementioned embodiments, wherein the output network is configured to receive a first amplified signal output by the main amplifier and a second amplified signal output by the auxiliary amplifier, so that the first amplified signal and the second amplified signal are combined at the combination node to be provided to the RF output end of the Doherty amplifier.

[0024] Another embodiment of the present application provides a method for designing a Doherty amplifier, the Doherty amplifier comprising a main amplifier, an auxiliary amplifier, and an output network as claimed in claim 1, wherein the method comprises: setting a target performance indicator of the Doherty amplifier, the target performance indicator comprising at least an operating frequency, a saturation power, and a dynamic range of the Doherty amplifier; selecting transistors for the main amplifier and the auxiliary amplifier according to the target performance indicator; determining first, second, and third target impedances based on a load-pull test or a simulation analysis, wherein the first target impedance is a load impedance that makes the main amplifier most efficient when the Doherty amplifier is in a back-off power state, the second target impedance is a load impedance that makes the main amplifier most efficient when the output power of the main amplifier reaches a saturation power, and the third target impedance is a load impedance that makes the auxiliary amplifier most efficient when the output power of the auxiliary amplifier reaches a saturation power; based on the first, second, and third target impedances, determining the circuit topology and component parameters of each sub-network in the main output network and the auxiliary output network, and determining the circuit topology and component parameters of the combiner matching network.

[0025] In an output network for a Doherty amplifier according to some embodiments of the present application, a main output network, an auxiliary output network, and a combining matching network are provided, wherein the main output network includes a first sub-network and a second sub-network connected in series, and the auxiliary output network includes a third sub-network, a fourth sub-network, and a fifth sub-network connected in series, wherein the combining matching network is configured so that the node impedance at the combined node is a complex impedance, and the main output network and the auxiliary output network are configured so that the node impedance is matched to the target load impedance of the main amplifier and the auxiliary amplifier, so that the Doherty amplifier can work efficiently from low power to high power. On the other hand, the first sub-network and the third sub-network have the same circuit topology and both include at least an inductor and a capacitor, the fourth sub-network is connected between the third sub-network and the fifth sub-network, the second sub-network, the fourth sub-network, and the fifth sub-network have the same circuit topology and both include at least one of an inductor, a capacitor, and a transmission line, thereby helping to simplify the structure of the output network of the Doherty amplifier and the corresponding design process.

[0026] These and other aspects of the application will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In the following description of exemplary embodiments in conjunction with the accompanying drawings, more details, features and advantages of the technical solution of the present application are disclosed, in which:

[0028] Figure 1 An exemplary principle diagram of a Doherty amplifier in the related art is schematically shown;

[0029] Figure 2 Schematically illustrates an exemplary schematic diagram of an output network for a Doherty amplifier according to some embodiments of the present application;

[0030] Figure 3 Schematically shows some embodiments of the present application Figure 2 An exemplary schematic diagram of the output network in achieving load modulation at low power;

[0031] Figure 4 Schematically shows some embodiments of the present application Figure 2 An exemplary schematic diagram of the output network in achieving load modulation at high power;

[0032] Figure 5 Schematically illustrates an exemplary circuit topology diagram of a first sub-network and a third sub-network according to some embodiments of the present application;

[0033] Figure 6Schematically illustrates an exemplary circuit topology diagram of a second sub-network, a fourth sub-network, and a fifth sub-network according to some embodiments of the present application;

[0034] Figure 7 Schematically illustrates an exemplary circuit topology diagram of a combiner matching network according to some embodiments of the present application;

[0035] Figure 8 Schematically shows an exemplary principle diagram of a Doherty amplifier according to some embodiments of the present application;

[0036] Fig. 9 A flow chart schematically illustrates a method for designing a Doherty amplifier according to some embodiments of the present application;

[0037] Fig.10 Schematically illustrates the use of some embodiments of the present application Fig. 9 An exemplary schematic diagram of a Doherty amplifier designed by the method in FIG.

[0038] Fig.11 Schematically illustrates the use of other embodiments according to the present application Fig. 9 An exemplary schematic diagram of a Doherty amplifier designed by the method in FIG.

[0039] Fig.12 Schematically showing an example performance diagram of a Doherty amplifier according to some embodiments of the present application;

[0040] Fig.13 An example performance diagram of a Doherty amplifier according to some embodiments of the present application is schematically shown. DETAILED DESCRIPTION

[0041] Several embodiments of the present application will be described in more detail below with reference to the accompanying drawings so that those skilled in the art can implement the technical solution of the present application. The technical solution of the present application can be embodied in many different forms and purposes, and should not be limited to the embodiments described herein. These embodiments are provided to make the technical solution of the present application clear and complete, but the embodiments do not limit the scope of protection of the present application.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this application belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0043] Figure 1Schematically shows an exemplary principle diagram of a Doherty amplifier in the related art. Figure 1 As shown, the Doherty amplifier includes two amplifiers (a main amplifier and an auxiliary amplifier), the main amplifier and the auxiliary amplifier are respectively connected to two output ports of a power divider (not shown), and the RF output port of the main amplifier is connected to an impedance Z M , a transmission line with an electrical length of 90° (i.e., a quarter-wavelength transmission line), and an auxiliary amplifier connected to a load R L In the related art, the main amplifier works in class B or class AB, and the auxiliary amplifier works in class C. As the input power increases, the output current of the auxiliary amplifier after it is turned on will affect the load R L The modulation effect is generated, and then the respective loads of the two amplifiers are dynamically modulated (this process is also called "dynamic load modulation"). The two amplifiers do not work in turns, but the main amplifier works all the time, and the auxiliary amplifier starts to work when the input power reaches the set peak value. The quarter-wavelength transmission line in the output path of the main amplifier can play a role in phase compensation, so that the output signal in the output path of the main amplifier and the output signal in the output path of the auxiliary amplifier are in the same phase at the combining point.

[0044] With the continuous development of communication technology, Multiple-Input Multiple-Output (MIMO) systems are becoming more and more widely used. The RF front-end system of the MIMO system contains multiple (for example, dozens or even hundreds) RF link units, which puts higher and higher requirements on the miniaturization design of the power amplifier in the RF link unit. However, the traditional solutions are highly complex, use many components, and have large circuit size, which makes it difficult to meet the design requirements of miniaturized amplifiers.

[0045] On the other hand, the increase in circuit components brings more problems to the integrated design of power amplifiers. Not only does the design difficulty increase, the overall circuit size increases, and the chip cost increases, but the circuit loss also becomes greater and the efficiency of the power amplifier decreases, which makes the design of efficient, energy-saving, and low-cost systems more difficult.

[0046] In addition, with the continuous iteration of communication systems, the communication bandwidth is increasing exponentially. For example, in the 5G scenario, the communication bandwidth has reached 500 MHz or even higher, which poses a high challenge to the working bandwidth of the power amplifier. Figure 1 In the present invention, the load modulation of the Doherty amplifier is realized by a quarter-wavelength transmission line, and this structure has only a narrow working bandwidth (usually less than 200 MHz), so this architecture is far from meeting the requirements of broadband operation of today's systems.

[0047] Figure 2 Schematically shows an exemplary schematic diagram of an output network 200 for a Doherty amplifier according to some embodiments of the present application. Figure 2As shown, the output network 200 includes: a combining node 230, a main output network 210 connected between the output end of the main amplifier of the Doherty amplifier and the combining node 230, an auxiliary output network 220 connected between the output end of the auxiliary amplifier of the Doherty amplifier and the combining node 230, and a combining matching network 240 connected between the combining node 230 and the RF output end of the Doherty amplifier.

[0048] Exemplarily, the main output network 210 includes a first sub-network 211 and a second sub-network 212 connected in series, and the auxiliary output network 220 includes a third sub-network 221, a fourth sub-network 222, and a fifth sub-network 223 connected in series, wherein the first sub-network 211 and the third sub-network 221 have the same circuit topology and each includes at least an inductor and a capacitor, the fourth sub-network 222 is connected between the third sub-network 221 and the fifth sub-network 223, the second sub-network 212, the fourth sub-network 222, and the fifth sub-network 223 have the same circuit topology and each includes at least one of an inductor, a capacitor, and a transmission line, and the combining matching network 240 is configured such that the node impedance at the combined node 230 is a complex impedance Z combine The main output network 210 and the auxiliary output network 220 are configured such that the node impedance is matched to the target load impedance of the main amplifier and the auxiliary amplifier.

[0049] like Figure 2 As shown, Z combine is the equivalent impedance seen from the combining node 230 to the combining matching network 240, which in some cases can be regarded as the voltage U at the combining node 230. TC The current I flowing into the combining matching network 240 TC The combining and matching network 240 may include appropriate types and numbers of circuit devices, as long as these circuit devices make the node impedance at the combined node 230 a complex impedance Z combine For example, the combining and matching network 240 may include an LC circuit, which makes the load (eg Figure 1 R L ) is transformed into a complex impedance Z combine , that is, the node impedance at the combined node 230 is the complex impedance Z combine .

[0050] It should be noted that, in the present application, the expression "A and B have the same circuit topology" indicates that A and B include the same type and the same number of circuit elements (devices, components), and the connection relationship between these circuit elements in A and B is also the same. Exemplarily, the first sub-network 211 and the third sub-network 221 having the same circuit topology may both include an LC circuit or an LLC circuit. In addition, although the first sub-network 211 and the third sub-network 221 have the same circuit topology, this does not mean that the component parameters of the first sub-network 211 and the third sub-network 221 are also the same. Similarly, for the second sub-network 212, the fourth sub-network 222 and the fifth sub-network 223, their component parameters are not necessarily the same. For example, they all include LC circuits, but the inductance and capacitance values ​​in each sub-network are not the same.

[0051] exist Figure 2 In the illustrated embodiment, the first sub-network 211 and the second sub-network 212 form the main output network 210, and the third sub-network 221, the fourth sub-network 222 and the fifth sub-network 223 form the auxiliary output network 220, but this does not exclude the situation that the main output network 210 and the auxiliary output network 220 include other components. For example, in other embodiments, the main output network 210 may also include other circuit components, such as a capacitor for isolating direct current; similarly, the auxiliary output network 220 may also include other circuit components, such as a capacitor for isolating direct current. Additionally or alternatively, the main output network 210 may also include other sub-networks, such as one or more sixth sub-networks (whose circuit topology may be the same as that of the second sub-network 212); the auxiliary output network 220 may also include other sub-networks, such as one or more seventh sub-networks (whose circuit topology may be the same as that of the fourth sub-network 222).

[0052] In addition, the combined node 230 indicates the common connection point of the main output network 210, the auxiliary output network 220 and the combining matching network 240. Exemplarily, the combined node 230 can be the electrical common connection point of the main output network 210, the auxiliary output network 220 and the combining matching network 240. The combined node 230 can also be the electrical node at the output end of the main output network 210. The combined node 230 can also be the electrical node at the output end of the auxiliary output network 220. Even the combined node 230 can be the electrical node at the input end of the combining matching network 240.

[0053] Specifically, the following Figure 3 and Figure 4 To illustrate the impedance matching process of the output network 200 .

[0054] like Figure 3As shown, under low power, the auxiliary amplifier is not turned on, so it can be equivalent to an open circuit state. At this time, the branch where the auxiliary output network 320 is located (hereinafter referred to as the auxiliary path) provides an auxiliary path impedance Z at the combination node 330. off , which is related to the node impedance Z combine Connected in parallel to one end of the branch where the main output network 310 is located (hereinafter referred to as the main path). Under the fallback power, the main output network 310 can reduce the auxiliary path impedance Z off and node impedance Z combine The parallel impedance Z off / / Z combine Converted to the target load impedance of the main amplifier at back-off power ( Figure 3 Z goal, BO ). For the main amplifier or auxiliary amplifier (usually implemented as a transistor), its target load impedance indicates the best power matching impedance of the amplifier at a specific power level, that is, the load impedance that can make the amplifier reach the highest efficiency at a specific power level. The target load impedance depends on the parameters of the amplifier itself and the actual power level, which can be obtained by theoretical calculation or simulation analysis, or by experimental measurement methods (such as load pull test). The main output network 310 connects the parallel impedance Z off / / Z combine Converted to the target load impedance Z of the main amplifier at back-off power goal, BO , which enables the main amplifier to still operate efficiently at backed-off power.

[0055] like Figure 4 As shown, the auxiliary amplifier is turned on at high power, and the current flowing through the auxiliary circuit is I T2 , the current flowing through the main circuit is I T1 According to Kirchhoff's voltage law and Kirchhoff's current law, the equivalent impedance of the main circuit is (1+I T2 / I T1 )*Z combine The combined equivalent impedance of the auxiliary circuit is (1+I T1 / I T2 )*Z combine , so the current I T2 The combined equivalent impedance of the main circuit and the combined equivalent impedance of the auxiliary circuit can be dynamically modulated. Under saturated power, the main output network 410 (including the first sub-network 411 and the second sub-network 412) can modulate the combined equivalent impedance of the main circuit (1+I T2 / I T1 )*Z combine Converted to the target load impedance of the main amplifier at saturation power ( Figure 4 Z goal, MThe auxiliary output network 420 (including the third sub-network 421, the fourth sub-network 422 and the fifth sub-network 423) can convert the combined equivalent impedance of the auxiliary circuit (1+I T1 / I T2 )*Z combine Converted to the target load impedance of the auxiliary amplifier at saturation power ( Figure 4 Z goal, A ). The main output network 410 and the auxiliary output network 420 respectively convert the combined equivalent impedance of the main path and the combined equivalent impedance of the auxiliary path into the corresponding target load impedance of the main amplifier and the auxiliary amplifier at saturated power, so that the main amplifier and the auxiliary amplifier can both work efficiently at saturated power.

[0056] The “combined equivalent impedance” mentioned here refers to the equivalent impedance seen from a combining node (i.e., combining node 430) on a certain path. Figure 4 As shown in the figure, the combined equivalent impedance of the main circuit is the voltage U at the output end of the main circuit. T1 With the main output current I T1 The ratio of the auxiliary circuit combined equivalent impedance is the auxiliary circuit output voltage U T2 With auxiliary output current I T2 Ratio.

[0057] In the present application, the main amplifier and the auxiliary amplifier may include and are not limited to, for example, power transistors based on VDMOS, LDMOS or GaN, and different transistor technologies provide different performance advantages in terms of output power, gain and performance. For example, the type of transistor can be selected according to requirements such as frequency, bandwidth, cost, etc. According to some embodiments of the present application, the main amplifier and the auxiliary amplifier may be the same type of power transistors (such as GaN-based power transistors), and the parameters and sizes of the transistors used as the main amplifier and the transistors used as the auxiliary amplifier may be exactly the same. In other embodiments, the transistors used as the main amplifier and the transistors used as the auxiliary amplifier differ in at least one of the aspects of transistor type, parameters and size. According to another embodiment of the present application, the main amplifier or the auxiliary amplifier may include a plurality of transistors. The specific implementation of the main amplifier and the auxiliary amplifier is not specifically limited herein.

[0058] By using a Doherty amplifier Figure 2 The output network 200 shown can combine the node impedance Z at the node 230 at different power levels. combineThe target load impedance of the main amplifier and the auxiliary amplifier of the Doherty amplifier is matched, so that the main amplifier can still work efficiently at the back-off power, and the main amplifier and the auxiliary amplifier can work efficiently at the saturated power, that is, the Doherty amplifier can work efficiently at different power levels. On the other hand, the first sub-network 211 and the third sub-network 221 have the same circuit topology and both include at least inductors and capacitors, and the second sub-network 212, the fourth sub-network 222 and the fifth sub-network 223 have the same circuit topology and both include at least one of inductors, capacitors and transmission lines, thereby helping to simplify the structure of the output network of the Doherty amplifier and the corresponding design process. In addition, as will be further described below, by reasonably setting the circuit topology and component parameters of each sub-network in the main output network 210 and the auxiliary output network 220, the Doherty amplifier can have a larger working bandwidth and a deeper back-off power (i.e., a larger back-off power range) while working efficiently.

[0059] In some embodiments, the main output network can be equivalent to the first transmission line TL1 in the working frequency band, the auxiliary output network can be equivalent to the second transmission line TL2 in the working frequency band, and the electrical angle θ of the first transmission line TL1 M and the electrical angle θ of the second transmission line TL2 A Satisfies: 70° < θ M < 90°, and 135°< θ A < 180°. The above range can be achieved by appropriately selecting the circuit topology and component parameters of the main output network and the auxiliary output network. Figure 2 Taking the output network 200 shown in the figure as an example, specifically, by selecting the circuit topology and component parameters of the first sub-network 211, the second sub-network 212, the third sub-network 221, the fourth sub-network 222 and the fifth sub-network 223, the transmission lines (the first transmission line TL1 and the second transmission line TL2) equivalent to the main output network 210 and the auxiliary output network 220 in the working frequency band have corresponding characteristic impedances and electrical lengths, and the electrical angle θ of the first transmission line TL1 is M and the electrical angle θ of the second transmission line TL2 A The above range is satisfied. The above range helps the Doherty amplifier to have a larger operating bandwidth and a deeper back-off power while operating at high efficiency.

[0060] In some embodiments, the output network can be configured so that the output current I M and the auxiliary amplifier output current I A Satisfaction: I M The amplitude is not greater than I A The amplitude of IM and I A The phase difference is less than 90°, that is, I A The phase of I M The phase obtained is less than 90°. Similar to the above, the circuit topology and component parameters of the main output network and the auxiliary output network can be appropriately selected to achieve the I M and I A The above constraints also help the Doherty amplifier to have a larger operating bandwidth and deeper back-off power while operating at high efficiency.

[0061] Figure 5 An exemplary circuit topology diagram of a first sub-network and a third sub-network according to some embodiments of the present application is schematically shown.

[0062] like Figure 5 As shown, in some embodiments, the first sub-network and the third sub-network may have a circuit topology 510, that is, they both include a first capacitor C1 and a first inductor L1, one end of the first capacitor C1 is connected to the output of the main amplifier or the auxiliary amplifier (that is, one end of the first capacitor C1 in the first sub-network is connected to the output of the main amplifier, and one end of the first capacitor C1 in the third sub-network is connected to the output of the auxiliary amplifier), the other end of the first capacitor C1 is grounded, one end of the first inductor L1 is connected to the output of the main amplifier or the auxiliary amplifier (that is, one end of the first inductor L1 in the first sub-network is connected to the output of the main amplifier, and one end of the first inductor L1 in the third sub-network is connected to the output of the auxiliary amplifier), and the other end of the first inductor L1 is connected to the input of the second sub-network or the fourth sub-network (that is, one end of the first inductor L1 in the first sub-network is connected to the input of the second sub-network, and one end of the first inductor L1 in the third sub-network is connected to the input of the fourth sub-network).

[0063] In some embodiments, the first sub-network and the third sub-network may have a circuit topology 520, that is, compared with the circuit topology 510, they both further include a second capacitor C2 and a third transmission line TL3, the third transmission line TL3 is connected between the first inductor L1 and the DC voltage terminal, one end of the second capacitor C2 is connected to the DC voltage terminal, the other end of the second capacitor C2 is grounded, and the DC voltage terminal is configured to provide a DC bias voltage V to the main amplifier or the auxiliary amplifier via the third transmission line TL3 and the first inductor L1. DD .

[0064] In some embodiments, the first sub-network and the third sub-network may have a circuit topology 530, that is, they both include a second inductor L2, a third inductor L3, a third capacitor C3, and a fourth capacitor C4, one end of the third capacitor C3 is connected to the output of the main amplifier or the auxiliary amplifier (that is, one end of the third capacitor C3 in the first sub-network is connected to the output of the main amplifier, and one end of the third capacitor C3 in the third sub-network is connected to the output of the auxiliary amplifier), the other end of the third capacitor C3 is grounded, one end of the second inductor L2 is connected to the output of the main amplifier or the auxiliary amplifier (that is, the first sub-network is connected to the output of the main amplifier), and one end of the third capacitor C3 is grounded. One end of the second inductor L2 in the network is connected to the output end of the main amplifier, and one end of the second inductor L2 in the third sub-network is connected to the output end of the auxiliary amplifier), the other end of the second inductor L2 and one end of the third inductor L3 are both connected to one end of a fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, and the other end of the third inductor L3 is connected to the input end of the second sub-network or the fourth sub-network (that is, the other end of the third inductor L3 in the first sub-network is connected to the input end of the second sub-network, and the other end of the third inductor L3 in the third sub-network is connected to the input end of the fourth sub-network).

[0065] In some embodiments, the first sub-network and the third sub-network may have a circuit topology 540, that is, they both include a fourth inductor L4, a fifth inductor L5, a fifth capacitor C5, and a sixth capacitor C6, one end of the fifth capacitor C5 is connected to the output terminal of the main amplifier or the auxiliary amplifier (that is, one end of the fifth capacitor C5 in the first sub-network is connected to the output terminal of the main amplifier, and one end of the fifth capacitor C5 in the third sub-network is connected to the output terminal of the auxiliary amplifier), the other end of the fifth capacitor C5 is grounded, one end of the fourth inductor L4 is connected to the output terminal of the main amplifier or the auxiliary amplifier (that is, one end of the fourth inductor L4 in the first sub-network is connected to the output terminal of the main amplifier, and one end of the fourth inductor L4 in the third sub-network is connected to the output terminal of the auxiliary amplifier), and the other end of the fourth inductor L4 is grounded. The first sub-network is connected to the DC voltage terminal, one end of the sixth capacitor C6 is connected to the DC voltage terminal, the other end of the sixth capacitor C6 is grounded, one end of the fifth inductor L5 is connected to the output terminal of the main amplifier or the auxiliary amplifier (that is, one end of the fifth inductor L5 in the first sub-network is connected to the output terminal of the main amplifier, and one end of the fifth inductor L5 in the third sub-network is connected to the output terminal of the auxiliary amplifier), the other end of the fifth inductor L5 is connected to the input terminal of the second sub-network or the fourth sub-network (that is, the other end of the fifth inductor L5 in the first sub-network is connected to the input terminal of the second sub-network, and the other end of the fifth inductor L5 in the third sub-network is connected to the input terminal of the fourth sub-network), and the DC voltage terminal is configured to provide a DC bias voltage V to the main amplifier or the auxiliary amplifier via the fourth inductor L4. DD .

[0066] Figure 6 An exemplary circuit topology diagram of a second sub-network, a fourth sub-network, and a fifth sub-network according to some embodiments of the present application is schematically shown.

[0067] like Figure 6 As shown, in some embodiments, taking the second sub-network and the fourth sub-network as an example, the second sub-network and the fourth sub-network may have a circuit topology 610, that is, they both include a sixth inductor L6 and a seventh capacitor C7, one end of the sixth inductor L6 is connected to the output end of the first sub-network or the third sub-network (that is, one end of the sixth inductor L6 in the second sub-network is connected to the output end of the first sub-network, and one end of the sixth inductor L6 in the fourth sub-network is connected to the output end of the third sub-network), the other end of the sixth inductor L6 is connected to one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded.

[0068] In some embodiments, the second sub-network and the fourth sub-network may have a circuit topology 620 , that is, compared with the circuit topology 610 , they both further include a seventh inductor L7 , and the seventh inductor L7 forms a T-type circuit with the sixth inductor L6 and the seventh capacitor C7 .

[0069] In some embodiments, the second sub-network and the fourth sub-network may have a circuit topology 630 , that is, compared with the circuit topology 610 , they both further include an eighth capacitor C8 , and the eighth capacitor C8 forms a π-type circuit with the sixth inductor L6 and the seventh capacitor C7 .

[0070] In some embodiments, the second sub-network and the fourth sub-network may have a circuit topology 640 , ie, they both include a fourth transmission line TL4 .

[0071] In some embodiments, the second sub-network and the fourth sub-network may have a circuit topology 650 , that is, compared with the circuit topology 640 , they both further include a ninth capacitor C9 , and the ninth capacitor C9 is connected between the fourth transmission line TL4 and the ground.

[0072] It should be noted that although Figure 5 and Figure 6 The various circuit topologies are shown in FIG. 1 , and those skilled in the art will understand that Figure 5 The circuit topologies 510, 520, 530 and 540 shown, and Figure 6 At least one of the illustrated circuit topologies 610 , 620 , 630 , 640 , and 650 may include other circuit components, such as capacitors for isolating direct current.

[0073] Figure 7 An exemplary circuit topology diagram of a combiner matching network according to some embodiments of the present application is schematically shown.

[0074] like Figure 7 As shown, in some embodiments, the combining matching network may have a circuit topology 710, that is, the combining matching network includes an eighth inductor L8 and a tenth capacitor C 10 , one end of the eighth inductor L8 is connected to the combination node, and the other end of the eighth inductor L8 is connected to the tenth capacitor C 10 One end of the tenth capacitor C 10 The other end is grounded.

[0075] In some embodiments, the combining and matching network may have a circuit topology 720, that is, compared with the circuit topology 710, the combining and matching network further includes a ninth inductor L9, one end of which is connected between the eighth inductor L8 and the tenth capacitor C 10The other end of the ninth inductor L9 is connected to a DC voltage terminal, and the DC voltage terminal is configured to provide a DC bias voltage V to the main amplifier and the auxiliary amplifier via the ninth inductor L9, the eighth inductor L8, the main output network and the auxiliary output network. DD .

[0076] In some embodiments, the combining and matching network may have a circuit topology 730, that is, the combining and matching network includes a fifth transmission line TL5, a sixth transmission line TL6 and an eleventh capacitor C 11 , one end of the fifth transmission line TL5 is connected to the combination node, the other end of the fifth transmission line TL5 is connected to one end of the sixth transmission line TL6, the other end of the sixth transmission line TL6 is connected to the RF output end of the Doherty amplifier, and the eleventh capacitor C 11 One end of the eleventh capacitor C is connected between the fifth transmission line TL5 and the sixth transmission line TL6. 11 The other end is grounded.

[0077] In some embodiments, the combining and matching network may have a circuit topology 740, that is, the combining and matching network includes a seventh transmission line TL7, an eighth transmission line TL8, a ninth transmission line TL9 and a twelfth capacitor C 12 One end of the seventh transmission line TL7 is connected to the combination node, the other end of the seventh transmission line TL7 is connected to one end of the eighth transmission line TL8, the other end of the eighth transmission line TL8 is connected to the DC voltage terminal, and the twelfth capacitor C 12 One end of the twelfth capacitor C is connected to the DC voltage terminal. 12 The other end of the ninth transmission line TL9 is grounded, one end of the ninth transmission line TL9 is connected between the seventh transmission line TL7 and the eighth transmission line TL8, the other end of the ninth transmission line TL9 is connected to the RF output end of the Doherty amplifier, and the DC voltage end is configured to provide a DC bias voltage V to the main amplifier and the auxiliary amplifier via the eighth transmission line TL8, the seventh transmission line TL7, the main output network and the auxiliary output network DD .

[0078] It should be noted that although Figure 7 The various circuit topologies are shown in FIG. 1 , and those skilled in the art will understand that Figure 7 At least one of the circuit topologies 710, 720, 730 and 740 shown may include other circuit devices, such as a capacitor for isolating direct current. By using this capacitor for isolating direct current, the direct current signal from the direct current voltage terminal will not be transmitted to the RF output terminal of the Doherty amplifier, thereby protecting sensitive RF components (loads) from the influence of direct current.

[0079] In addition, in the above Figure 5 and Figure 7 In the described embodiment, it is disclosed that a DC bias voltage V is provided to the main amplifier and the auxiliary amplifier. DD , but this is only schematic, and those skilled in the art should understand that the number of related bias circuits and their positions in the Doherty amplifier circuit can be adjusted according to actual applications. Exemplarily, when the configuration parameters of the main amplifier and the auxiliary amplifier of the Doherty amplifier are different (for example, when they are not the same type of transistors), corresponding DC bias circuits can be set for the main amplifier and the auxiliary amplifier, respectively. Exemplarily, a corresponding DC bias circuit can be set in the first sub-network or the second sub-network to provide a DC bias for the main amplifier (for example, see the circuit topologies 520 and 540 described above), and a corresponding DC bias circuit can be set in the third sub-network or the fourth sub-network or the fifth sub-network to provide a DC bias for the auxiliary amplifier. Alternatively, a corresponding DC bias circuit can be set in the combiner matching network to provide a DC bias for the main amplifier and the auxiliary amplifier (for example, see the circuit topologies 720 and 740 described above).

[0080] In some embodiments, at least one of the first to twelfth capacitors can be implemented in at least one of the following forms: PCB surface mount components, integrated circuit devices, and wherein at least one of the first to ninth inductors can be implemented in at least one of the following forms: PCB surface mount components, integrated circuit devices, bonding wires, microstrip lines, metal windings, and transmission lines.

[0081] In some embodiments, at least one transmission line among the third to ninth transmission lines may be implemented in at least one of the following forms: a microstrip line, a stripline, a coplanar waveguide, or a substrate integrated waveguide.

[0082] Microstrip line is a planar transmission line that is currently used most in hybrid microwave integrated circuits and monolithic microwave integrated circuits. It is a strip conductor (signal line) that is separated from the ground by a dielectric. Microstrip line can be implemented in a variety of forms such as PCB microstrip line and integrated circuit microstrip line. Factors affecting the characteristic impedance of the microstrip line include the thickness, width, distance from the ground, and dielectric constant of the dielectric of the microstrip line. The length of the microstrip line can correspond to the electrical angle of the microstrip line. Exemplarily, at least one of the third to ninth transmission lines can be implemented by a microstrip line. Accordingly, the length, width and other dimensional parameters of the microstrip line can be configured based on the characteristic impedance and electrical angle of the corresponding transmission line in the third to ninth transmission lines. By using a microstrip line to implement the corresponding transmission line in the third to ninth transmission lines, a transmission line that meets the characteristic parameter requirements can be obtained, so that the Doherty amplifier can have a smaller circuit size, higher working efficiency, larger working bandwidth and deeper back-off power (i.e., a larger back-off power range). In particular, the microstrip line can be implemented by adopting a substrate with a high dielectric constant to further reduce the size of the related circuit.

[0083] In other embodiments, at least one of the third to ninth transmission lines may include a stripline, a coplanar waveguide, or a substrate integrated waveguide. A stripline is a high-frequency transmission conductor placed between two parallel ground planes (or power planes) between dielectrics. Striplines have the advantages of small size, light weight, wide bandwidth, high quality factor, simple process, and low cost, and are suitable for making high-performance (wideband, high quality factor, high isolation) passive components. Coplanar waveguide (CPW) is formed by making a central conductor strip on one surface of a dielectric substrate and making conductor planes on both sides adjacent to the central conductor strip. In the millimeter wave frequency band, the coplanar waveguide has less loss than microstrip and stripline circuits. Substrate integrated waveguide (SIW) uses metal through holes to realize the field propagation mode of the waveguide on the dielectric substrate, and has the advantages of low loss, low radiation, and high quality factor. In some embodiments, at least one of the third to ninth transmission lines may be composed of only one of a stripline, a coplanar waveguide, or a substrate integrated waveguide.

[0084] Another embodiment of the present application provides a Doherty amplifier, comprising: a main amplifier; an auxiliary amplifier; and an output network according to any of the foregoing embodiments, wherein the output network is configured to receive a first amplified signal output by the main amplifier and a second amplified signal output by the auxiliary amplifier, so that the first amplified signal and the second amplified signal are combined at the combination node to be provided to the RF output end of the Doherty amplifier. Since the Doherty amplifier includes the output network according to the foregoing embodiment of the present application, the Doherty amplifier has the advantages brought by the corresponding output network. Figure 8Let's further describe this Doherty amplifier.

[0085] like Figure 8 As shown, the RF input signal is connected to the main amplifier and the auxiliary amplifier after passing through the power divider (these amplifiers can be single-stage transistors or multi-stage transistors cascaded), where the input side of the main amplifier and the auxiliary amplifier also includes an input matching network (i.e. Figure 8 The input matching network 1 and input matching network 2) and the phase shifter network (i.e. Figure 8 The phase shifter 1 and phase shifter 2 shown in the figure), wherein the phase shifter network can be set only in the auxiliary circuit or only in the main circuit (for example, only in the auxiliary circuit). The output side of the main amplifier and the auxiliary amplifier is an output network according to any of the aforementioned embodiments of the present application, and the output network includes a main output network 810 and an auxiliary output network 820, the main output network 810 includes a first sub-network 811 and a second sub-network 812 connected in series, and the auxiliary output network 820 includes a third sub-network 821, a fourth sub-network 822 and a fifth sub-network 823 connected in series. The combining matching network 840 is configured so that the node impedance at the combined node 830 is a complex impedance, and the main output network 810 and the auxiliary output network 820 are configured so that the node impedance is matched to the target load impedance of the main amplifier and the auxiliary amplifier. Exemplarily, the (drain) DC bias voltage can be fed through the DC bias circuit in the first sub-network 811 and the third sub-network 821 (or the combining matching network 840).

[0086] The first sub-network 811 and the third sub-network 821 may have the Figure 5 In any of the circuit topologies described above, the second sub-network 812, the fourth sub-network 822, and the fifth sub-network 823 may have Figure 6 By selecting the circuit topology and component parameters of the first sub-network 811, the second sub-network 812, the third sub-network 821, the fourth sub-network 822 and the fifth sub-network 823, the transmission lines equivalent to the main output network 810 and the auxiliary output network 820 in the working frequency band have corresponding characteristic impedance, electrical length and electrical angle, so that the Doherty amplifier has a larger working bandwidth and deeper back-off power while working at high efficiency.

[0087] It should be noted that although Figure 8 The Doherty amplifier shown in the figure only includes one auxiliary amplifier, but those skilled in the art should understand that the Doherty amplifier disclosed in the present application may include more auxiliary amplifiers (for example, two auxiliary amplifiers). On the basis of the aforementioned embodiments of the present application, the multiple auxiliary output networks on the multiple auxiliary circuits corresponding to these auxiliary amplifiers may all adopt the circuit structure disclosed in the aforementioned embodiments of the present application.

[0088] Another embodiment of the present application provides a method for designing a Doherty amplifier, wherein the Doherty amplifier includes a main amplifier, an auxiliary amplifier, and Figure 2 The output network 200 described, Fig. 9 A flowchart 900 of a method for designing a Doherty amplifier according to some embodiments of the present application is schematically shown. Fig. 9 As shown, the method comprises the following steps:

[0089] In step 910, target performance indicators of the Doherty amplifier are set, and the target performance indicators include at least the operating frequency, saturation power, and dynamic range of the Doherty amplifier; in step 920, transistors for the main amplifier and the auxiliary amplifier are selected according to the target performance indicators. The selection of transistors can take into account various design requirements, such as power, cost, size, etc., and reference can be made to the description of different types of transistors above, which is not limited in the present application; in step 930, based on load-pull test or simulation analysis, first, second, and third target impedances are determined, wherein the first target impedance is the load impedance that makes the main amplifier most efficient when the Doherty amplifier is in a back-off power state, the second target impedance is the load impedance that makes the main amplifier most efficient when the output power of the main amplifier reaches the saturation power, and the third target impedance is the load impedance that makes the auxiliary amplifier most efficient when the output power of the auxiliary amplifier reaches the saturation power; in step 940, based on the first, second, and third target impedances, circuit topologies and component parameters of each sub-network in the main output network and the auxiliary output network are determined, and circuit topologies and component parameters of the combiner matching network are determined.

[0090] By using the method for designing a Doherty amplifier proposed in the embodiment of the present application, a Doherty amplifier with a more compact structure and a simplified circuit structure and design process can be obtained. In addition, the Doherty amplifier can also achieve efficient operation in the range from low power to high power, with a deeper back-off power and a wider operating bandwidth.

[0091] Fig.10 Schematically illustrates the use of some embodiments of the present application Fig. 9 An exemplary schematic diagram of the Doherty amplifier designed by the method in FIG. For simplicity, the input side structures of the main amplifier and the auxiliary amplifier are omitted. Fig.10As shown, the output network 1000 includes a main output network 1010 and an auxiliary output network 1020, the main output network 1010 includes a first sub-network 1011 and a second sub-network 1012 connected in series, and the auxiliary output network 1020 includes a third sub-network 1021, a fourth sub-network 1022, and a fifth sub-network 1023 connected in series. The combining matching network 1040 is configured so that the node impedance at the combined node 1030 is a complex impedance, and the main output network 1010 and the auxiliary output network 1020 are configured so that the node impedance is matched to the target load impedance of the main amplifier and the auxiliary amplifier. The drain DC bias voltage is fed through the DC bias circuit in the combining matching network 1040.

[0092] from Fig.10 It can be seen that the circuit topology of the first sub-network 1011 and the third sub-network 1021 adopts the circuit topology of Figure 5 The circuit topology 510 described above, the circuit topology of the second sub-network 1012, the fourth sub-network 1022 and the fifth sub-network 1023 adopts the circuit topology of Figure 6 The circuit topology 650 described above, and the combining matching network 1040 adopts the above Figure 7 The circuit topology 740 described (including the capacitor C for isolating the DC block As mentioned above, although the circuit topologies of different sub-networks may be the same, their component parameters may be different.

[0093] Fig.11 Schematically illustrates the use of other embodiments according to the present application Fig. 9 An exemplary schematic diagram of a Doherty amplifier designed by the method in FIG. 1 , in which the input side structures of the main amplifier and the auxiliary amplifier are also omitted. Fig.11 As shown, the output network 1100 includes a main output network 1110 and an auxiliary output network 1120, the main output network 1110 includes a first sub-network 1111 and a second sub-network 1112 connected in series, and the auxiliary output network 1120 includes a third sub-network 1121, a fourth sub-network 1122, and a fifth sub-network 1123 connected in series. The combining matching network 1140 is configured so that the node impedance at the combined node 1130 is a complex impedance, and the main output network 1110 and the auxiliary output network 1120 are configured so that the node impedance is matched to the target load impedance of the main amplifier and the auxiliary amplifier. The drain DC bias voltage is fed through the DC bias circuit in the combining matching network 1140.

[0094] from Fig.11 It can be seen that the circuit topology of the first sub-network 1111 and the third sub-network 1121 adopts the circuit topology of Figure 5The circuit topology 510 described above adopts the circuit topology of the second sub-network 1112, the fourth sub-network 1122 and the fifth sub-network 1123. Figure 6 The circuit topology 630 described above, and the combining matching network 1140 adopts the above Figure 7 The circuit topology 720 described (including the capacitor C for isolating the DC block As mentioned above, although the circuit topologies of different sub-networks may be the same, their component parameters may be different. Fig.11 The parameter design example of the output network 1100 is shown as follows:

[0095] The Doherty amplifier corresponding to the output network 1100 can be applied to 5G mobile communication systems (2.6 GHz frequency band, 32 T transmitter array, base station amplifier). The main amplifier is a transistor based on gallium nitride (GaN) semiconductor process with a total gate width of 4.8 mm. Its saturation power is 50 W and the parasitic capacitance C dsM The auxiliary amplifier is a transistor based on gallium nitride (GaN) semiconductor process with a total gate width of 8.4 mm. Its saturation power is 85 W and the parasitic capacitance C dsA 3 pF; L pM and L pA is the parasitic inductance, both equal to 0.1 pF; use Fig. 9 The other component parameters of each sub-network in the output network 1100 designed by the method are as follows:

[0096] L M1 =1.1 nH;

[0097] C M1 =1.53 pF;

[0098] C M2 =3.166 pF;

[0099] L A1 =0.55 nH;

[0100] C A1 =3.8 pF;

[0101] C A2 =6.46 pF;

[0102] L A2 =0.55 nH;

[0103] C A3 =6.46 pF;

[0104] C A4 =5.61 pF;

[0105] L out1 =2.1 nH;

[0106] C out1 =6 pF;

[0107] L choke =10 nH;

[0108] C block =10 pF.

[0109] The RF characteristics of the main output network 1110 in the 2.6 GHz frequency band are equivalent to a transmission line with an electrical length of 86°, and the RF characteristics of the auxiliary output network 1120 in the 2.6 GHz frequency band are equivalent to a transmission line with an electrical length of 161°.

[0110] Fig.12 and Fig.13 The performance example diagram of the Doherty amplifier according to some embodiments of the present application obtained through simulation experiments is schematically shown. Fig.12 As shown, the DC-RF conversion efficiency of the Doherty amplifier according to some embodiments of the present application and the traditional Doherty amplifier varies with the output power as shown in curves 1210 and 1220, respectively. It can be seen that under low output power conditions, the efficiency of the Doherty amplifier according to some embodiments of the present application is much higher than that of the traditional solution. Fig.13 As shown, the amplifier small signal gains of the Doherty amplifier according to some embodiments of the present application and the traditional Doherty amplifier are shown as curves 1310 and 1320 respectively. It can be seen that the bandwidth of the Doherty amplifier according to some embodiments of the present application is much larger than that of the traditional Doherty amplifier (more than twice the bandwidth of the traditional Doherty amplifier).

[0111] It will be understood that, although the first, second, third and other terms may be used to describe various devices, elements, parts or portions in this article, these devices, elements, parts or portions should not be limited by these terms. These terms are only used to distinguish one device, element, part or portion from another device, element, part or portion. The "connection" mentioned herein includes "direct connection" or "indirect connection".

[0112] Although the present application has been described in conjunction with some embodiments, it is not intended to be limited to the specific form set forth herein. On the contrary, the scope of the present application is limited only by the appended claims. Additionally, although individual features may be included in different claims, these may possibly be advantageously combined, and the inclusion in different claims does not imply that the combination of features is not feasible and / or advantageous. The order of features in the claims does not imply any specific order in which the features must work. In addition, in the claims, the word "comprising" does not exclude other elements, and the term "one" or "an" does not exclude a plurality. The figure marks in the claims are provided only as clear examples and should not be interpreted as limiting the scope of the claims in any way.

Claims

1. An output network for a Doherty amplifier, the Doherty amplifier comprising a main amplifier and an auxiliary amplifier, the output network comprising: a combining node, a main output network connected between the output end of the main amplifier and the combining node, an auxiliary output network connected between the output end of the auxiliary amplifier and the combining node, and a combining matching network connected between the combining node and the radio frequency output end of the Doherty amplifier, wherein the main output network includes a first sub-network and a second sub-network connected in series, the auxiliary output network includes a third sub-network, a fourth sub-network and a fifth sub-network connected in series, the first sub-network and the third sub-network have the same circuit topology and each includes at least an inductor and a capacitor, the fourth sub-network is connected between the third sub-network and the fifth sub-network, the second sub-network, the fourth sub-network and the fifth sub-network have the same circuit topology and each includes at least one of an inductor, a capacitor and a transmission line, wherein the combining matching network is configured such that the node impedance at the combined node is a complex impedance, and the main output network and the auxiliary output network are configured such that the node impedance is matched to the target load impedance of the main amplifier and the auxiliary amplifier, The main output network is equivalent to a first transmission line in the working frequency band, and the auxiliary output network is equivalent to a second transmission line in the working frequency band. The electrical angle θ of the first transmission line M and the electrical angle θ of the second transmission line A Satisfies: 70°<θ M <90°, and 135°<θ A <180°.

2. The output network according to claim 1, wherein the output network is configured so that the output current I M and the auxiliary amplifier output current I A Satisfaction: I M The amplitude is not greater than I A The amplitude of I M and I A The phase difference is less than 90°.

3. The output network according to claim 1, wherein the first sub-network and the third sub-network each include a first capacitor and a first inductor, one end of the first capacitor is connected to the output end of the main amplifier or the auxiliary amplifier, the other end of the first capacitor is grounded, one end of the first inductor is connected to the output end of the main amplifier or the auxiliary amplifier, and the other end of the first inductor is connected to the input end of the second sub-network or the fourth sub-network.

4. The output network according to claim 3, wherein the first sub-network and the third sub-network each further include a second capacitor and a third transmission line, the third transmission line being connected between the first inductor and a DC voltage terminal, one end of the second capacitor being connected to the DC voltage terminal, the other end of the second capacitor being grounded, and the DC voltage terminal being configured to provide a DC bias voltage to the main amplifier or the auxiliary amplifier via the third transmission line and the first inductor.

5. The output network according to claim 1, wherein the first sub-network and the third sub-network each include a second inductor, a third inductor, a third capacitor and a fourth capacitor, one end of the third capacitor is connected to the output end of the main amplifier or the auxiliary amplifier, the other end of the third capacitor is grounded, one end of the second inductor is connected to the output end of the main amplifier or the auxiliary amplifier, the other end of the second inductor and one end of the third inductor are both connected to one end of the fourth capacitor, the other end of the fourth capacitor is grounded, and the other end of the third inductor is connected to the input end of the second sub-network or the fourth sub-network.

6. The output network according to claim 1, wherein the first sub-network and the third sub-network both include a fourth inductor, a fifth inductor, a fifth capacitor and a sixth capacitor, one end of the fifth capacitor is connected to the output end of the main amplifier or the auxiliary amplifier, the other end of the fifth capacitor is grounded, one end of the fourth inductor is connected to the output end of the main amplifier or the auxiliary amplifier, the other end of the fourth inductor is connected to a DC voltage terminal, one end of the sixth capacitor is connected to the DC voltage terminal, the other end of the sixth capacitor is grounded, one end of the fifth inductor is connected to the output end of the main amplifier or the auxiliary amplifier, the other end of the fifth inductor is connected to the input end of the second sub-network or the fourth sub-network, and the DC voltage terminal is configured to provide a DC bias voltage to the main amplifier or the auxiliary amplifier via the fourth inductor.

7. The output network according to claim 1, wherein the second sub-network and the fourth sub-network each include a sixth inductor and a seventh capacitor, one end of the sixth inductor is connected to the output end of the first sub-network or the third sub-network, the other end of the sixth inductor is connected to one end of the seventh capacitor, and the other end of the seventh capacitor is grounded. 8 . The output network of claim 7 , wherein the second sub-network and the fourth sub-network each further include a seventh inductor, the seventh inductor forming a T-type circuit with the sixth inductor and the seventh capacitor. 9 . The output network of claim 7 , wherein the second sub-network and the fourth sub-network each further include an eighth capacitor, the eighth capacitor forming a π-type circuit with the sixth inductor and the seventh capacitor.

10. The output network of claim 1, wherein the second sub-network and the fourth sub-network each include a fourth transmission line. 11 . The output network of claim 10 , wherein the second sub-network and the fourth sub-network each further include a ninth capacitor connected between the fourth transmission line and ground.

12. The output network according to claim 1, wherein the combining matching network comprises an eighth inductor and a tenth capacitor, one end of the eighth inductor is connected to the combining node, the other end of the eighth inductor is connected to one end of the tenth capacitor, and the other end of the tenth capacitor is grounded.

13. The output network according to claim 12, wherein the combining matching network further comprises a ninth inductor, one end of the ninth inductor being connected between the eighth inductor and the tenth capacitor, and the other end of the ninth inductor being connected to a DC voltage terminal, and the DC voltage terminal being configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the ninth inductor, the eighth inductor, the main output network and the auxiliary output network.

14. The output network according to claim 1, wherein the combining matching network comprises a fifth transmission line, a sixth transmission line and an eleventh capacitor, one end of the fifth transmission line is connected to the combining node, the other end of the fifth transmission line is connected to one end of the sixth transmission line, the other end of the sixth transmission line is connected to the RF output end of the Doherty amplifier, one end of the eleventh capacitor is connected between the fifth transmission line and the sixth transmission line, and the other end of the eleventh capacitor is grounded.

15. The output network according to claim 1, wherein the combiner matching network comprises a seventh transmission line, an eighth transmission line, a ninth transmission line and a twelfth capacitor, one end of the seventh transmission line is connected to the combination node, the other end of the seventh transmission line is connected to one end of the eighth transmission line, the other end of the eighth transmission line is connected to a DC voltage terminal, one end of the twelfth capacitor is connected to the DC voltage terminal, the other end of the twelfth capacitor is grounded, one end of the ninth transmission line is connected between the seventh transmission line and the eighth transmission line, the other end of the ninth transmission line is connected to the RF output terminal of the Doherty amplifier, and the DC voltage terminal is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the eighth transmission line, the seventh transmission line, the main output network and the auxiliary output network.

16. The output network according to any one of claims 3 to 15, wherein at least one of the first to twelfth capacitors can be implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device, and wherein, At least one of the first to ninth inductors may be implemented in at least one of the following forms: a PCB surface-mount component, an integrated circuit device, a bonding wire, a microstrip line, a metal winding, and a transmission line.

17. The output network according to any one of claims 4, 10, 14, and 15, wherein at least one of the third to ninth transmission lines can be implemented in at least one of the following forms: microstrip line, stripline, coplanar waveguide, substrate integrated waveguide.

18. A Doherty amplifier, comprising: Main amplifier; Auxiliary amplifier; as well as The output network according to any one of claims 1 to 17, The output network is configured to receive a first amplified signal output by the main amplifier and a second amplified signal output by the auxiliary amplifier, so that the first amplified signal and the second amplified signal are combined at the combination node to be provided to a radio frequency output terminal of the Doherty amplifier.

19. A method for designing a Doherty amplifier, the Doherty amplifier comprising a main amplifier, an auxiliary amplifier, and an output network as claimed in claim 1, wherein the method comprises: Setting target performance indicators of the Doherty amplifier, wherein the target performance indicators at least include an operating frequency, a saturated power, and a dynamic range of the Doherty amplifier; Selecting transistors for the main amplifier and the auxiliary amplifier according to the target performance indicator; Based on a load-pull test or simulation analysis, determining a first, second, and third target impedances, wherein the first target impedance is a load impedance that makes the main amplifier most efficient when the Doherty amplifier is in a back-off power state, the second target impedance is a load impedance that makes the main amplifier most efficient when the output power of the main amplifier reaches a saturation power, and the third target impedance is a load impedance that makes the auxiliary amplifier most efficient when the output power of the auxiliary amplifier reaches a saturation power; Based on the first, second and third target impedances, the circuit topology and component parameters of each sub-network in the main output network and the auxiliary output network are determined, and the circuit topology and component parameters of the combiner matching network are determined.

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