Control chips, smart electronic switches and automobiles

Abstract

The present application provides a control chip, an intelligent electronic switch and an automobile. The control chip includes a power supply pin, a power ground pin, an enable pin, a drive pin, a turn-on time setting pin, a turn-off time setting pin and a drive circuit. In addition to being internally connected to the drive circuit, the turn-on time setting pin and the turn-off time setting pin are also used to be externally connected to a first resistor, and the turn-off time setting pin is also used to be externally connected to a second resistor. The first resistor is used to set a turn-on current flowing through the drive pin, and the second resistor is used to set a turn-off current flowing through the drive pin. Different first resistors correspond to different turn-on currents, and different second resistors correspond to different turn-off currents, so that the turn-on speed of the power switch is determined by the turn-on current, and the turn-off speed of the power switch is determined by the turn-off current, thereby realizing the control of the turn-on speed and the turn-off speed of the power switch, and ensuring that the turn-on speed and the turn-off speed of the power switch can meet the requirements.

Description

Technical Field

[0001] The present application relates to the technical field of intelligent semiconductor switches, and in particular to a control chip, an intelligent electronic switch and a car. Background Art

[0002] Intelligent electronic switches are usually used to couple loads with batteries. They are electronic components that control the on and off of load lines and are widely used in automotive electronics, industrial automation, medical equipment, and other fields. Due to the variety of load types connected and the harsh working environment, in practical applications, there are strict requirements on the opening and closing speed of the power switch in the intelligent electronic switch.

[0003] In the prior art, the power switch of the intelligent electronic switch is usually built into a control chip. In this case, the driving circuit in the control chip drives the power switch to turn on or off with a fixed driving capability (eg, maximum driving capability).

[0004] However, in order to improve the versatility of control chips, the application of power switches external to control chips is becoming more and more widespread. However, when the control chip is matched with different power switches, the turn-on speed or turn-off speed of the power switch may not meet the requirements due to the different input capacitance of the power switch. Summary of the invention

[0005] The present application provides a control chip, an intelligent electronic switch and a car, which are used to solve the problem that the opening or closing speed of a power switch in the intelligent electronic switch cannot meet the requirements.

[0006] In a first aspect, the present application provides a control chip of a power switch, which is used to control the on-off or off-off of the power switch, wherein the control chip includes a power supply pin, a power ground pin, an enable pin, a drive pin, an on-time setting pin, an off-time setting pin, and a drive circuit;

[0007] The power supply pin and the power ground pin are used to connect to a battery, the drive circuit is connected to the on-time setting pin, the off-time setting pin, the enable pin and the drive pin respectively, the on-time setting pin is also used to connect to a first resistor, the off-time setting pin is also used to connect to a second resistor, and the drive pin is also used to connect to a control end of a power switch; the first resistor is used to set a turn-on current flowing through the drive pin, and the second resistor is used to set a turn-off current flowing through the drive pin. Different first resistors correspond to different turn-on currents, and different second resistors correspond to different turn-off currents;

[0008] When the enable pin receives a first signal, the drive circuit controls the power switch to turn on, and the turn-on speed of the power switch is determined by the turn-on current; when the enable pin receives a second signal, the drive circuit controls the power switch to turn off, and the turn-off speed of the power switch is determined by the turn-off current.

[0009] In a possible design of the first aspect, the driving circuit includes a first control unit and a second control unit;

[0010] The first control unit is connected to the turn-on time setting pin, the enable pin and the drive pin respectively. When the enable pin receives a first signal, the first control unit generates a turn-on current according to the first resistor and flows through the drive pin. The larger the turn-on current, the faster the turn-on speed of the power switch and the shorter the time required for the power switch to be fully turned on.

[0011] The second control unit is respectively connected to the turn-off time setting pin, the enable pin and the drive pin. When the enable pin receives a second signal, the second control unit generates a turn-off current according to the second resistor that flows through the drive pin. The larger the turn-off current, the faster the power switch is disconnected and the shorter the time required for the power switch to be completely turned off.

[0012] Optionally, the first control unit includes a first operational amplifier unit, a first NMOS tube and a first conversion unit;

[0013] The first input end of the first operational amplifier unit is used to access the first reference voltage, the second input end thereof is connected to the start-up time setting pin and the second end of the first NMOS transistor, the output end thereof is connected to the control end of the first NMOS transistor, the first end of the first NMOS transistor is connected to the first conversion unit, and the first conversion unit is also connected to the driving pin;

[0014] The first operational amplifier unit is used to generate a control signal for turning on the first NMOS tube based on the first reference voltage and the first resistor connected to the turn-on time setting pin. The output current of the first NMOS tube is determined based on the first reference voltage and the first resistor. The first conversion unit is used to convert the output current of the first NMOS tube into the turn-on current. The smaller the first resistor is, the larger the output current of the first NMOS tube is, and the corresponding turn-on current is larger.

[0015] Optionally, the start-up current flows through the drive pin when the enable pin receives a first signal to control a start-up speed of the power switch;

[0016] The first conversion unit includes a first-first PMOS tube, a first-second PMOS tube, a first-second NMOS tube, a first-third NMOS tube, a first-third PMOS tube and a first-fourth PMOS tube;

[0017] The first PMOS tube and the first NMOS tube are connected in series, the control end of the first PMOS tube is connected to the control end of the first second PMOS tube, the first PMOS tube and the first second PMOS tube are also connected to the first power supply end, the first second PMOS tube and the first second NMOS tube are connected in series, the control end of the first second NMOS tube is connected to the control end of the first third NMOS tube, the first second NMOS tube and the first third NMOS tube are also connected to the power ground pin, the first third NMOS tube and the first third PMOS tube are connected in series, the control end of the first third PMOS tube is connected to the control end of the first fourth PMOS tube, the first third PMOS tube and the first fourth PMOS tube are also connected to the second power supply end, and the first fourth PMOS tube is also connected to the driving pin;

[0018] The output current of the first PMOS tube is equal to the output current of the first NMOS tube, the first mirror current of the first second PMOS tube is mirrored to the output current of the first PMOS tube, the output current of the first second NMOS tube is equal to the first mirror current of the first second PMOS tube, the second mirror current of the first third NMOS tube is mirrored to the output current of the first second NMOS tube, the output current of the first third PMOS tube is equal to the second mirror current of the first third NMOS tube, the third mirror current of the first fourth PMOS tube is mirrored to the output current of the first third PMOS tube, and the start-up current is equal to the third mirror current.

[0019] In another possible design of the first aspect, the second control unit includes a second operational amplifier unit, a second NMOS transistor and a second conversion unit;

[0020] The first input end of the second operational amplifier unit is used to access the second reference voltage, the second input end thereof is connected to the off-time setting pin and the second end of the second-NMOS tube, the output end thereof is connected to the control end of the second-NMOS tube, the first end of the second-NMOS tube is connected to the second conversion unit, and the second conversion unit is also connected to the driving pin;

[0021] The second operational amplifier unit is used to generate a control signal for turning on the second-to-NMOS tube based on the second reference voltage and the second resistor connected to the shutdown time setting pin. The output current of the second-to-NMOS tube is determined based on the second reference voltage and the second resistor. The second conversion unit is used to convert the output current of the second-to-NMOS tube into the shutdown current. The smaller the second resistor is, the larger the output current of the second-to-NMOS tube is, and the corresponding shutdown current is larger.

[0022] Optionally, the shutdown current flows through the drive pin when the enable pin receives a second signal to control a shutdown speed of the power switch;

[0023] The second conversion unit includes a second-first PMOS tube, a second-second PMOS tube, a second-second NMOS tube, a second-third NMOS tube, a second-third PMOS tube, a second-fourth PMOS tube, a second-fourth NMOS tube and a second-fifth NMOS tube;

[0024] The second-first PMOS tube and the second-first NMOS tube are connected in series, the control end of the second-first PMOS tube is connected to the control end of the second-second PMOS tube, the second-first PMOS tube and the second-second PMOS tube are also connected to the first power supply end, the second-second PMOS tube and the second-second NMOS tube are connected in series, the control end of the second-second NMOS tube is connected to the control end of the second-third NMOS tube, the second-second NMOS tube and the second-third NMOS tube are also connected to the power ground pin, the second-third NMOS tube and the second-third PMOS tube are connected in series, the control end of the second-third PMOS tube is connected to the control end of the second-fourth PMOS tube, the second-third PMOS tube and the second-fourth PMOS tube are also connected to the second power supply end, the second-fourth PMOS tube and the second-fourth NMOS tube are connected in series, the control end of the second-fourth NMOS tube is connected to the control end of the second-fifth NMOS tube, the second-fourth NMOS tube and the second-fifth NMOS tube are also connected to the second end of the power switch, and the second-fifth NMOS tube is also connected to the driving pin;

[0025] The output current of the second-first PMOS tube is equal to the output current of the second-first NMOS tube, the fourth mirror current of the second-second PMOS tube is mirrored with the output current of the second-first PMOS tube, the output current of the second-second NMOS tube is equal to the fourth mirror current of the second-second PMOS tube, the fifth mirror current of the second-third NMOS tube is mirrored with the output current of the second-second NMOS tube, the output current of the second-third PMOS tube is equal to the fifth mirror current of the second-third NMOS tube, the sixth mirror current of the second-fourth PMOS tube is mirrored with the output current of the second-third PMOS tube, the output current of the second-fourth NMOS tube is equal to the sixth mirror current of the second-fourth PMOS tube, the seventh mirror current of the second-fifth NMOS tube is mirrored with the output current of the second-fourth NMOS tube, and the shutdown current is equal to the seventh mirror current.

[0026] In a second aspect, the present application provides an intelligent electronic switch, including a control chip, a power supply terminal, a power ground terminal, a load output terminal, and a power switch as described in the first aspect and possible designs thereof;

[0027] The power supply end and the power ground end are used to be connected to a battery, the control end of the power switch is connected to a drive pin of the control chip, the first end of the power switch is connected to the power supply end or the power ground end, the second end of the power switch is connected to a load output end, and the load output end is used to be connected to a load; the control chip is used to control the power switch to be turned on or off.

[0028] Optionally, the power switch is any one of an NMOS tube, a PMOS tube, and a JFET, and / or the power switch is implemented as a silicon device, silicon carbide, gallium arsenide, or gallium nitride.

[0029] Optionally, the power switch is located on a first chip other than the control chip;

[0030] Among them, the power supply end is a power supply pin, the power ground end is a power ground pin, the load output end is a load output pin, and the load output pin is located on the first chip.

[0031] In a third aspect, an embodiment of the present application provides a car, comprising the control chip as described in the first aspect and its possible design, or the intelligent electronic switch as described in the second aspect;

[0032] It also includes a battery, a first resistor, a second resistor, a load and a microprocessor, wherein the positive and negative electrodes of the battery are connected to the power supply pin and the power ground pin of the control chip respectively, the first resistor is connected to the turn-on time setting pin of the control chip, the second resistor is connected to the turn-off time setting pin of the control chip, the load is connected to the power switch, and the microprocessor is connected to the control chip.

[0033] Optionally, the vehicle is an electric vehicle, a hybrid vehicle or a fuel vehicle, and the load includes at least one of a resistive load, an inductive load and a capacitive load.

[0034] The control chip, intelligent electronic switch and automobile provided in the present application include a power supply pin, a power ground pin, an enable pin, a drive pin, a turn-on time setting pin, a turn-off time setting pin and a drive circuit. In addition to the internal drive circuit, the turn-on time setting pin and the turn-off time setting pin are also used to externally connect a first resistor, and the turn-off time setting pin is also used to externally connect a second resistor. The first resistor is used to set the turn-on current flowing through the drive pin, and the second resistor is used to set the turn-off current flowing through the drive pin. Different first resistors correspond to different turn-on currents, and different second resistors correspond to different turn-off currents, so that the turn-on speed of the power switch is determined by the turn-on current, and the turn-off speed of the power switch is determined by the turn-on current, thereby realizing the control of the turn-on speed and the turn-off speed of the power switch, and ensuring that the turn-on speed and the turn-off speed of the power switch can meet the requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0036] Figure 1 This is a schematic diagram of a circuit module of a control chip and its peripheral components provided in the first embodiment of the present application;

[0037] Figure 2 This is a circuit module schematic diagram of a control chip and its peripheral components provided in the second embodiment of the present application;

[0038] Figure 3 This is a schematic diagram of a circuit module of a control chip and its peripheral components provided in the third embodiment of the present application;

[0039] Figure 4 This is a circuit module diagram of a control chip and its peripheral components provided in the fourth embodiment of the present application;

[0040] Figure 5This is a circuit module diagram of a control chip and its peripheral components provided in the fifth embodiment of the present application.

[0041] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] The terms "including" and "having" and any variations thereof appearing in the specification, claims and drawings of this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or modules is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0044] In addition, the terms "first", "second" and "third" are used to distinguish different objects, rather than to describe a specific order. The electrical connection of the present application includes direct electrical connection and indirect electrical connection. Indirect electrical connection means that other electronic components, pins, etc. may exist between the two electrically connected components. The XX end mentioned in the present application may be an actual terminal, or it may not be an actual terminal, for example, it is only one end of a component or one end of a wire. The "and / or" mentioned in the present application includes three situations. For example, A and / or B includes three situations: A, B, A and B.

[0045] In recent years, with the rapid growth of the automobile market, especially the explosion of the electric vehicle market, such as the electric passenger car market and the electric commercial vehicle market, the demand for automotive electronic components has increased. The most demanded electronic component in automobiles is the relay, which is used to turn on or off a load line. However, the relay itself has some disadvantages, such as long delay time for opening and closing, and the relay itself is expensive and large in size. Therefore, with the development of semiconductor technology, intelligent electronic switches have been successfully developed to replace traditional relays. Intelligent electronic switches usually include a power switch and a drive circuit for driving the power switch. The drive circuit usually controls the opening and closing of the power switch with a fixed drive capability.

[0046] In the related art, as the application of power switches and drive circuits being deployed separately is becoming more and more widespread, a drive circuit can be used to match different power switches to improve the versatility of the drive circuit. However, since different power switches have different input capacitances, when the drive circuit drives different power switches with the same drive capability, the turn-on speed and turn-off speed of different power switches may be different, resulting in the turn-on speed and / or turn-off speed of some power switches failing to meet the requirements. For example, the intelligent electronic switch cannot pass the electromagnetic compatibility (EMC) test during system testing, such as the electromagnetic interference (EMI) test or the electromagnetic tolerance (EMS) test.

[0047] In response to the above technical problems, the inventors of this application have proposed a technical concept after long-term research. When the driving circuit and the power switch are deployed on different chips, if the driving circuit can provide corresponding driving capabilities based on the needs of different power switches, the turn-on speed and turn-off speed of the power switch can be controlled to ensure that the turn-on speed and turn-off speed of the power switch can meet the requirements.

[0048] Based on the above technical concept, an embodiment of the present application provides a control chip, which may include a power supply pin, a power ground pin, an enable pin, a drive pin, a turn-on time setting pin, a turn-off time setting pin and a drive circuit. In addition to the internal drive circuit, the turn-on time setting pin and the turn-off time setting pin are also used to externally connect a first resistor, and the turn-off time setting pin is also used to externally connect a second resistor. The first resistor is used to set the turn-on current flowing through the drive pin, and the second resistor is used to set the turn-off current flowing through the drive pin. Different first resistors have different corresponding turn-on currents, and different second resistors have different corresponding turn-off currents, so that the turn-on speed of the power switch is determined by the turn-on current, and the turn-off speed of the power switch is determined by the turn-on current, thereby realizing the control of the turn-on speed and the turn-off speed of the power switch, and ensuring that the turn-on speed and the turn-off speed of the power switch can meet the requirements.

[0049] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0050] The first embodiment of the present application provides a control chip for a power switch, which is used to control the power switch to be turned on or turned off. For example, Figure 1 1 is a schematic diagram of a circuit module of a control chip and its peripheral components provided in the first embodiment of the present application. Figure 1 As shown, the control chip 20 includes a power supply pin VCC, a power ground pin GND, an enable pin EN, a drive pin GATE, a turn-on time setting pin RTon, a turn-off time setting pin RToff and a drive circuit 200 .

[0051] Among them, the power supply pin VCC and the power ground pin GND are used to connect to the battery 10, and the drive circuit 200 is respectively connected to the on-time setting pin RTon, the off-time setting pin RToff, the enable pin EN and the drive pin GATE. The on-time setting pin RTon is also used to connect to the first resistor R1, the off-time setting pin RToff is also used to connect to the second resistor R2, and the drive pin GATE is also used to connect to the control end of the power switch Q1; the first resistor R1 is used to set the on-current Ion flowing through the drive pin GATE, and the second resistor R2 is used to set the off-current Ioff flowing through the drive pin GATE. Different first resistors R1 have different corresponding on-currents Ion, and different second resistors R2 have different corresponding off-currents Ioff.

[0052] In this embodiment, when the enable pin EN receives a first signal, the drive circuit 200 controls the power switch Q1 to turn on, and the turn-on speed of the power switch Q1 is determined by the turn-on current Ion; when the enable pin EN receives a second signal, the drive circuit 200 controls the power switch Q1 to turn off, and the turn-off speed of the power switch Q1 is determined by the turn-off current Ioff.

[0053] Optional, in Figure 1 In the embodiment, the power supply pin VCC is electrically connected to the positive electrode of the battery 10, and the power ground pin GND is electrically connected to the negative electrode of the battery 10. The battery 10 is used to supply power to the control chip 20 to ensure that the control chip 20 can work normally.

[0054] In this embodiment, the drive circuit 200 is connected to the control end of the power switch Q1 through the drive pin GATE, so that the drive circuit 200 can control the power switch Q1 to turn on or turn off based on the input signal received by the enable pin EN. It can be understood that the embodiment of the present application is explained by the state change of the drive circuit 200 controlling the power switch Q1, that is, the power switch Q1 can be changed from the off state to the on state, and can also be changed from the on state to the off state. Of course, when the input signal received by the enable pin EN is the first signal, the drive circuit 200 can also control the power switch Q1 to maintain in the on state, and when the input signal received by the enable pin EN is the second signal, the drive circuit 200 can also control the power switch Q1 to maintain in the off state, and this embodiment does not limit it.

[0055] Optionally, in this embodiment, the control chip 20 is additionally provided with an on-time setting pin RTon and an off-time setting pin RToff, wherein the on-time setting pin RTon is used to connect the first resistor R1, and the off-time setting pin RToff is used to connect the second resistor R2. By designing the circuit structure of the driving circuit 200, a relationship between the first resistor R1 and the on-current Ion flowing through the driving pin GATE can be established, and a relationship between the second resistor R2 and the off-current Ioff flowing through the driving pin GATE can also be established. The specific relationship between the on-current Ion and the first resistor R1, and the specific relationship between the off-current Ioff and the second resistor R2 can be referred to the records in the following embodiments, which will not be repeated here.

[0056] In the embodiment of the present application, the first resistor R1 is used to set the on-current Ion flowing through the driving pin GATE when the power switch Q1 is turned on, that is, the turn-on speed of the power switch Q1 is determined by the on-current Ion. At the same time, the second resistor R2 is used to set the off-current Ioff flowing through the driving pin GATE when the power switch Q1 is turned off, that is, the turn-off speed of the power switch Q1 is determined by the off-current Ioff.

[0057] Understandable, Figure 1 The illustrated embodiment is explained with the power switch Q1 connected as a high-side switch (high-side switch), that is, the power switch Q1 is connected between the positive electrode of the battery 10 and the load R0. In other embodiments of the present application, the power switch Q1 can also be connected as a low-side switch (low-side switch), that is, the power switch Q1 is connected between the negative electrode of the battery 10 and the load R0, which will not be described in detail here.

[0058] Optionally, in this embodiment, the power switch Q1 can be an N-type metal-oxide-semiconductor field-effect transistor (N Metal-Oxide-SemiconductorField-Effect Transistor, NMOS FET, referred to as NMOS tube), a PMOS tube, a junction field effect transistor (Junction Field Effect Transistor, referred to as JFET) or an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, referred to as IGBT), etc., and the N-type MOS tube is used as an example for illustration in the figure. In another possible design of this embodiment, the power switch Q1 can also be implemented as a silicon device, or can be implemented using other semiconductor materials, such as silicon carbide (SiC), gallium arsenide (GaAs) or gallium nitride (GaN), etc. The embodiment of the present application does not limit the form of expression of the power switch Q1.

[0059] In an embodiment of the present application, the control chip includes a power supply pin, a power ground pin, an enable pin, a drive pin, a turn-on time setting pin, a turn-off time setting pin and a drive circuit. The turn-on time setting pin is also used to connect to a first resistor, and the turn-off time setting pin is also used to connect to a second resistor. The first resistor is used to set a turn-on current flowing through the drive pin, and the second resistor is used to set a turn-off current flowing through the drive pin. Different first resistors have different corresponding turn-on currents, and different second resistors have different corresponding turn-off currents, so that the turn-on speed of the power switch is determined by the turn-on current, and the turn-off speed of the power switch is determined by the turn-off current, thereby realizing the control of the turn-on speed and the turn-off speed of the power switch, and ensuring that the turn-on speed and the turn-off speed of the power switch can meet the requirements.

[0060] Optionally, a fuse (not shown) may be connected in series between the battery 10 and the power supply pin VCC to prevent a fault caused by excessive current in the line. Other components may also be provided between the power ground pin GND and the negative electrode of the battery 10, for example, a reverse connection prevention diode and a current limiting resistor connected in parallel to improve the stability of the intelligent electronic switch.

[0061] Optional, in Figure 1 In the schematic diagram shown, the connection relationship between the drive circuit 200 and the power supply unit is not shown, but in actual application, a power supply unit can be set inside the control chip 20, and the internal power supply unit is connected to the power supply pin VCC to step down the voltage of the power supply pin VCC and provide it to the drive circuit 200 or other circuits. In other embodiments, the control chip 20 may not be provided with a power supply unit inside. In this case, a step-down unit needs to be provided between the power supply pin VCC and the positive electrode of the battery 10 to reduce the voltage input to the power supply terminal to the rated working voltage of the control chip 20, so that the voltage at the power supply pin VCC can directly power the circuit inside the control chip 20, and the embodiment of the present application does not limit it.

[0062] The above embodiment generally introduces the control chip 20. The following will explain the specific implementation of the drive circuit 200 through different embodiments. Figure 1 The illustrated embodiment is used as a basis for explaining the principle.

[0063] For example, Figure 2 Schematic diagram of a circuit module of a control chip and its peripheral components provided in the second embodiment of the present application. Figure 2 As shown, in this embodiment, the driving circuit 200 includes a first control unit 201 and a second control unit 202 .

[0064] Among them, the first control unit 201 is respectively connected to the turn-on time setting pin RTon, the enable pin EN and the driving pin GATE. When the enable pin EN receives the first signal, the first control unit 201 generates a turn-on current Ion through the driving pin GATE according to the first resistor R1. The larger the turn-on current Ion, the faster the turn-on speed of the power switch Q1 and the shorter the time required for the power switch Q1 to be fully turned on.

[0065] Correspondingly, the second control unit 202 is respectively connected to the off-time setting pin RToff, the enable pin EN and the driving pin GATE. When the enable pin EN receives the second signal, the second control unit 202 generates an off-current Ioff through the driving pin GATE according to the second resistor R2. The larger the off-current Ioff, the faster the power switch Q1 is turned off and the shorter the time required for the power switch Q1 to be completely turned off.

[0066] In an embodiment of the present application, the first control unit 201 can generate a turn-on current Ion according to the first resistor R1. When the input signal received by the enable pin EN is the first signal, the turn-on current Ion flows through the drive pin GATE, thereby controlling the turn-on speed of the power switch Q1. For example, when the power switch Q1 is connected as a high-side switch and the power switch Q1 is an NMOS tube, the larger the turn-on current Ion is, the faster the charging speed of the input capacitor of the power switch Q1 by the turn-on current Ion is, so that the voltage between the gate and the source increases faster, and the turn-on threshold voltage of the power switch Q1 can be reached quickly, so that the turn-on speed of the power switch Q1 is faster and the time required for the power switch Q1 to be fully turned on is shorter.

[0067] Correspondingly, the second control unit 202 can generate a turn-off current Ioff according to the second resistor R2. When the input signal received by the enable pin EN is the second signal, the turn-off current Ioff flows through the drive pin GATE, thereby controlling the turn-off speed of the power switch Q1. For example, when the power switch Q1 is connected as a high-side switch and the power switch Q1 is an NMOS tube, the larger the turn-off current Ioff is, the faster the discharge speed of the turn-off current Ioff for the input capacitor of the power switch Q1 is, so that the voltage between the gate and the source of the power switch Q1 drops faster, and can quickly drop from the voltage when it is fully turned on (for example, the battery voltage) to the turn-on threshold voltage of the power switch Q1, so that the turn-off speed of the power switch Q1 is faster and the time required for the power switch Q1 to be completely turned off is shorter.

[0068] Optionally, the following Figure 3 Shown Figure 2 The specific implementation of the first control unit 201 and the second control unit 202 is limited. Figure 3 Schematic diagram of a circuit module of a control chip and its peripheral components provided in the third embodiment of the present application. Figure 3 As shown, in the control chip 20 , the first control unit 201 includes a first operational amplifier unit DP1 , a first NMOS transistor N11 and a first conversion unit 2010 .

[0069] Among them, the first input end of the first operational amplifier unit DP1 is used to access the first reference voltage Vref1, the second input end thereof is connected to the turn-on time setting pin RTon and the second end of the first NMOS tube N11, the output end thereof is connected to the control end of the first NMOS tube N11, the first end of the first NMOS tube N11 is connected to the first conversion unit 2010, and the first conversion unit 2010 is also connected to the driving pin GATE.

[0070] In this embodiment, the first operational amplifier unit DP1 is used to generate a control signal for turning on the first NMOS tube N11 based on the first reference voltage Vref1 and the first resistor R1 connected to the turn-on time setting pin RTon. The output current of the first NMOS tube N11 is determined based on the first reference voltage Vref1 and the first resistor R1. The first conversion unit 2010 is used to convert the output current of the first NMOS tube N11 into the turn-on current Ion. The smaller the first resistor R1 is, the larger the output current of the first NMOS tube N11 is, and the corresponding turn-on current Ion is larger.

[0071] For example, refer to Figure 3 As shown, the first input end of the first operational amplifier unit DP1 is a non-phase end, and the second input end thereof is an inverting end, and the inverting end is connected to the turn-on time setting pin RTon and the second end of the first NMOS tube N11, and the turn-on time setting pin RTon is used to be connected to the first resistor R1, and the output current of the first NMOS tube N11 can be determined according to the first resistor R1 and the first reference voltage Vref1. For example, the output current i11 of the first NMOS tube N11 is equal to the ratio of the first reference voltage Vref1 to the first resistor R1, that is, i11=Vref1 / R1.

[0072] In an embodiment of the present application, the first NMOS transistor N11 operates in a saturation region. At this time, if the voltage at the non-phase terminal of the first operational amplifier unit DP1 is greater than the voltage at the inverting terminal, the first operational amplifier unit DP1 will output a high-level control signal, so that the first NMOS transistor N11 is turned on or is in a conducting state. Moreover, since the first reference voltage Vref1 remains unchanged, the smaller the first resistor R1 is, the greater the output current of the first NMOS transistor N11 is, and accordingly, the greater the turn-on current Ion processed by the first conversion unit 2010 is.

[0073] In other embodiments of the present application, the first NMOS tube N11 can also be replaced by a PMOS tube. In this case, the first input end of the first operational amplifier unit DP1 can be an inverting end, and the second input end can be a non-inverting end. The turn-on current flowing through the drive pin GATE can also be changed by adjusting the first resistor R1, which will not be elaborated here.

[0074] Similarly, continue to see Figure 3 As shown, in the control chip 20 , the second control unit 202 includes a second operational amplifier unit DP2 , a second NMOS transistor N21 and a second conversion unit 2020 .

[0075] Among them, the first input end of the second operational amplifier unit DP2 is used to access the second reference voltage Vref2, and its second input end is simultaneously connected to the off-time setting pin RToff and the second end of the second NMOS tube N21, and its output end is connected to the control end of the second NMOS tube N21, and the first end of the second NMOS tube N21 is connected to the second conversion unit 2020, and the second conversion unit 2020 is also connected to the driving pin GATE.

[0076] In this embodiment, the second operational amplifier unit DP2 is used to generate a control signal for turning on the second-NMOS tube N21 based on the second reference voltage Vref2 and the second resistor R2 connected to the off-time setting pin RToff. The output current of the second-NMOS tube N21 is determined based on the second reference voltage Vref2 and the second resistor R2. The second conversion unit 2020 is used to convert the output current of the second-NMOS tube N21 into the off-current Ioff. The smaller the second resistor R2, the larger the output current of the second-NMOS tube N21, and the larger the corresponding off-current Ioff.

[0077] For example, refer to Figure 3 As shown, the first input end of the second operational amplifier unit DP2 is a non-phase end, and the second input end thereof is an inverting end, and the inverting end is connected to the off-time setting pin RToff and the second end of the second-NMOS tube N21, and the off-time setting pin RToff is used to be connected to the second resistor R2, and the output current of the second-NMOS tube N21 can be determined according to the second resistor R2 and the second reference voltage Vref2. For example, the output current i21 of the second-NMOS tube N21 is equal to the ratio of the second reference voltage Vref2 to the second resistor R2, that is, i21=Vref2 / R2.

[0078] In an embodiment of the present application, the second NMOS tube N21 operates in a saturation region. At this time, if the voltage at the positive terminal of the second operational amplifier unit DP2 is greater than the voltage at the negative terminal, the second operational amplifier unit DP2 will output a high-level control signal, so that the second NMOS tube N21 is turned on or is in an on state. Moreover, since the second reference voltage Vref2 remains unchanged, the smaller the second resistor R2 is, the greater the output current of the second NMOS tube N21 is, and accordingly, the greater the off current Ioff after being processed by the second conversion unit 2020 is.

[0079] Similarly, the second NMOS tube N21 can also be replaced by a PMOS tube. In this case, the first input end of the second operational amplifier unit DP2 can be an inverting end, and the second input end can be a non-inverting end. The shutdown current flowing through the drive pin GATE can also be changed by adjusting the second resistor R2, which will not be elaborated here.

[0080] It is understandable that in practical applications, the first reference voltage Vref1 and the second reference voltage Vref2 may be the same or different, and may be set according to actual needs, which will not be elaborated herein.

[0081] exist Figure 3 Based on the embodiment shown, the following Figure 4 The illustrated embodiment describes how the first resistor R1 affects the turn-on speed of the power switch Q1 .

[0082] Figure 4 Schematic diagram of a circuit module of a control chip and its peripheral components provided in the fourth embodiment of the present application. Figure 4 As shown, in this example, when the enable pin EN receives the first signal, the turn-on current Ion flows through the drive pin GATE to control the turn-on speed of the power switch Q1.

[0083] Continue to see Figure 4 As shown, in the control chip 20, the first conversion unit 2010 includes a first-first PMOS transistor P11, a first-second PMOS transistor P12, a first-second NMOS transistor N12, a first-third NMOS transistor N13, a first-third PMOS transistor P13 and a first-fourth PMOS transistor P14.

[0084] Among them, the first PMOS tube P11 and the first NMOS tube N11 are connected in series, the control end of the first PMOS tube P11 is connected to the control end of the first second PMOS tube P12, the first PMOS tube P11 and the first second PMOS tube P12 are also connected to the first power supply end, the first second PMOS tube P12 and the first second NMOS tube N12 are connected in series, the control end of the first second NMOS tube N12 is connected to the control end of the first third NMOS tube N13, the first second NMOS tube N12 and the first third NMOS tube N13 are also connected to the power ground pin GND, the first third NMOS tube N13 and the first third PMOS tube P13 are connected in series, the control end of the first third PMOS tube P13 is connected to the control end of the first fourth PMOS tube P14, the first third PMOS tube P13 and the first fourth PMOS tube P14 are also connected to the second power supply end, and the first fourth PMOS tube P14 is also connected to the driving pin GATE.

[0085] In this embodiment, based on Figure 4In the circuit connection relationship shown, the output current of the first-PMOS tube P11 is equal to the output current of the first-NMOS tube N11, the first mirror current of the first-second PMOS tube P12 is mirrored with the output current of the first-PMOS tube P11, the output current of the first-second NMOS tube N12 is equal to the first mirror current of the first-second PMOS tube P12, the second mirror current of the first-third NMOS tube N13 is mirrored with the output current of the first-second NMOS tube N12, the output current of the first-third PMOS tube P13 is equal to the second mirror current of the first-third NMOS tube N13, the third mirror current of the first-fourth PMOS tube P14 is mirrored with the output current of the first-three PMOS tube P13, and the turn-on current Ion is equal to the third mirror current.

[0086] Optionally, in this embodiment, the first power supply terminal is a power supply terminal inside the control chip, and the voltage of the first power supply terminal is usually less than the voltage of the power supply terminal VCC. When the power switch Q1 is an NMOS tube and is connected as a high-side switch, the second power supply terminal connected to the first three PMOS tubes P13 and the first four PMOS tubes P14 is the output terminal of the boost circuit (not shown in the figure), and the input terminal of the boost circuit can be the power supply pin VCC. The main function of the boost circuit is to enhance the driving ability of the drive circuit and increase the voltage at the drive pin GATE so that the power switch Q1 can be turned on. For example, the boost circuit is described with a charge pump (CP) circuit. Figure 4 In the example, the second power supply terminal is identified by CP.

[0087] It can be understood that in other embodiments of the present application, when the power switch Q1 is a PMOS tube or the power switch Q1 is an NMOS tube and is connected as a low-side switch, the second power supply terminal can be an internal power supply terminal with the same potential as the power supply pin VCC, which is not elaborated here.

[0088] In a possible design, it is assumed that the ratio of the output current i11 of the first-first PMOS tube P11 to the first mirror current i12 of the first-second PMOS tube P12 is 1:k11, the ratio of the output current i12 of the first-second NMOS tube N12 to the second mirror current i13 of the first-third NMOS tube N13 is 1:k12, and the ratio of the output current i13 of the first-third PMOS tube P13 to the third mirror current i14 of the first-fourth PMOS tube P14 is 1:k13. In this way, if the output current of the first-first NMOS tube N11 is i11, the third mirror current i14 of the first-fourth PMOS tube P14 is equal to k11*k12*k13*Vref1 / R1. Therefore, when the enable pin EN receives the first signal, the turn-on current Ion flowing through the drive pin GATE = k11*k12*k13*Vref1 / R1, so that by replacing the first resistor R1 or adjusting the resistance value of the first resistor R1, the turn-on current Ion flowing through the drive pin GATE can be changed, thereby controlling the turn-on speed of the power switch Q1. Among them, k11, k12, k13, etc. can be set according to actual needs, and will not be described in detail here.

[0089] Optionally, in this embodiment, the start switch may include a switch M1 connected to the output end of the first conversion unit 2010, or may include at least one switch connected inside the first conversion unit 2010, for example, a switch M3 connected between the second power supply end and the control end of the first quad PMOS transistor P14. Figure 4 In the embodiment shown, the switch M1 and the switch M3 are used as an example. Figure 4 In the embodiment, when the enable pin EN receives the first signal, the switch M1 is turned on and the switch M3 is turned off.

[0090] In other embodiments, the turn-on switch may also include a switch connected between the first power supply terminal VDD and the first-first PMOS tube P11 and / or the first-second PMOS tube P12, and / or a switch connected between the second power supply terminal and the first-third PMOS tube P13, and / or a switch connected between the power ground pin GND and the first-second NMOS tube N12 and / or the first-third NMOS tube N13, etc., and the present application does not limit this.

[0091] It is understandable that the embodiment of the present application does not limit the circuit structure of the first conversion unit 2010. The specific implementation of the first conversion unit 2010 can also be designed according to actual needs. As long as the solution can indirectly or directly control the power switch opening speed based on the first resistor, it belongs to the protection scope of the present application.

[0092] In this embodiment, when the control chip matches different power switches, the turn-on current flowing through the driving pin can be set by the first resistor, thereby controlling the turn-on speed of the power switch to ensure that the turn-on speed of the power switch can meet the requirements.

[0093] exist Figure 3 Based on the embodiment shown, the following Figure 5 The illustrated embodiment explains the implementation principle of how the second resistor R2 affects the turn-off speed of the power switch Q1 .

[0094] Figure 5 1 is a circuit structure diagram of a control chip and its peripheral components provided in the fifth embodiment of the present application. In this example, when the enable pin EN receives the second signal, the off current Ioff flows through the drive pin GATE to control the off speed of the power switch Q1.

[0095] like Figure 5 As shown, in the control chip 20, the second conversion unit 2020 also includes a second-first PMOS tube P21, a second-second PMOS tube P22, a second-second NMOS tube N22, a second-third NMOS tube N23, a second-third PMOS tube P23, a second-fourth PMOS tube P24, a second-fourth NMOS tube N24, and a second-fifth NMOS tube N25. Among them, the second-first PMOS tube P21 and the second-first NMOS tube N21 are connected in series, the control end of the second-first PMOS tube P21 is connected to the control end of the second-second PMOS tube P22, the second-first PMOS tube P21 and the second-second PMOS tube P22 are also connected to the first power supply end, the second-second PMOS tube P22 and the second-second NMOS tube N22 are connected in series, the control end of the second-second NMOS tube N22 is connected to the control end of the second-third NMOS tube N23, the second-second NMOS tube N22 and the second-third NMOS tube N23 are also connected to the power ground pin GND, and the second-third NMOS tube N2 The second-third PMOS tube P23 and the second-fourth PMOS tube P23 are connected in series, the control end of the second-third PMOS tube P23 is connected to the control end of the second-fourth PMOS tube P24, the second-third PMOS tube P23 and the second-fourth PMOS tube P24 are also connected to the second power supply end, the second-fourth PMOS tube P24 and the second-fourth NMOS tube N24 are connected in series, the control end of the second-fourth NMOS tube N24 is connected to the control end of the second-five NMOS tube N25, the second-fourth NMOS tube N24 and the second-five NMOS tube N25 are also connected to the second end of the power switch Q1, and the second-five NMOS tube N25 is also connected to the driving pin GATE.

[0096] In this embodiment, based on Figure 5In the circuit connection relationship shown, the output current of the second-first PMOS tube P21 is equal to the output current of the second-first NMOS tube N21, the fourth mirror current of the second-second PMOS tube P22 is a mirror image of the output current of the second-first PMOS tube P21, the output current of the second-second NMOS tube N22 is equal to the fourth mirror current of the second-second PMOS tube P22, the fifth mirror current of the second-third NMOS tube N23 is a mirror image of the output current of the second-second NMOS tube N22, the output current of the second-third PMOS tube P23 is equal to the fifth mirror current of the second-third NMOS tube N23, the sixth mirror current of the second-fourth PMOS tube P24 is a mirror image of the output current of the second-third PMOS tube P23, the output current of the second-fourth NMOS tube N24 is equal to the sixth mirror current of the second-fourth PMOS tube P24, the seventh mirror current of the second-fifth NMOS tube N25 is a mirror image of the output current of the second-fourth NMOS tube N24, and the off current Ioff is equal to the seventh mirror current.

[0097] and Figure 4 Similar to the first power supply terminal, the first power supply terminal is the power supply terminal inside the control chip, and the voltage of the first power supply terminal is usually less than the voltage of the power supply terminal VCC. When the power switch Q1 is an NMOS tube and is connected as a high-side switch, the second power supply terminal is the output terminal of the boost circuit (not shown in the figure). The main function of the boost circuit is to enhance the driving ability of the drive circuit and increase the voltage at the drive pin GATE so that the power switch Q1 can be turned on. Figure 4 In other embodiments of the present application, when the power switch Q1 is a PMOS tube or the power switch Q1 is an NMOS tube and is connected as a low-side switch, the second power supply terminal can be an internal power supply terminal with the same potential as the power supply pin VCC, which is not described here.

[0098] In the embodiment of the present application, it is assumed that the ratio of the output current i21 of the second-first PMOS tube P21 to the fourth mirror current i22 of the second-second PMOS tube P22 is 1:k21, the ratio of the output current i22 of the second-second NMOS tube N22 to the fifth mirror current i23 of the second-third NMOS tube N23 is 1:k22, the ratio of the output current i23 of the second-third PMOS tube P23 to the sixth mirror current i24 of the second-fourth PMOS tube P24 is 1:k23, and the ratio of the output current i24 of the second-fourth NMOS tube N24 to the seventh mirror current i25 of the second-fifth NMOS tube N25 is 1:k24. In this way, if the output current of the second-first NMOS tube N21 is i21, the seventh mirror current i25 of the second-fifth NMOS tube N25 is equal to k21*k22*k23*k24*Vref2 / R2. Therefore, when the enable pin EN receives the second signal, the off current Ioff flowing through the drive pin GATE = k21*k22*k23*k24*Vref2 / R2, so that by replacing the second resistor R2 or adjusting the resistance value of the second resistor R2, the off current Ioff flowing through the drive pin GATE can be changed, thereby controlling the turn-off speed of the power switch Q1. Among them, k21, k22, k23, k24, etc. can be set according to actual needs, and will not be described in detail here.

[0099] Optionally, in this embodiment, the off switch may include a switch M2 connected to the output end of the second conversion unit 2020, or may include at least one switch connected inside the second conversion unit 2020, for example, a switch M4 connected between the second end of the power switch Q1 and the control end of the second fifth NMOS transistor N25. Figure 5 In the example, the off switches include switch M2 and switch M4. Figure 5 In the embodiment, when the enable pin EN receives the second signal, the switch M2 is turned on and the switch M4 is turned off.

[0100] In other embodiments, the shutdown switch may also include a switch connected between the first power supply terminal VDD and the second-first PMOS tube P21 and / or the second-second PMOS tube P22, and / or a switch connected between the power ground pin GND and the second-second NMOS tube N22 and / or the second-third NMOS tube N23, and / or a switch connected between the second power supply terminal and the second-third PMOS tube P23 and / or the second-fourth PMOS tube P24, and / or a switch connected between the second end of the power switch Q1 and the second-fourth NMOS tube N24, and the present application does not limit this.

[0101] It can be understood that the embodiment of the present application does not limit the circuit structure of the second conversion unit 2020. The specific implementation of the second conversion unit 2020 can also be designed according to actual needs. As long as the solution can indirectly or directly control the shutdown speed of the power switch based on the second resistor, it belongs to the protection scope of the present application.

[0102] In this embodiment, when the control chip matches different power switches, the turn-off current flowing through the drive pin can be set by the second resistor, thereby controlling the turn-off speed of the power switch, thereby ensuring that the turn-off speed of the power switch can meet the requirements.

[0103] It can be understood that in the embodiments of the present application, the on switch and the off switch can be implemented in various forms, such as field effect transistors, triodes, etc. The embodiments of the present application do not limit the form of the switch, which can be selected according to actual needs.

[0104] In summary, the control chip provided in the embodiment of the present application sets a turn-on current flowing through a driving pin through a first resistor to control a turn-on speed of a power switch, and sets a turn-off current flowing through a driving pin through a second resistor to control a turn-off speed of the power switch. That is, in actual applications, the first resistor and the second resistor can be adjusted or replaced based on the power switch matched with the control chip so that the turn-on speed and the turn-off speed of the power switch meet the requirements.

[0105] Optionally, based on the above embodiments, the embodiments of the present application further provide an intelligent electronic switch. Referring to the contents recorded in each embodiment, the intelligent electronic switch includes the control chip 20, the power supply terminal, the power ground terminal, the load output terminal OUT and the power switch Q1 in the above embodiments.

[0106] Among them, the power supply end and the power ground end are used to connect to the battery 10, the control end of the power switch Q1 is connected to the drive pin GATE of the control chip 20, the first end of the power switch Q1 is connected to the power supply end or the power ground end, the second end of the power switch Q1 is connected to the load output end OUT, the load output end OUT is used to connect to the load R0, and the control chip 20 is used to control the power switch Q1 to be turned on and / or turned off.

[0107] In this embodiment, the power supply end is usually directly or indirectly connected to the positive electrode of the battery 10, and the power ground end can usually be directly or indirectly connected to the negative electrode of the battery 10. The opening and / or closing of the power switch Q1 is controlled by the control chip 20. The power switch Q1 can be connected as a high-side switch, that is, connected between the power supply end and the load R0. The power switch Q1 can also be connected as a low-side switch, that is, connected between the load R0 and the power ground end. It can be set according to actual needs and will not be elaborated here.

[0108] Optionally, the power switch Q1 is any one of an NMOS tube, a PMOS tube, and a JFET, and / or the power switch Q1 is implemented as a silicon device, silicon carbide, gallium arsenide, or gallium nitride.

[0109] In a possible design of the present application, the power switch Q1 is located on a first chip other than the control chip 20, wherein the power supply end is a power supply pin, the power ground end is a power ground pin, and the load output end OUT is a load output pin, and accordingly, the load output pin is located on the first chip.

[0110] It is understandable that in the embodiment of the present application, the first chip, the control chip 20, etc. can also add other pins, omit related pins, or merge related pins as needed. Here, the first chip and the control chip 20 can be packaged into one product.

[0111] In addition, in other embodiments of the present application, a car is also provided, which can be an electric car, such as an electric passenger car or an electric commercial vehicle, or a hybrid car or a fuel car. The car can include the control chip 20 in the above embodiments, or the intelligent electronic switch in the above embodiments, and can also include a battery 10, a first resistor R1, a second resistor R2, a load R0, and a microprocessor (not shown). Among them, the positive and negative electrodes of the battery 10 are connected to the power supply pin VCC and the power ground pin GND of the control chip 20, the first resistor R1 is connected to the on time setting pin RTon of the control chip 20, the second resistor R2 is connected to the off time setting pin RToff of the control chip 20, the load R0 is connected to the power switch Q1, and the microprocessor is connected to the control chip 20.

[0112] Optionally, the battery 10 can be a single cell or a battery pack, which is not limited in this embodiment. The battery 10 is generally a storage battery, which provides voltages such as 12V, 24V, 48V, etc., and can also be other types of batteries such as lithium batteries. The first resistor R1 is connected to the on-time setting pin RTon of the control chip 20, and is used to set the on-current Ion flowing through the drive pin GATE of the control chip 20. The second resistor R2 is connected to the off-time setting pin RToff of the control chip 20, and is used to set the off-current Ioff flowing through the drive pin GATE of the control chip 20. The load R0 includes at least one of a resistive load, an inductive load, and a capacitive load. The resistive load is, for example, a seat adjustment device, an auxiliary heating device, a window heating device, a light emitting diode (LED), a rear lighting, or other resistive loads. The inductive load is, for example, a pump, an actuator, a motor, an anti-lock braking system (ABS), an electronic braking system (EBS), a fan, or other systems including an inductive load for one or more wiper systems. The capacitive load is, for example, a lighting element, such as a xenon arc lamp.

[0113] The microcontroller is connected to the intelligent electronic switch for controlling the intelligent electronic switch. Meanwhile, the intelligent electronic switch feeds back its state and relevant parameter information, such as relevant parameter information of diagnosis, to the microprocessor for processing by the microprocessor.

[0114] It is understandable that the control chip, intelligent electronic switch, etc. of this embodiment are not limited to use in automotive electronics, but can also be used in industrial automation, aerospace and other fields, which will not be elaborated here.

[0115] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0116] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A control chip for a power switch, used to control the on-off or off-off of a power switch, characterized in that: The control chip includes a power supply pin, a power ground pin, an enable pin, a drive pin, an on time setting pin, an off time setting pin and a drive circuit; The power supply pin and the power ground pin are used to connect to a battery, the drive circuit is connected to the on-time setting pin, the off-time setting pin, the enable pin and the drive pin respectively, the on-time setting pin is also used to connect to a first resistor, the off-time setting pin is also used to connect to a second resistor, and the drive pin is also used to connect to a control end of a power switch; the first resistor is used to set a turn-on current flowing through the drive pin, the second resistor is used to set a turn-off current flowing through the drive pin, the first resistor, the second resistor and the power switch are all external to the control chip, the first resistor is different, the corresponding turn-on current is different, the second resistor is different, the corresponding turn-off current is different; When the enable pin receives a first signal, the drive circuit controls the power switch to turn on, and the turn-on speed of the power switch is determined by the turn-on current; when the enable pin receives a second signal, the drive circuit controls the power switch to turn off, and the turn-off speed of the power switch is determined by the turn-off current.

2. The control chip according to claim 1, characterized in that: The driving circuit includes a first control unit and a second control unit; The first control unit is connected to the turn-on time setting pin, the enable pin and the drive pin respectively. When the enable pin receives a first signal, the first control unit generates a turn-on current according to the first resistor and flows through the drive pin. The larger the turn-on current, the faster the turn-on speed of the power switch and the shorter the time required for the power switch to be fully turned on. The second control unit is respectively connected to the turn-off time setting pin, the enable pin and the drive pin. When the enable pin receives a second signal, the second control unit generates a turn-off current according to the second resistor that flows through the drive pin. The larger the turn-off current, the faster the power switch is disconnected and the shorter the time required for the power switch to be completely turned off.

3. The control chip according to claim 2, characterized in that: The first control unit includes a first operational amplifier unit, a first NMOS tube and a first conversion unit; The first input end of the first operational amplifier unit is used to access the first reference voltage, the second input end thereof is connected to the start-up time setting pin and the second end of the first NMOS transistor, the output end thereof is connected to the control end of the first NMOS transistor, the first end of the first NMOS transistor is connected to the first conversion unit, and the first conversion unit is also connected to the driving pin; The first operational amplifier unit is used to generate a control signal for turning on the first NMOS tube based on the first reference voltage and the first resistor connected to the turn-on time setting pin. The output current of the first NMOS tube is determined based on the first reference voltage and the first resistor. The first conversion unit is used to convert the output current of the first NMOS tube into the turn-on current. The smaller the first resistor is, the larger the output current of the first NMOS tube is, and the corresponding turn-on current is larger.

4. The control chip according to claim 3, characterized in that: The start-up current flows through the drive pin when the enable pin receives the first signal to control the start-up speed of the power switch; The first conversion unit includes a first-first PMOS tube, a first-second PMOS tube, a first-second NMOS tube, a first-third NMOS tube, a first-third PMOS tube and a first-fourth PMOS tube; The first PMOS tube and the first NMOS tube are connected in series, the control end of the first PMOS tube is connected to the control end of the first second PMOS tube, the first PMOS tube and the first second PMOS tube are also connected to the first power supply end, the first second PMOS tube and the first second NMOS tube are connected in series, the control end of the first second NMOS tube is connected to the control end of the first third NMOS tube, the first second NMOS tube and the first third NMOS tube are also connected to the power ground pin, the first third NMOS tube and the first third PMOS tube are connected in series, the control end of the first third PMOS tube is connected to the control end of the first fourth PMOS tube, the first third PMOS tube and the first fourth PMOS tube are also connected to the second power supply end, and the first fourth PMOS tube is also connected to the driving pin; The output current of the first PMOS tube is equal to the output current of the first NMOS tube, the first mirror current of the first second PMOS tube is mirrored to the output current of the first PMOS tube, the output current of the first second NMOS tube is equal to the first mirror current of the first second PMOS tube, the second mirror current of the first third NMOS tube is mirrored to the output current of the first second NMOS tube, the output current of the first third PMOS tube is equal to the second mirror current of the first third NMOS tube, the third mirror current of the first fourth PMOS tube is mirrored to the output current of the first third PMOS tube, and the start-up current is equal to the third mirror current.

5. The control chip according to any one of claims 2 to 4, characterized in that: The second control unit includes a second operational amplifier unit, a second NMOS tube and a second conversion unit; The first input end of the second operational amplifier unit is used to access the second reference voltage, the second input end thereof is connected to the off-time setting pin and the second end of the second-NMOS tube, the output end thereof is connected to the control end of the second-NMOS tube, the first end of the second-NMOS tube is connected to the second conversion unit, and the second conversion unit is also connected to the driving pin; The second operational amplifier unit is used to generate a control signal for turning on the second-to-NMOS tube based on the second reference voltage and the second resistor connected to the shutdown time setting pin. The output current of the second-to-NMOS tube is determined based on the second reference voltage and the second resistor. The second conversion unit is used to convert the output current of the second-to-NMOS tube into the shutdown current. The smaller the second resistor is, the larger the output current of the second-to-NMOS tube is, and the corresponding shutdown current is larger.

6. The control chip according to claim 5, characterized in that: The shutdown current flows through the driving pin when the enable pin receives a second signal to control the shutdown speed of the power switch; The second conversion unit includes a second-first PMOS tube, a second-second PMOS tube, a second-second NMOS tube, a second-third NMOS tube, a second-third PMOS tube, a second-fourth PMOS tube, a second-fourth NMOS tube and a second-fifth NMOS tube; The second-first PMOS tube and the second-first NMOS tube are connected in series, the control end of the second-first PMOS tube is connected to the control end of the second-second PMOS tube, the second-first PMOS tube and the second-second PMOS tube are also connected to the first power supply end, the second-second PMOS tube and the second-second NMOS tube are connected in series, the control end of the second-second NMOS tube is connected to the control end of the second-third NMOS tube, the second-second NMOS tube and the second-third NMOS tube are also connected to the power ground pin, the second-third NMOS tube and the second-third PMOS tube are connected in series, the control end of the second-third PMOS tube is connected to the control end of the second-fourth PMOS tube, the second-third PMOS tube and the second-fourth PMOS tube are also connected to the second power supply end, the second-fourth PMOS tube and the second-fourth NMOS tube are connected in series, the control end of the second-fourth NMOS tube is connected to the control end of the second-fifth NMOS tube, the second-fourth NMOS tube and the second-fifth NMOS tube are also connected to the second end of the power switch, and the second-fifth NMOS tube is also connected to the driving pin; The output current of the second-first PMOS tube is equal to the output current of the second-first NMOS tube, the fourth mirror current of the second-second PMOS tube is mirrored with the output current of the second-first PMOS tube, the output current of the second-second NMOS tube is equal to the fourth mirror current of the second-second PMOS tube, the fifth mirror current of the second-third NMOS tube is mirrored with the output current of the second-second NMOS tube, the output current of the second-third PMOS tube is equal to the fifth mirror current of the second-third NMOS tube, the sixth mirror current of the second-fourth PMOS tube is mirrored with the output current of the second-third PMOS tube, the output current of the second-fourth NMOS tube is equal to the sixth mirror current of the second-fourth PMOS tube, the seventh mirror current of the second-fifth NMOS tube is mirrored with the output current of the second-fourth NMOS tube, and the shutdown current is equal to the seventh mirror current.

7. An intelligent electronic switch, characterized in that: It comprises a control chip as claimed in any one of claims 1 to 6, a power supply terminal, a power ground terminal, a load output terminal and a power switch; The power supply end and the power ground end are used to be connected to a battery, the control end of the power switch is connected to a drive pin of the control chip, the first end of the power switch is connected to the power supply end or the power ground end, the second end of the power switch is connected to a load output end, and the load output end is used to be connected to a load; the control chip is used to control the power switch to be turned on or off.

8. The intelligent electronic switch according to claim 7, characterized in that: The power switch is any one of an NMOS tube, a PMOS tube, and a JFET, and / or the power switch is implemented as a silicon device, silicon carbide, gallium arsenide, or gallium nitride.

9. The intelligent electronic switch according to claim 7 or 8, characterized in that: The power switch is located on a first chip other than the control chip; Among them, the power supply end is a power supply pin, the power ground end is a power ground pin, the load output end is a load output pin, and the load output pin is located on the first chip.

10. An automobile, characterized in that: Comprising the control chip according to any one of claims 1 to 6, or the intelligent electronic switch according to any one of claims 7 to 9; It also includes a battery, a first resistor, a second resistor, a load and a microprocessor, wherein the positive and negative electrodes of the battery are connected to the power supply pin and the power ground pin of the control chip respectively, the first resistor is connected to the turn-on time setting pin of the control chip, the second resistor is connected to the turn-off time setting pin of the control chip, the load is connected to the power switch, and the microprocessor is connected to the control chip.

11. The automobile according to claim 10, characterized in that: The vehicle is an electric vehicle, a hybrid vehicle or a fuel vehicle, and the load includes at least one of a resistive load, an inductive load and a capacitive load.

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