Epitaxial wafer and preparation method thereof

By controlling the temperature difference during the epitaxial wafer preparation process by high-temperature baking and low-temperature growth of the epitaxial layer, the problem of high epitaxial wafer warping is solved, and the warping is reduced and the yield is improved.

CN118127626BActive Publication Date: 2025-09-23ZHONGHUAN ADVANCED SEMICONDUCTOR TECHNOLOGY CO LTD
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Patent Information

Application Number
CN202410200909.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-02-21
Publication Date
2025-09-23
Estimated Expiration
2044-02-21

AI Technical Summary

Technical Problem

During the epitaxial wafer preparation process, high temperature thermal stress leads to high warping, affecting product yield.

Method used

The substrate is baked at high temperature before growing the epitaxial wafer, and the epitaxial layer is grown at low temperature during the epitaxial growth process. The temperature difference is controlled at 60℃≤T1-T2≤80℃, and the thermal stress is released by controlling the flow and temperature of hydrogen, silicon source gas and doping gas.

Benefits of technology

The warpage of the epitaxial wafer is reduced and the product yield is improved.

✦ Generated by Eureka AI based on patent content.

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Abstract

The present application discloses an epitaxial wafer and a method for preparing the same. The epitaxial wafer preparation method comprises: placing a substrate into a reaction chamber; heating the reaction chamber to a first temperature T1, introducing hydrogen into the reaction chamber, and baking the substrate; cooling the reaction chamber to a second temperature T2, maintaining the introduction of hydrogen into the reaction chamber, and introducing silicon source gas and doping gas into the reaction chamber to grow an epitaxial layer on the substrate; stopping the introduction of silicon source gas and doping gas to obtain an epitaxial wafer; wherein, 60°C ≤ T1-T2 ≤ 80°C. The present application bakes the substrate at a high temperature before growing the epitaxial wafer, and uses a low temperature to grow the epitaxial layer during the epitaxial growth process, thereby releasing the thermal stress during the epitaxial layer growth process, thereby reducing the warpage of the prepared epitaxial wafer and improving the product yield.
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Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an epitaxial wafer and a method for preparing the same. Background Art

[0002] Currently, high-temperature thermal stress is usually generated during the preparation of epitaxial wafers, resulting in high warping of the grown epitaxial wafers. Summary of the Invention

[0003] The purpose of this application is to provide a method for preparing an epitaxial wafer, which can improve the warping of the epitaxial wafer and increase the product yield.

[0004] The first aspect of the present application provides a method for preparing an epitaxial wafer, comprising:

[0005] placing the substrate into the reaction chamber;

[0006] Raising the temperature of the reaction chamber to a first temperature T1, introducing hydrogen into the reaction chamber, and baking the substrate;

[0007] Cooling the reaction chamber to a second temperature T2, keeping the hydrogen gas flowing into the reaction chamber, and flowing a silicon source gas and a doping gas into the reaction chamber to grow an epitaxial layer on the substrate;

[0008] Stopping the introduction of the silicon source gas and the doping gas to obtain an epitaxial wafer;

[0009] Among them, 60℃≤T1-T2≤80℃.

[0010] In some embodiments, when the reaction chamber is heated to a first temperature T1, hydrogen is introduced into the reaction chamber, and the substrate is baked, the hydrogen flow rate is 40 to 60 L / min; the baking time is 1 to 1.5 minutes; and the first temperature T1 ranges from 1170 to 1180°C.

[0011] In some embodiments, when the reaction chamber is cooled to a second temperature T2, the hydrogen is kept introduced into the reaction chamber, and silicon source gas and dopant gas are introduced into the reaction chamber to grow an epitaxial layer on the substrate, the hydrogen flow rate is 40 to 60 L / min; the silicon source gas flow rate is 10 to 20 g / min; the dopant gas flow rate is 0 to 300 sccm; the second temperature T2 ranges from 1100 to 1110°C; and the epitaxial layer growth rate is 3.5 to 4.2 μm / min.

[0012] In some embodiments, before placing the substrate into the reaction chamber, the method further includes:

[0013] The reaction chamber is heated to a third temperature T3, and hydrogen chloride gas is introduced to etch the reaction chamber.

[0014] In some embodiments, when the reaction chamber is heated to a third temperature T3 and hydrogen chloride gas is introduced to etch the reaction chamber, the flow rate of hydrogen chloride is 20 to 21 L / min; the third temperature T3 is in the range of 1150 to 1190° C.; and the etching time is 1 to 2 minutes.

[0015] In some embodiments, after heating the reaction chamber to the third temperature T3 and introducing hydrogen chloride gas to etch the susceptor in the reaction chamber, the method further includes:

[0016] The reaction chamber is cooled to a fourth temperature T4, wherein the fourth temperature T4 is in the range of 750-850°C.

[0017] In some embodiments, after obtaining the epitaxial wafer, the method further includes:

[0018] After hydrogen is introduced to purge the epitaxial wafer, the reaction chamber is cooled to a fifth temperature T5.

[0019] In some embodiments, after hydrogen is introduced to purge the epitaxial wafer, during the process of cooling the reaction chamber to the fifth temperature T5, the hydrogen flow rate is 40 to 60 L / min; the purge time is 5 to 10 s; and the fifth temperature T5 ranges from 750 to 850°C.

[0020] In some embodiments, before introducing the silicon source gas and the doping gas into the reaction chamber, the method further comprises:

[0021] Maintaining the reaction chamber at the second temperature T2 for 30 to 60 seconds;

[0022] The silicon source gas and the doping gas are introduced into the tail gas treatment device.

[0023] In some embodiments, the silicon source gas is selected from trichlorosilane.

[0024] In some embodiments, the doping gas is selected from phosphine or borane.

[0025] In some embodiments, a flow ratio of the silicon source gas to the doping gas is 10-20:0-300.

[0026] A second aspect of the present application provides an epitaxial wafer, which is prepared using the epitaxial wafer preparation method as described above.

[0027] In some embodiments, the warpage of the epitaxial wafer is 40-50 μm.

[0028] The beneficial effects of this application are:

[0029] The present application provides a method for preparing an epitaxial wafer, comprising: placing a substrate in a reaction chamber; heating the reaction chamber to a first temperature T1, introducing hydrogen into the reaction chamber, and baking the substrate; cooling the reaction chamber to a second temperature T2, maintaining the introduction of hydrogen into the reaction chamber, and introducing a silicon source gas and a dopant gas into the reaction chamber to grow an epitaxial layer on the substrate; stopping the introduction of the silicon source gas and the dopant gas to obtain an epitaxial wafer; wherein 60°C ≤ T1-T2 ≤ 80°C. By baking the substrate at a high temperature before growing the epitaxial wafer and growing the epitaxial layer at a low temperature during the epitaxial growth process, the present application can release thermal stress during epitaxial layer growth, thereby reducing warpage of the prepared epitaxial wafer and improving product yield.

[0030] The present application also provides an epitaxial wafer having a warpage of 40 to 50 μm. The epitaxial wafer prepared by the epitaxial wafer preparation method of the present application has a lower warpage. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Flowchart of the epitaxial wafer preparation method provided in this application;

[0032] Figure 2 Schematic diagram of the epitaxial wafer warpage measurement method provided in this application. DETAILED DESCRIPTION

[0033] The technical solutions of the present application will be described clearly and completely below in conjunction with the embodiments and drawings of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. The various embodiments of the present application may be presented in the form of a range; it should be understood that the description in the form of a range is only for convenience and brevity and should not be understood as a rigid limitation on the scope of the present application; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single numerical values ​​within the range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the numbered range, such as 1, 2, 3, 4, 5 and 6, which applies regardless of the range. In addition, whenever a numerical range is indicated herein, it is meant to include any quoted number (fractional or integer) within the indicated range.

[0034] like Figure 1 As shown, the first aspect of the present application provides a method for preparing an epitaxial wafer, comprising:

[0035] Step S1: placing the substrate into the reaction chamber;

[0036] Step S2: heating the reaction chamber to a first temperature T1, introducing hydrogen into the reaction chamber, and baking the substrate;

[0037] Step S3: cooling the reaction chamber to a second temperature T2, continuing to introduce hydrogen into the reaction chamber, and introducing silicon source gas and doping gas into the reaction chamber to grow an epitaxial layer on the substrate;

[0038] Step S4: stopping the introduction of silicon source gas and doping gas to obtain an epitaxial wafer;

[0039] Among them, 60℃≤T1-T2≤80℃.

[0040] The present application bakes the substrate at high temperature before growing the epitaxial wafer and grows the epitaxial layer at low temperature during the epitaxial growth process, which can release the thermal stress during the epitaxial layer growth process, thereby reducing the warping of the prepared epitaxial wafer and improving the product yield.

[0041] In some embodiments, the value of T1-T2 is any one of 60°C, 65°C, 70°C, 75°C, 80°C, or a range consisting of any two of them.

[0042] In some embodiments, when the reaction chamber is heated to the first temperature T1, hydrogen is introduced into the reaction chamber, and the substrate is baked, the hydrogen flow rate is 40 to 60 L / min; the baking time is 1 to 1.5 minutes; and the first temperature T1 ranges from 1170 to 1180°C.

[0043] Specifically, the hydrogen flow rate is any one of 40L / min, 45L / min, 50L / min, 55L / min, and 60L / min, or a range consisting of any two of them; the baking time is any one of 1min, 1.1min, 1.2min, 1.3min, 1.4min, and 1.5min, or a range consisting of any two of them; and the first temperature T1 is any one of 1170°C, 1171°C, 1172°C, 1173°C, 1174°C, 1175°C, 1176°C, 1177°C, 1178°C, 1179°C, and 1180°C, or a range consisting of any two of them.

[0044] It can be understood that the present application can better release the thermal stress during the growth of the epitaxial layer and reduce the warping of the prepared epitaxial wafer by controlling the temperature of the reaction chamber to 1170-1180°C, the hydrogen gas flow rate to 40-60L / min, and the baking time to 1-1.5min during the baking process.

[0045] In some embodiments, during the process of growing an epitaxial layer on a substrate by cooling the reaction chamber to a second temperature T2, while maintaining the flow of hydrogen into the reaction chamber and introducing a silicon source gas and a dopant gas into the reaction chamber, the hydrogen flow rate is 40 to 60 L / min; the silicon source gas flow rate is 10 to 20 g / min; and the dopant gas flow rate is 0 to 300 sccm. The second temperature T2 ranges from 1100 to 1110° C.; and the epitaxial layer growth rate is 3.5 to 4.2 μm / min. The second temperature T2 is also the growth temperature of the epitaxial layer.

[0046] Specifically, the gas flow rate of hydrogen is any one of 40L / min, 45L / min, 50L / min, 55L / min, and 60L / min, or any two of them; the gas flow rate of silicon source gas is any one of 10g / min, 11g / min, 12g / min, 13g / min, 14g / min, 15g / min, 16g / min, 17g / min, 18g / min, 19g / min, and 20g / min, or any two of them; the doping gas is any one of 10g / min, 11g / min, 12g / min, 13g / min, 14g / min, 15g / min, 16g / min, 17g / min, 18g / min, 19g / min, and 20g / min, or any two of them; The size of the body gas flow rate is determined by the doping amount. Specifically, the doping gas flow rate is any one of 0sccm, 50sccm, 100sccm, 150sccm, 200sccm, 250sccm, and 300sccm, or a range consisting of any two of them; the second temperature T2 is any one of 1100℃, 1101℃, 1102℃, 1103℃, 1104℃, 1105℃, 1106℃, 1107℃, 1108℃, 1109℃, and 1110℃, or a range consisting of any two of them.

[0047] It can be understood that by controlling the epitaxial layer growth temperature to 1100-1110°C, the silicon source gas flow rate to 10-20g / min, and the hydrogen gas flow rate to 40-60L / min during the epitaxial layer growth process, the thermal stress during the epitaxial layer growth process can be released, thereby reducing the warping of the prepared epitaxial wafer and improving the product yield.

[0048] In some embodiments, before placing the substrate into the reaction chamber, the method further includes:

[0049] The reaction chamber is heated to a third temperature T3, and hydrogen chloride gas is introduced to etch the susceptor in the reaction chamber.

[0050] In some embodiments, when the reaction chamber is heated to the third temperature T3 and hydrogen chloride gas is introduced to etch the reaction chamber, the flow rate of hydrogen chloride is 20 to 21 L / min; the third temperature T3 ranges from 1150 to 1190° C.; and the etching time is 1 to 2 minutes.

[0051] Specifically, the hydrogen chloride gas flow rate is 20 L / min or 21 L / min; the third temperature T3 is any one of 1150° C., 1160° C., 1170° C., 1180° C., and 1190° C., or a range consisting of any two thereof; and the etching time is any one of 1 minute, 1.5 minutes, and 2 minutes, or a range consisting of any two thereof.

[0052] It can be understood that the present application controls the temperature of the reaction chamber to 1150-1190°C, the gas flow rate of hydrogen chloride to 20-21 L / min, and the etching time to 1-2 minutes during the etching process, thereby removing the residues on the base in the reaction chamber and improving the stability of the epitaxial layer growth.

[0053] In some embodiments, after heating the reaction chamber to the third temperature T3 and introducing hydrogen chloride gas to etch the susceptor in the reaction chamber, the method further includes:

[0054] The reaction chamber is cooled to a fourth temperature T4, and the fourth temperature T4 ranges from 750°C to 850°C.

[0055] Specifically, the fourth temperature T4 is any one of 750° C., 800° C., and 850° C., or a range consisting of any two of the above.

[0056] In some embodiments, after obtaining the epitaxial wafer, the method further includes:

[0057] After hydrogen is introduced to purge the epitaxial wafer, the reaction chamber is cooled to a fifth temperature T5.

[0058] It is understandable that the use of hydrogen to purge the epitaxial wafer can, on the one hand, remove the residues that have not participated in the reaction, and on the other hand, take away the temperature of the epitaxial wafer and cool it down.

[0059] In some embodiments, after hydrogen is introduced to purge the epitaxial wafer, during the process of cooling the reaction chamber to the fifth temperature T5, the hydrogen gas flow rate is 40 to 60 L / min; the purge time is 5 to 10 s; and the fifth temperature T5 ranges from 750 to 850°C.

[0060] Specifically, the hydrogen flow rate is any one of 40L / min, 45L / min, 50L / min, 55L / min, 60L / min, or a range consisting of any two of them; the purge time is any one of 5s, 6s, 7s, 8s, 9s, or 10s, or a range consisting of any two of them; the fifth temperature T5 is any one of 750°C, 800°C, or 850°C, or a range consisting of any two of them.

[0061] In some embodiments, before introducing the silicon source gas and the doping gas into the reaction chamber, the process further includes:

[0062] Maintaining the reaction chamber at the second temperature T2 for 30 to 60 seconds;

[0063] The silicon source gas and the doping gas are introduced into the tail gas treatment device.

[0064] Specifically, the constant temperature is within the range of any one of 30s, 40s, 50s, and 60s, or any two of them.

[0065] It can be understood that after the reaction chamber is heated to the second temperature T2, the temperature has not reached stability. By maintaining the temperature for 30 to 60 seconds, the temperature of the epitaxial layer growth is allowed to reach a stable state, which is conducive to the growth of the epitaxial layer; the initial gas flow rates of the silicon source gas and the doping gas are unstable. The silicon source gas and the doping gas are first introduced into the exhaust gas treatment device, and the gas flow rate is allowed to reach a stable state before being introduced into the reaction chamber, which can improve the stability of the epitaxial layer growth.

[0066] In some embodiments, the silicon source gas is selected from trichlorosilane.

[0067] In some embodiments, the dopant gas is selected from phosphine or borane.

[0068] In some embodiments, the flow ratio of the silicon source gas to the doping gas is 10-20:0-300.

[0069] In some embodiments, the heating rate of the reaction chamber from the initial temperature to the third temperature T3 is 10-15°C / s. Specifically, the heating rate from the initial temperature to the third temperature T3 is in the range of any one of 10°C / s, 11°C / s, 12°C / s, 13°C / s, 14°C / s, and 15°C / s, or any two thereof.

[0070] In some embodiments, the cooling rate of the reaction chamber from the third temperature T3 to the fourth temperature T4 is 10-15°C / s. Specifically, the cooling rate from the third temperature T3 to the fourth temperature T4 is in the range of any one of 10°C / s, 11°C / s, 12°C / s, 13°C / s, 14°C / s, and 15°C / s, or any two thereof.

[0071] In some embodiments, the heating rate of the reaction chamber from the fourth temperature T4 to the first temperature T1 is 5-10°C / s. Specifically, the heating rate from the fourth temperature T4 to the first temperature T1 is in the range of any one of 5°C / s, 6°C / s, 7°C / s, 8°C / s, 9°C / s, and 10°C / s, or any two thereof.

[0072] In some embodiments, the cooling rate of the reaction chamber from the first temperature T1 to the second temperature T2 is 5-10°C / s. Specifically, the heating rate from the fourth temperature T4 to the first temperature T1 is in the range of any one of 5°C / s, 6°C / s, 7°C / s, 8°C / s, 9°C / s, and 10°C / s, or any two thereof.

[0073] In some embodiments, the cooling rate of the reaction chamber from the second temperature T2 to the fifth temperature T5 is 5-10°C / s. Specifically, the heating rate from the fourth temperature T4 to the first temperature T1 is in the range of any one of 5°C / s, 6°C / s, 7°C / s, 8°C / s, 9°C / s, and 10°C / s, or any two thereof.

[0074] A second aspect of the present application provides an epitaxial wafer, which is prepared using the epitaxial wafer preparation method as described above.

[0075] In some embodiments, the warpage of the epitaxial wafer is 40-50 μm.

[0076] Specifically, the warpage of the epitaxial wafer is in the range of any one of 40 μm, 41 μm, 42 μm, 43 μm, 44 μm, 45 μm, 46 μm, 47 μm, 48 μm, 49 μm, and 50 μm, or any two of them.

[0077] The present application is described below with reference to specific embodiments.

[0078] Example 1

[0079] The reaction chamber was heated to 1170°C, and hydrogen chloride gas was introduced to etch the susceptor in the reaction chamber. The hydrogen chloride flow rate was 20 L / min, the temperature of the reaction chamber was 1180°C, and the etching time was 1.5 min.

[0080] Cool the reaction chamber to 800°C and place the substrate into the reaction chamber;

[0081] The reaction chamber is heated to a first temperature T1, hydrogen is introduced into the reaction chamber, and the substrate is baked. The first temperature T1 is 1175°C, the hydrogen flow rate is 50 L / min, and the baking time is 1.3 min.

[0082] The reaction chamber is cooled to a second temperature T2, and hydrogen is continuously introduced into the reaction chamber. A silicon source gas and a dopant gas are introduced into the reaction chamber to grow an epitaxial layer on the substrate. The second temperature T2 is 1105° C.; the silicon source gas flow rate is 15 g / min; the hydrogen flow rate is 50 L / min; and the epitaxial layer growth time is 160 s.

[0083] Stop introducing silicon source gas and doping gas to obtain epitaxial wafer. After introducing hydrogen to purge the epitaxial wafer, cool the reaction chamber to 800°C and take out the epitaxial wafer. The hydrogen flow rate is 50 L / min and the purge time is 8 s.

[0084] Examples 2-3

[0085] The preparation methods of Examples 2 to 3 are the same as those of Example 1, except that the first temperature T1 is adjusted.

[0086] Examples 4-5

[0087] The preparation methods of Examples 4 to 5 are the same as those of Example 1, except that the second temperature T2 is adjusted.

[0088] Comparative Example 1

[0089] The preparation method of Comparative Example 1 is the same as that of Example 1, except that high-temperature baking is not performed and the second temperature T2 is 1130°C.

[0090] Test Method

[0091] Calculation method of warpage

[0092] See also Figure 2 , using the ADE 9300 machine to measure the variation range of the highest and lowest points of the epitaxial wafer middle surface relative to the back reference surface, that is, Figure 2 The value of a in .

[0093] Table 1 shows the parameter settings and test results of Examples 1 to 5 and Comparative Example 1 of the present application.

[0094]

[0095] Result Analysis

[0096] It can be seen from the results of Examples 1 to 5, Comparative Example 1 and Table 1 that by baking the substrate at a high temperature before growing the epitaxial wafer and growing the epitaxial layer at a low temperature during the epitaxial growth process, the thermal stress during the epitaxial layer growth process can be released, thereby reducing the warpage of the prepared epitaxial wafer.

[0097] The above is a detailed introduction to the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, based on the idea of ​​the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for preparing an epitaxial wafer, characterized in that: include: Heating the reaction chamber to a third temperature T3, wherein the third temperature T3 is in the range of 1150-1190° C., and introducing hydrogen chloride gas to etch the susceptor in the reaction chamber; After introducing hydrogen chloride gas to etch the reaction chamber, the reaction chamber is cooled to a fourth temperature T4, wherein the fourth temperature T4 is in the range of 750-850° C.; placing a substrate into the reaction chamber; The reaction chamber is heated to a first temperature T1, hydrogen is introduced into the reaction chamber, and the substrate is baked; the first temperature T1 is in the range of 1170~1180 ℃; during the baking process of the substrate, the baking time is 1~1.5min; The reaction chamber is cooled to a second temperature T2, the hydrogen gas is continuously introduced into the reaction chamber, and the reaction chamber is kept at the second temperature T2 for 30 to 60 seconds; a silicon source gas and a dopant gas are introduced into the reaction chamber to grow an epitaxial layer on the substrate; the second temperature T2 is in the range of 1100 to 1110° C.; during the growth of the epitaxial layer on the substrate, the hydrogen gas flow rate is 40 to 60 L / min; and the silicon source gas flow rate is 10 to 20 g / min; Stop introducing the silicon source gas and the doping gas to obtain an epitaxial wafer, then introduce hydrogen to purge the epitaxial wafer, and then cool the reaction chamber to a fifth temperature T5, wherein the fifth temperature T5 is in the range of 750-850° C.; Wherein, 60°C≤T1-T2≤80°C, and the warpage of the epitaxial wafer is 40-50 μm.

2. The method for preparing an epitaxial wafer according to claim 1, wherein: During the process of baking the substrate, the flow rate of the hydrogen gas is 40-60 L / min.

3. The method for preparing an epitaxial wafer according to claim 1, wherein: During the process of growing the epitaxial layer on the substrate, the gas flow rate of the doping gas is 0-300 sccm; and the growth rate of the epitaxial layer is 3.5-4.2 μm / min.

4. The method for preparing an epitaxial wafer according to claim 1, wherein: During the etching of the base in the reaction chamber, the gas flow rate of hydrogen chloride is 20-21 L / min; and the etching time is 1-2 min.

5. The method for preparing an epitaxial wafer according to claim 1, wherein: During the process of cooling the reaction chamber to the fifth temperature T5, the flow rate of hydrogen is 40-60 L / min; and the purge time is 5-10 s.

6. The method for preparing an epitaxial wafer according to claim 1, wherein: Before introducing the silicon source gas and the doping gas into the reaction chamber, the method further comprises: The silicon source gas and the doping gas are introduced into the tail gas treatment device.

7. The method for preparing an epitaxial wafer according to claim 1, wherein: The silicon source gas is selected from trichlorosilane.

8. The method for preparing an epitaxial wafer according to claim 1, wherein: The doping gas is selected from phosphine or borane.

9. The method for preparing an epitaxial wafer according to claim 1, wherein: The flow ratio of the silicon source gas to the doping gas is 10-20:0-300.

Citation Information

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