Voltage drop repair method, voltage drop repair device, electronic device, and storage medium

Abstract

A voltage drop repair method, a voltage drop repair device, an electronic device and a non-transitory computer-readable storage medium. The voltage drop repair method is used for voltage drop repair of a chip, the chip comprising a plurality of standard cells, and the voltage drop repair method comprising: performing at least one repair operation on the plurality of standard cells until the plurality of standard cells satisfies a voltage drop convergence condition. Each repair operation comprises: analyzing the plurality of standard cells to determine at least one first standard cell, wherein the plurality of standard cells comprises at least one first standard cell, and each first standard cell corresponds to a dynamic voltage drop greater than a dynamic voltage drop threshold; for each first standard cell, moving the first standard cell between two via groups corresponding to the first standard cell; and performing a legal placement and rewinding operation on the at least one first standard cell.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a voltage drop repair method, a voltage drop repair device, an electronic device, and a non-transient computer-readable storage medium. Background Technology

[0002] Voltage drop refers to a phenomenon where the voltage decreases or increases on the power and ground networks inside a chip. With the continuous advancement of integrated circuit technology, the width of metal interconnects is becoming narrower and narrower, resulting in a significant increase in the resistance value on the power network. The problem of voltage drop has seriously affected the normal operation of the chip.

[0003] In digital circuits, the switching of a standard cell consumes electrical energy. When current flows through the power network, the presence of a resistive path causes a significant drop in the supply voltage when the voltage on the top metal layer reaches the standard cell at the bottom layer. This voltage change is called dynamic IR drop. Summary of the Invention

[0004] This content section is provided to briefly introduce the concepts, which will be described in detail in the subsequent detailed description section. This content section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0005] At least one embodiment of this disclosure provides a voltage drop repair method for repairing voltage drop in a chip, wherein the chip includes a plurality of standard cells, and the voltage drop repair method includes: performing at least one repair operation on the plurality of standard cells until the plurality of standard cells meet a voltage drop convergence condition, wherein each repair operation includes: analyzing the plurality of standard cells to determine at least one first standard cell, wherein the plurality of standard cells include the at least one first standard cell, and the dynamic voltage drop corresponding to each first standard cell is greater than a dynamic voltage drop threshold; for each first standard cell, moving the first standard cell to between two via groups corresponding to the first standard cell; and performing a legal placement and rewinding operation on the at least one first standard cell.

[0006] At least one embodiment of this disclosure also provides a voltage drop repair device for repairing voltage drop in a chip. The chip includes multiple standard cells, and the voltage drop repair device includes a repair module. The repair module is configured to perform at least one repair operation on the multiple standard cells until the multiple standard cells meet a voltage drop convergence condition. The repair module includes an analysis module, a movement module, and a legal placement module. In each repair operation: the analysis module is configured to analyze the multiple standard cells to determine at least one first standard cell, wherein the multiple standard cells include the at least one first standard cell, and the dynamic voltage drop corresponding to each first standard cell is greater than a dynamic voltage drop threshold; the movement module is configured to move each first standard cell to between two via groups corresponding to the first standard cell; and the legal placement module is configured to perform legal placement and rewinding operations on the at least one first standard cell.

[0007] At least one embodiment of this disclosure also provides an electronic device, including: at least one memory storing computer-executable instructions non-transitory; and at least one processor configured to run the computer-executable instructions, wherein the computer-executable instructions, when run by the at least one processor, implement the voltage drop repair method according to any embodiment of this disclosure.

[0008] At least one embodiment of this disclosure also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement the voltage drop repair method according to any embodiment of this disclosure. Attached Figure Description

[0009] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0010] Figure 1A A planar schematic diagram of a chip provided for at least one embodiment of this disclosure;

[0011] Figure 1B A schematic diagram of a power network in a channel region between SRAMs is shown;

[0012] Figure 1C A hotspot diagram showing a voltage drop greater than 10% in the channel region between SRAMs is shown;

[0013] Figure 2A schematic flowchart illustrating a voltage drop repair method provided for at least one embodiment of this disclosure;

[0014] Figure 3 A schematic diagram of a chip provided for at least one embodiment of this disclosure;

[0015] Figure 4 A schematic diagram of a voltage repair region on a chip provided for at least one embodiment of this disclosure;

[0016] Figures 5A to 5D A schematic diagram of a first standard unit and a via assembly provided for at least one embodiment of this disclosure;

[0017] Figure 6A A schematic diagram of a voltage repair region before a repair operation is performed, provided for at least one embodiment of this disclosure;

[0018] Figure 6B A schematic diagram of a voltage repair region after a repair operation is performed, provided for at least one embodiment of this disclosure;

[0019] Figure 6C A schematic diagram of a voltage repair region before a repair operation is performed, provided for at least one embodiment of this disclosure;

[0020] Figure 6D A schematic diagram of a voltage repair region after a repair operation is performed, provided for at least one embodiment of this disclosure;

[0021] Figure 7 A schematic block diagram of an electronic device provided for at least one embodiment of this disclosure;

[0022] Figure 8 A schematic block diagram of a voltage drop repair device provided for at least one embodiment of this disclosure;

[0023] Figure 9 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of this disclosure; and

[0024] Figure 10 This is a schematic diagram of the hardware structure of an electronic device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0025] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0026] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0027] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0028] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0029] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0030] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0031] When standard cells with large drives, especially inverters and buffers, are clustered together and toggling simultaneously, a significant current demand is generated. This can easily lead to voltage drops in the power network, such as dynamic voltage drops. Dynamic voltage drops cause instability in the voltage supplied to the standard cells, ultimately preventing them from operating normally and affecting the circuit's frequency and functionality.

[0032] It should be noted that in this disclosure, "standard cell with large drive" refers to a cell with a large transistor size and a large current during operation.

[0033] In a typical digital chip layout, standard cells and memory cells are arranged on the base layer. The memory cells can include Static Random-Access Memory (SRAM). First, in order to save area, the spacing between SRAMs is small, which often results in insufficient strength of the power network in the channel region between SRAMs. Second, standard cells with large drives tend to cluster in narrow channel regions, which can easily lead to voltage drops.

[0034] Figure 1A This is a planar schematic diagram of a chip provided for at least one embodiment of the present disclosure.

[0035] like Figure 1A As shown, chip 100 includes a base layer 101, on which SRAMs are arranged in an array. There is a channel region 102 between the SRAMs. The power network resources of the channel region 102 between the SRAMs on chip 100 are limited, while the power network resources of the core region 103 of chip 100 are sufficient.

[0036] In chip 100, the power supply scheme is as follows: through the crisscrossing signal lines in each metal layer, the power supply voltage is transmitted from the top metal layer through the signal lines and vias between the layers to the module units. For example... Figure 1A As shown, the core area 103 has a large area and sufficient power and network resources. Figure 1A The diagram shows two layers of signal lines in the core region 103. The solid line 1031 represents one layer of signal lines, and the dashed line 1032 represents another layer of signal lines.

[0037] Figure 1B A schematic diagram of a power network in a channel region between SRAMs is shown. Figure 1B As shown, the channel area between SRAMs is small, and power network resources are limited, for example, Figure 1B The diagram shows three layers of signal lines in the channel region between SRAMs. Dashed line 1021 represents one layer of signal lines, dashed line 1022 represents one layer of signal lines, and solid line 1023 represents one layer of signal lines.

[0038] For example, each layer of signal lines includes signal lines extending in the horizontal direction and signal lines extending in the vertical direction, and signal lines in different layers can be electrically connected through vias.

[0039] It should be noted that, Figure 1A and Figure 1B The signal lines shown are merely illustrative; in actual chips, there can be many more layers of signal lines.

[0040] Figure 1CA hotspot diagram is shown where the voltage drop in the channel region between SRAMs is greater than 10%. (Example) Figure 1C As shown, the elliptical circle represents the weak point (i.e., the point where the voltage drop is greater than 10%), based on... Figure 1C It is known that the weakness of voltage drop mainly occurs at the edge of the channel region. The main reasons include: First, the integrity of the power network at the edge of the channel region is poor; Second, for timing considerations and to minimize the routing, Electronic Design Automation (EDA) tools generally place the standard cells of large drives (such as inverters, buffers, etc.) at the very edge of the channel region (i.e., the edge of the channel region close to the SRAM), thus causing the standard cells of large drives to be clustered together.

[0041] Currently, there are various methods for repairing voltage drop. Table 1 below shows the various methods for repairing voltage drop, their principles, and limitations.

[0042] Table 1

[0043]

[0044]

[0045] Currently, in this field, the common method for repairing voltage drop in the channel region is to manually move the standard cell away from the area with large voltage drop. However, firstly, the effect of this repair method is relatively random, and secondly, it involves a lot of manual work and is not very efficient.

[0046] At least one embodiment of this disclosure provides a voltage drop repair method for a chip, which includes multiple standard cells. The voltage drop repair method includes: performing at least one repair operation on the multiple standard cells until the multiple standard cells meet a voltage drop convergence condition. Each repair operation includes: analyzing the multiple standard cells to determine at least one first standard cell, wherein the multiple standard cells include at least one first standard cell, and the dynamic voltage drop corresponding to each first standard cell is greater than a dynamic voltage drop threshold; for each first standard cell, moving the first standard cell between two via groups corresponding to the first standard cell; and performing a legal placement and rewinding operation on the at least one first standard cell.

[0047] The voltage drop repair method provided in the embodiments of this disclosure can move the first standard cell to a location with stronger power supply after determining the first standard cell, thereby realizing automated, efficient and rapid repair of dynamic voltage drop violation points (i.e. cells where the dynamic voltage drop is greater than the dynamic voltage drop threshold) in the chip, improving the voltage drop repair efficiency, reducing the impact of voltage drop on chip performance, and ensuring that the voltage drop meets the chip design requirements. At the same time, this voltage drop repair method can reduce or avoid the impact on timing and design rules during the repair process.

[0048] At least one embodiment of this disclosure also provides a voltage drop repair device, an electronic device, and a non-transient computer-readable storage medium. This voltage drop repair device can be used to implement the voltage drop repair method provided in the embodiments of this disclosure, and the device can be configured on an electronic device. The electronic device can be a personal computer, a mobile terminal, etc., and the mobile terminal can be a hardware device such as a mobile phone or tablet computer.

[0049] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings; however, this disclosure is not limited to these specific embodiments. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted.

[0050] Figure 2 This is a schematic flowchart illustrating a voltage drop repair method provided in at least one embodiment of the present disclosure. Figure 3 This is a schematic diagram of a chip provided for at least one embodiment of the present disclosure.

[0051] The voltage drop repair method provided in the embodiments of this disclosure can be used to repair voltage drops in chips, and this method can automatically and quickly repair voltage drops in chips. For example, this voltage drop repair method can be applied in the chip design process.

[0052] like Figure 3 As shown, in some embodiments, chip 300 includes a plurality of standard units 302, which are disposed within a voltage drop repair region 301. For example, each rectangular block in the voltage drop repair region 301 is a schematic representation of the plurality of standard units 302. It should be noted that in... Figure 3 The dashed rectangle used to illustrate the voltage drop repair area 301 is merely illustrative; the actual chip does not have a specific lined partition of the voltage drop repair area 301.

[0053] For example, in some embodiments, such as Figure 3As shown, the chip 300 also includes a base layer 310 and multiple module units 311, with the multiple module units 311 and multiple standard units 302 all disposed on the base layer 310. The multiple module units 311 are arranged in an array on the base layer 310 along a first direction X and a second direction Y to form multiple module unit columns, and the voltage drop repair region 301 includes a channel region between two adjacent module unit columns. Figure 3 Six module units 311a to 311f are shown. Module units 311a, 311c and 311e are arranged along the second direction Y to form a module unit column (hereinafter referred to as the first module unit column). Module units 311b, 311d and 311f are arranged along the second direction Y to form a module unit column (hereinafter referred to as the second module unit column). The first module unit column and the second module unit column are arranged along the first direction X. The voltage drop repair region 301 is located between the first module unit column and the second module unit column.

[0054] For example, multiple module units 311 include static random access memory, etc. In some examples, multiple module units 311 are all static random access memory (SRAM). The routing resources in the channel area between static random access memory are limited. The voltage drop repair method provided by the embodiments of this disclosure can perform voltage drop repair operation on standard cells in the channel area between SRAM with limited routing layout resources, automatically and efficiently repairing the voltage drop of standard cells in the channel area without damaging timing or causing unnecessary design rule violations.

[0055] like Figure 2 As shown, the voltage drop repair method includes step S100.

[0056] S100: Perform at least one repair operation on multiple standard cells until the multiple standard cells meet the voltage drop convergence condition.

[0057] For example, such as Figure 2 As shown, in some embodiments, each repair operation includes:

[0058] S200: Analyze multiple standard cells to determine at least one first standard cell.

[0059] S201: For each first standard unit, move the first standard unit to the two via groups corresponding to the first standard unit.

[0060] S202: Perform a valid placement and rewinding operation on at least one first standard cell.

[0061] For example, in step S200, the plurality of standard units include at least one first standard unit, and the dynamic voltage drop corresponding to each first standard unit is greater than the dynamic voltage drop threshold.

[0062] For example, in step S200, the analysis may include voltage drop analysis and drive capability analysis. For instance, a voltage drop analysis tool (e.g., EDA) can be used to perform voltage drop analysis on multiple standard cells, employing a dynamic rail vectorless analysis mode to find standard cells in the voltage drop repair region 301 whose dynamic voltage drop is greater than a dynamic voltage drop threshold. For example, the dynamic voltage drop threshold can be 10% * supply voltage, but this disclosure is not limited to this; the dynamic voltage drop threshold can also be 15% * supply voltage, 8% * supply voltage, etc. The dynamic voltage drop threshold can be set according to actual conditions. For example, the dynamic voltage drop threshold can be set according to the chip size, type, application scenario, and the type and size of the standard cells.

[0063] For example, in some embodiments, step S200 may include: performing voltage drop analysis on multiple standard cells to determine N standard cells whose dynamic voltage drop is greater than a dynamic voltage drop threshold, where N is a positive integer; performing drive capability analysis on the N standard cells to determine the standard cells among the N standard cells whose drive capability meets the drive capability condition as at least one first standard cell.

[0064] For example, in some embodiments, at least one first standard unit includes an inverter and / or a buffer, etc.

[0065] The voltage drop repair method provided in the embodiments of this disclosure can repair the voltage drop of inverters and / or buffers in large drives, thereby reducing the voltage drop of standard units such as inverters and / or buffers in large drives and ensuring that standard units such as inverters and / or buffers in large drives work normally.

[0066] For example, in some embodiments, multiple standard units 302 are inverters and / or buffers, etc. In this case, when determining at least one first standard unit, the standard unit with a dynamic voltage drop greater than the dynamic voltage drop threshold can be directly used as at least one first standard unit.

[0067] For example, the driving capability condition can be represented by a standard cell with a driving capability greater than D10 as the first standard cell.

[0068] It should be noted that, in this disclosure, "first standard cell" refers to a standard cell whose dynamic voltage drop is greater than the dynamic voltage drop threshold and whose driving capability meets the driving capability conditions.

[0069] Figure 4 This is a schematic diagram of a voltage repair region on a chip provided in at least one embodiment of the present disclosure. Figures 5A to 5DThis is a schematic diagram of a first standard unit and a via assembly provided for at least one embodiment of the present disclosure.

[0070] like Figure 4 As shown, multiple standard units 302 are indicated by white rectangular frames. These multiple standard units 302 are typically located at the edge of the voltage drop repair region 301. For example, these multiple standard units 302 are all standard units with a driving capability greater than D10.

[0071] For example, step S201 may include: determining two through-hole groups based on the position of the first standard unit; moving the first standard unit such that the orthographic projection of the first standard unit on the substrate covers part of the orthographic projection of the centerline between the two through-hole groups on the substrate.

[0072] For example, the two through-hole groups can be two through-hole groups adjacent to the first standard unit.

[0073] For example, in some embodiments, chip 300 may further include a power network disposed on substrate 310. The power network is configured to deliver power voltage to multiple standard cells, and includes multiple via groups, such as... Figure 5A and Figure 5B As shown, the multiple through-hole groups include a first through-hole group Via1, a second through-hole group Via2, and a third through-hole group Via3; as... Figure 5C and Figure 5D As shown, the multiple through-hole groups include a first through-hole group Via1, a second through-hole group Via2, a third through-hole group Via3, and a fourth through-hole group Via4.

[0074] For example, multiple through-hole groups and multiple standard units are not located on the same layer, but in the direction perpendicular to the base layer 310, the multiple through-hole groups are the through-hole groups closest to the multiple standard units.

[0075] For example, each of the multiple through-hole groups includes multiple through-holes, the multiple through-hole groups are arranged along a first direction, and the multiple through-holes in each through-hole group are arranged along a second direction, such as... Figure 5A and Figure 5B As shown, the first through-hole group Via1, the second through-hole group Via2, and the third through-hole group Via3 are arranged in the first direction X. Each of the first through-hole group Via1, the second through-hole group Via2, and the third through-hole group Via3 has multiple through-holes (in...) Figure 5A and Figure 5B (Using ellipses to represent them) arranged along the second direction Y.

[0076] For example, in some embodiments, determining two via groups based on the position of the first standard unit includes: determining M via groups from a plurality of via groups whose distance from the first standard unit in a first direction is less than or equal to a distance threshold, based on the position of the first standard unit; and determining two via groups from the M via groups. For example, M is a positive integer greater than or equal to 2, and the M via groups are arranged along the first direction.

[0077] For example, after determining the first standard cell, a group of through holes can be found within a certain range (determined based on a distance threshold) near the first standard cell in the first direction, and then two groups of through holes corresponding to the first standard cell can be determined based on the found groups of through holes.

[0078] For example, the distance threshold can be set according to the actual situation, and the standard for determining the distance threshold is strongly related to the power supply design of the chip. This standard can be the distance threshold being slightly greater than twice the spacing between two adjacent via groups in the PG (power good) network.

[0079] For example, in some embodiments, determining two through-hole groups from M through-hole groups includes: in response to M being 3, selecting two through-hole groups from the M through-hole groups that have the smallest sum of distances to the first standard cell in a first direction and are located on the same side of the first standard cell as two through-hole groups; in response to M being 2, selecting M through-hole groups as two through-hole groups.

[0080] If M equals 3, it means that the first standard unit is in a region with weak power supply, and the first standard unit can be moved to a region with strong power supply. For example, the first standard unit can be moved to the side with more than or equal to 2 via groups.

[0081] If M equals 2, it means that the first standard unit can be moved to the middle of the two through-hole groups in areas with weak power supply.

[0082] If M is greater than or equal to 4, meaning the number of via groups whose distance from the first standard unit in the first direction is less than or equal to a distance threshold is greater than or equal to 4, it indicates that the first standard unit is already in a position with strong power supply and does not need to be moved. It should be noted that this disclosure is not limited to this. In some embodiments, when M is greater than or equal to 4, the first standard unit can also be moved. For example, the first standard unit can be moved to the middle of the two via groups closest to the first standard unit on the side with more via groups; if the number of via groups on both sides of the first standard unit is the same, the first standard unit can be moved to the middle of the two via groups with the smallest sum of distances from the first standard unit in the first direction and located on the same side of the first standard unit.

[0083] If the number of via groups whose distance from the first standard cell in the first direction is less than or equal to the distance threshold is less than 2, it indicates that the power supply network near the first standard cell is abnormal. It may be necessary to open the layout for investigation. The machine does not move the first standard cell, that is, it does not perform any operation.

[0084] The following explains the cases where M is 3 and 2.

[0085] For example, in some embodiments, the first standard unit is not located between any two via groups, such as Figure 5A As shown, in one example, in the first direction X, the distance between the first standard unit 302a and the first via group Via1 is less than the distance threshold Dth, the distance between the first standard unit 302a and the second via group Via2 is also less than the distance threshold Dth, and the distance between the first standard unit 302a and the third via group Via3 is greater than the distance threshold Dth. In this case, it can be determined that the number of via groups whose distance to the first standard unit 302a in the first direction X is less than or equal to the distance threshold is 2, i.e., M is 2. The first via group Via1 and the second via group Via2 are the two via groups corresponding to the first standard unit 302a, thus moving the first standard unit 302a between the first via group Via1 and the second via group Via2; as shown... Figure 5B As shown, in another example, in the first direction X, the distance between the first standard unit 302b and the first via group Via1 is less than the distance threshold Dth, the distance between the first standard unit 302b and the second via group Via2 is also less than the distance threshold Dth, and the distance between the first standard unit 302b and the third via group Via3 is also less than the distance threshold Dth. In this case, it can be determined that the number of via groups whose distance to the first standard unit 302b in the first direction X is less than or equal to the distance threshold is 3, i.e., M is... 3. Since the sum of the distances between the first standard unit 302b and the first through-hole group Via1 and the first standard unit 302b and the second through-hole group Via2 is the smallest, and the first through-hole group Via1 and the second through-hole group Via2 are located on the same side (right side) of the first standard unit 302b, the first through-hole group Via1 and the second through-hole group Via2 are the two through-hole groups corresponding to the first standard unit 302b, thereby moving the first standard unit 302b between the first through-hole group Via1 and the second through-hole group Via2.

[0086] For example, in some embodiments, the first standard unit is located between two via groups, such as Figure 5C and Figure 5D As shown, the first standard unit 302c is located between the second through-hole group Via2 and the third through-hole group Via3. Figure 5CAs shown, in one example, the distance between the first standard unit 302c and the first via group Via1 is greater than the distance threshold Dth; the distance between the first standard unit 302c and the second via group Via2 is less than the distance threshold Dth; the distance between the first standard unit 302c and the third via group Via3 is less than the distance threshold Dth; and the distance between the first standard unit 302c and the fourth via group Via4 is greater than the distance threshold Dth. In this case, it can be determined that the number of via groups whose distance from the first standard unit 302c in the first direction X is less than or equal to the distance threshold is 2, i.e., M is 2. The second via group... Hole group Via2 and third through-hole group Via3 are two through-hole groups corresponding to the first standard unit 302c, thereby moving the first standard unit 302c to between the second through-hole group Via2 and the third through-hole group Via3, for example, to the center point between the second through-hole group Via2 and the third through-hole group Via3. It should be noted that if the first standard unit 302c is located at the center point between the second through-hole group Via2 and the third through-hole group Via3, the first standard unit 302c does not need to be moved, or the first standard unit 302c can be moved a preset distance towards the second through-hole group Via2 or the third through-hole group Via3; for example... Figure 5D As shown, the distance between the first standard unit 302d and the first through-hole group Via1 is greater than the distance threshold Dth; the distance between the first standard unit 302d and the second through-hole group Via2 is less than the distance threshold Dth; the distance between the first standard unit 302d and the third through-hole group Via3 is also less than the distance threshold Dth; and the distance between the first standard unit 302d and the fourth through-hole group Via4 is also less than the distance threshold Dth. Therefore, it can be determined that the number of through-hole groups whose distance to the first standard unit 302d in the first direction X is less than or equal to the distance threshold is 3, i.e., M is 3. Although, in the first direction X, the distance between the first standard unit 302d and the second through-hole group... The sum of the distances between Via2 and the distance between the first standard unit 302d and the third through-hole group Via3 is minimized. However, since the second through-hole group Via2 and the third through-hole group Via3 are located on both sides of the first standard unit 302d, the second through-hole group Via2 and the third through-hole group Via3 do not meet the condition. The third through-hole group Via3 and the fourth through-hole group Via4 are located on the same side of the first standard unit 302d, for example, on the right side. The third through-hole group Via3 and the fourth through-hole group Via4 are the two through-hole groups corresponding to the first standard unit 302d, thereby moving the first standard unit 302d between the third through-hole group Via3 and the fourth through-hole group Via4.

[0087] exist Figures 5A to 5DIn the diagram, the first standard unit 302a / 302b / 302c / 302d before the movement is shown as a solid rectangle, and the first standard unit 302a / 302b / 302c / 302d after the movement is shown as a dashed rectangle.

[0088] For example, in some embodiments, the first standard unit can be moved to any position between its corresponding two via groups.

[0089] For example, in some embodiments, for algorithmic simplicity, the first standard unit can be moved to the midpoint between the two through-hole groups. After moving the first standard unit, the orthographic projection of the center point of the first standard unit on the substrate lies within the orthographic projection of the centerline between the two through-hole groups on the substrate. In this case, in step S201, as... Figure 5A As shown, for a first standard unit 302a, two via groups via1 and via2 adjacent to the first standard unit 302a can be found in the first direction X. Then, the midpoint M of the two via groups via1 and via2 is determined, and the first standard unit 302a is moved horizontally along the first direction X to the midpoint M, for example, so that the center point of the first standard unit 302a is aligned with the midpoint M.

[0090] For example, such as Figure 5A As shown, the line connecting the center point of the first standard unit 302a (shown in solid rectangle) before the first standard unit 302a is moved and the center point of the first standard unit 302a (shown in dashed rectangle) after the first standard unit 302a is moved is parallel to the first direction X.

[0091] For example, in step S202, after all at least one first standard cell has been moved, the at least one first standard cell can be legalized and re-ecorated to reduce design rule violations. Finally, after performing the repair operation, a voltage drop analysis tool is used to perform voltage drop analysis on the multiple standard cells to analyze whether the voltage drop of the multiple standard cells meets the voltage drop convergence condition.

[0092] For example, such as Figure 5A As shown, if the first standard unit 302a overlaps with one or more signal lines after the first standard unit 302a is moved, the first standard unit 302a is invalid and the signal lines on the chip 300 need to be rewound to avoid the situation where the first standard unit 302a overlaps with one or more signal lines.

[0093] For example, in some embodiments, the voltage drop convergence condition can be that the number of first standard cells in a plurality of standard cells before performing at least one repair operation is less than the number of first standard cells in a plurality of standard cells after performing at least one repair operation.

[0094] For example, in some embodiments, each repair operation further includes: analyzing multiple standard cells (including voltage drop analysis and drive capability analysis) after performing the repair operation to determine the number of first standard cells among the multiple standard cells after performing the repair operation, to obtain a first number; determining the number of first standard cells among the multiple standard cells before performing at least one repair operation, to obtain a second number; in response to the first number being less than the second number, determining that the multiple standard cells meet the voltage drop convergence condition, thereby ending the repair process of voltage drop repair on the chip; in response to the first number being greater than or equal to the second number, determining that the multiple standard cells do not meet the voltage drop convergence condition, thereby continuing to perform the next repair operation until the multiple standard cells meet the voltage drop convergence condition.

[0095] For example, multiple standard cells can be analyzed (including voltage drop analysis and drive capability analysis) before performing at least one repair operation to determine the second quantity.

[0096] For example, in some embodiments, by applying the voltage drop repair method provided in this disclosure, the number of violation points (i.e., the first standard unit) with a voltage drop greater than 10% (i.e., the dynamic voltage drop threshold is 10% * supply voltage) in the voltage drop repair area is reduced from 2844 to 2378, a reduction of 16%.

[0097] Figure 6A and Figure 6C This is a schematic diagram of a voltage repair region before a repair operation is performed, provided in at least one embodiment of this disclosure. Figure 6B and Figure 6D This is a schematic diagram of a voltage repair region after a repair operation has been performed, provided for at least one embodiment of this disclosure. Figure 6B Indicates to Figure 6A The diagram shown illustrates the voltage repair region obtained after performing the repair operation provided in the embodiments of this disclosure. Figure 6D Indicates to Figure 6C The diagram shown is a schematic of the voltage repair area obtained after performing the repair operation provided in the embodiments of this disclosure. Figures 6A to 6D The elliptical region in the diagram represents the area where the violation occurred.

[0098] contrast Figure 6A and Figure 6B and comparison Figure 6C and Figure 6DIt can be seen that the number of violation points in the voltage drop repair area after the repair operation is performed is significantly less than the number of violation points in the voltage drop repair area before the repair operation is performed.

[0099] The voltage drop repair method provided in the embodiments of this disclosure has a small impact on timing and design rule check (DRC). For example, in one experiment, before voltage drop repair, the design rule check showed that there were 49 violations. After voltage drop repair, the design rule check showed that there were 45 violations. This shows that voltage drop repair has a small impact on DRC.

[0100] The voltage drop repair method provided by the embodiments of this disclosure can automatically and efficiently repair voltage drops, while hardly impairing timing performance and causing unnecessary design rule violations.

[0101] Figure 7 A schematic block diagram of an electronic device provided for at least one embodiment of this disclosure.

[0102] At least one embodiment of this disclosure also provides an electronic device, such as... Figure 7 As shown, the electronic device 700 may include at least one memory 701 and at least one processor 702. It should be noted that the components of the electronic device 700 described above are merely exemplary and not limiting. Depending on the actual application requirements, the electronic device 700 may also have other components, and the embodiments disclosed herein do not impose specific limitations on this.

[0103] For example, at least one memory 701 is used to non-transiently store computer-executable instructions; at least one processor 702 is configured to run the computer-executable instructions. The computer-executable instructions are executed by the at least one processor 702 to implement at least one step in the voltage drop repair method according to any embodiment of this disclosure. For specific implementations and related explanations of the various steps of the voltage drop repair method, please refer to the embodiments of the voltage drop repair method described above; repeated details will not be elaborated here.

[0104] For example, the memory 701 and the processor 702 can communicate with each other directly or indirectly. For example, in some embodiments, the electronic device 700 may also include a communication interface and a communication bus. The memory 701, processor 702, and communication interface can communicate with each other via the communication bus. Components such as the memory 701, processor 702, and communication interface can also communicate via a network connection, which may include a wireless network, a wired network, and / or any combination of wireless and wired networks. This disclosure does not limit the type and function of the network.

[0105] For example, a communication bus can be a Peripheral Component Interconnect Standard (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. This communication bus can be divided into address bus, data bus, control bus, etc.

[0106] For example, a communication interface is used to enable communication between electronic device 700 and other devices. The communication interface can be a Universal Serial Bus (USB) interface, etc.

[0107] For example, memory 701 and processor 702 can be located on the server side (or in the cloud).

[0108] For example, processor 702 can control other components in electronic device 700 to perform desired functions. The processor can be a central processing unit (CPU), graphics processing unit (GPU), network processor (NP), etc.; the processor can also be other forms of processing units with data processing capabilities and / or program execution capabilities, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), tensor processing units (TPUs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The central processing unit (CPU) can be based on x86 or ARM architectures, etc.

[0109] For example, memory 701 can be a computer-readable storage medium and can include any combination of one or more computer program products. The computer program products can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory can include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory can include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer-readable instructions can be stored on the computer-readable storage medium, and processor 702 can execute the computer-readable instructions to implement various functions of electronic device 700. Various application programs and various data can also be stored in the storage medium.

[0110] For the technical effects that electronic device 700 can achieve, please refer to the relevant descriptions in the embodiments of the voltage drop repair method described above. Repeated descriptions will not be repeated here.

[0111] Figure 8 This is a schematic block diagram of a voltage drop repair device provided for at least one embodiment of the present disclosure.

[0112] At least one embodiment of this disclosure also provides a voltage drop repair device for repairing voltage drops in a chip. Figure 8 As shown, the voltage drop repair device 710 may include a repair module 711, which may include an analysis module 7110, a movement module 7111, and a legal placement module 7112. Figure 8 The components and structure of the voltage drop repair device 710 shown are merely exemplary and not limiting. The voltage drop repair device 710 may also include other components and structures as needed.

[0113] For example, the chip includes multiple standard cells, and the repair module 711 is configured to perform at least one repair operation on the multiple standard cells until the multiple standard cells meet the voltage drop convergence condition. The repair module 711 can be used to implement step S100 in the voltage drop repair method described above.

[0114] In each repair operation, the analysis module 7110 is configured to analyze multiple standard cells to determine at least one first standard cell, wherein the multiple standard cells include at least one first standard cell, and the dynamic voltage drop corresponding to each first standard cell is greater than the dynamic voltage drop threshold; the movement module 7111 is configured to move the first standard cell to between the two via groups corresponding to the first standard cell for each first standard cell; and the legal placement module 7112 is configured to perform legal placement and rewinding operations on at least one first standard cell.

[0115] Analysis module 7110 can be used to implement step S200 in the voltage drop repair method described above; moving module 7111 can be used to implement step S201 in the voltage drop repair method described above; and legal placement module 7112 can be used to implement step S202 in the voltage drop repair method described above. For a detailed explanation of the functions implemented by analysis module 7110, please refer to the embodiments of the voltage drop repair method described above. Figure 2 The description of step S200 shown, and the specific explanation of the function implemented by the moving module 7111, can be found in the embodiments of the voltage drop repair method described above. Figure 2 The description of step S201 shown, and the specific explanation of the function implemented by the legal placement module 7112, can be found in the embodiments of the voltage drop repair method described above. Figure 2 The relevant description of step S202 shown.

[0116] For example, at least one first standard unit includes an inverter and / or a buffer.

[0117] For example, the chip also includes a base layer and multiple module units, which are arrayed on the base layer to form multiple module unit columns. Multiple standard units are located in a voltage drop repair region, which includes a channel region between two adjacent module unit columns.

[0118] For example, each module unit includes static random access memory.

[0119] For example, the analysis module 7110 includes a voltage drop analysis submodule and a drive capability analysis submodule. The voltage drop analysis submodule is configured to perform voltage drop analysis on multiple standard units to determine N standard units whose dynamic voltage drop is greater than the dynamic voltage drop threshold, where N is a positive integer. The drive capability analysis submodule is configured to perform drive capability analysis on the N standard units to determine the standard units among the N standard units whose drive capability meets the drive capability condition as the at least one first standard unit.

[0120] For example, multiple standard units are set on the base layer, and the moving module 7111 includes a through-hole group determining submodule and a moving submodule. The through-hole group determining submodule is configured to determine two through-hole groups based on the position of the first standard unit; the moving submodule is configured to move the first standard unit such that the orthographic projection of the first standard unit on the base layer covers the portion of the orthographic projection of the centerline between the two through-hole groups on the base layer.

[0121] For example, in one embodiment, after the first standard unit is moved, the orthographic projection of the center point of the first standard unit on the substrate lies within the orthographic projection of the centerline between the two through-hole groups on the substrate.

[0122] For example, two through-hole groups are arranged along a first direction, and the line connecting the center point of the first standard unit before the first standard unit is moved and the center point of the first standard unit after the first standard unit is moved is parallel to the first direction.

[0123] For example, the chip also includes a power network configured to transmit power voltage to a plurality of standard cells. The power network includes a plurality of via groups, which are the via groups closest to the plurality of standard cells in a direction perpendicular to the substrate. The plurality of via groups are arranged along a first direction, and each of the plurality of via groups includes a plurality of vias arranged along a second direction.

[0124] When performing the operation of determining two via groups based on the position of the first standard unit, the via group determination submodule is configured to: determine M via groups from multiple via groups whose distance from the first standard unit in the first direction is less than or equal to a distance threshold, based on the position of the first standard unit, where M is a positive integer greater than or equal to 2; and determine two via groups from the M via groups.

[0125] For example, when performing the operation of determining two via groups from M via groups, the via group determination submodule is configured to: in response to M being 3, determine the two via groups from the M via groups that have the smallest sum of distances to the first standard cell in the first direction and are located on the same side of the first standard cell as two via groups; in response to M being 2, determine the M via groups as two via groups.

[0126] For example, the voltage drop convergence condition is that the number of the first standard cells in a plurality of standard cells before performing at least one repair operation is less than the number of the first standard cells in a plurality of standard cells after performing at least one repair operation.

[0127] For example, the repair module also includes a judgment module, wherein in each repair operation: the analysis module 7110 is further configured to: analyze multiple standard cells (including voltage drop analysis and drive capability analysis) after performing the repair operation, determine the number of first standard cells among the multiple standard cells after performing the repair operation, to obtain a first number; and determine the number of first standard cells among the multiple standard cells before performing at least one repair operation, to obtain a second number. The judgment module is configured to: determine that the multiple standard cells satisfy the voltage drop convergence condition in response to the first number being less than the second number.

[0128] For example, the aforementioned modules (repair module 711, analysis module 7110, movement module 7111, legal placement module 7112, and / or judgment module) and / or sub-modules (voltage drop analysis sub-module, drive capability analysis sub-module, via group determination sub-module, and / or movement sub-module) can be hardware, software, firmware, or any feasible combination thereof. For example, the aforementioned modules and / or sub-modules can be dedicated or general-purpose circuits, chips, or devices, or a combination of a processor and memory. The embodiments of this disclosure do not limit the specific implementation of the aforementioned modules and sub-modules.

[0129] The voltage drop repair device can achieve similar or the same technical effects as the aforementioned voltage drop repair method, and will not be described in detail here.

[0130] Figure 9 This is a schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. For example, such as... Figure 9 As shown, one or more computer-executable instructions 801 may be stored non-transitory on a non-transitory computer-readable storage medium 80. For example, when the computer-executable instructions 801 are executed by a processor, one or more steps in the voltage drop repair method according to any embodiment of this disclosure may be performed.

[0131] For example, the non-transitory computer-readable storage medium 80 can be used in the electronic device 700 described above. For example, the non-transitory computer-readable storage medium 80 may include the memory 701 in the electronic device 700 described above.

[0132] For example, a description of the non-transitory computer-readable storage medium 80 can be found in the description of the memory 701 in the embodiments of the electronic device 700, and will not be repeated here.

[0133] The following is for reference. Figure 10 , Figure 10 A schematic diagram of another electronic device 900 suitable for implementing embodiments of the present disclosure is shown. The electronic device 900 can be a terminal device (e.g., a computer) or a processor, and can be used to execute the voltage drop repair method of the above embodiments. The electronic device 900 in the embodiments of the present disclosure can include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, personal digital assistants (PDAs), portable Android devices (PADs), portable multimedia players (PMPs), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable electronic devices, etc., as well as fixed terminals such as digital TVs, desktop computers, smart home devices, etc. Figure 10 The electronic device 900 shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0134] like Figure 10 As shown, electronic device 900 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 901, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 902 or a program loaded from storage device 908 into random access memory (RAM) 903. RAM 903 also stores various programs and data required for the operation of electronic device 900. Processing device 901, ROM 902, and RAM 903 are interconnected via bus 904. Input / output (I / O) interface 905 is also connected to bus 904.

[0135] Typically, the following devices can be connected to I / O interface 905: input devices 906 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 907 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 908 including, for example, magnetic tapes, hard disks, etc.; and communication devices 909. Communication device 909 allows electronic device 900 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 10 An electronic device 900 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0136] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts to execute one or more steps in the voltage drop repair method described above. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 909, or installed from a storage device 908, or installed from a ROM 902. When the computer program is executed by a processing device 901, the processing device 901 can perform the functions defined in the voltage drop repair method of the embodiments of this disclosure.

[0137] It should be noted that, in the context of this disclosure, a computer-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, capable of transmitting, propagating, or transmitting a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination of the aforementioned media.

[0138] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0139] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0140] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0141] The units described in the embodiments of this disclosure can be implemented in software or hardware. For example, the name of a unit does not necessarily limit the unit itself.

[0142] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0143] In a first aspect, according to one or more embodiments of this disclosure, a voltage drop repair method is provided for repairing the voltage drop of a chip, the chip comprising a plurality of standard cells, wherein the voltage drop repair method comprises: performing at least one repair operation on the plurality of standard cells until the plurality of standard cells meet a voltage drop convergence condition, wherein each repair operation comprises: analyzing the plurality of standard cells to determine at least one first standard cell, wherein the plurality of standard cells includes the at least one first standard cell, and the dynamic voltage drop corresponding to each first standard cell is greater than a dynamic voltage drop threshold; for each first standard cell, moving the first standard cell to between two via groups corresponding to the first standard cell; and performing a legal placement and rewinding operation on the at least one first standard cell.

[0144] According to one or more embodiments of this disclosure, the chip further includes a base layer, the plurality of standard units are disposed on the base layer, and moving the first standard unit between two via groups corresponding to the first standard unit includes: determining the two via groups based on the position of the first standard unit; moving the first standard unit such that the orthographic projection of the first standard unit on the base layer covers a portion of the orthographic projection of the centerline between the two via groups on the base layer.

[0145] According to one or more embodiments of this disclosure, the orthographic projection of the center point of the first standard unit on the substrate lies within the orthographic projection of the centerline between the two through-hole groups on the substrate.

[0146] According to one or more embodiments of this disclosure, the chip further includes a power network configured to transmit power voltage to the plurality of standard cells. The power network includes a plurality of via groups, wherein the plurality of via groups are the via groups closest to the plurality of standard cells in a direction perpendicular to the substrate. The plurality of via groups are arranged along a first direction, and each of the plurality of via groups includes a plurality of vias arranged along a second direction. Determining the two via groups based on the position of the first standard cell includes: determining M via groups from the plurality of via groups whose distance from the first standard cell in the first direction is less than or equal to a distance threshold, where M is a positive integer greater than or equal to 2; and determining the two via groups from the M via groups.

[0147] According to one or more embodiments of this disclosure, determining the two through-hole groups from the M through-hole groups includes: in response to M being 3, selecting the two through-hole groups among the M through-hole groups that have the smallest sum of distances to the first standard unit in the first direction and are located on the same side of the first standard unit as the two through-hole groups; and in response to M being 2, selecting the M through-hole groups as the two through-hole groups.

[0148] According to one or more embodiments of this disclosure, the two through-hole groups are arranged along a first direction, and the line connecting the center point of the first standard unit before the first standard unit is moved and the center point of the first standard unit after the first standard unit is moved is parallel to the first direction.

[0149] According to one or more embodiments of this disclosure, the voltage drop convergence condition is that the number of first standard cells among the plurality of standard cells is less than the number of first standard cells among the plurality of standard cells after the at least one repair operation is performed.

[0150] According to one or more embodiments of this disclosure, each repair operation further includes: analyzing the plurality of standard units after performing the repair operation to determine the number of first standard units among the plurality of standard units after performing the repair operation, to obtain a first number; determining the number of first standard units among the plurality of standard units before performing the at least one repair operation, to obtain a second number; and determining that the plurality of standard units satisfy the voltage drop convergence condition in response to the first number being less than the second number.

[0151] According to one or more embodiments of this disclosure, analyzing the plurality of standard units to determine at least one first standard unit includes: performing voltage drop analysis on the plurality of standard units to determine N standard units whose dynamic voltage drop is greater than the dynamic voltage drop threshold, where N is a positive integer; performing drive capability analysis on the N standard units to determine the standard unit among the N standard units whose drive capability meets the drive capability condition as the at least one first standard unit.

[0152] According to one or more embodiments of the present disclosure, the chip further includes a base layer and a plurality of module units, the plurality of module units being arrayed on the base layer to form a plurality of module unit columns, the plurality of standard units being located within a voltage drop repair region, the voltage drop repair region including a channel region between two adjacent module unit columns.

[0153] According to one or more embodiments of this disclosure, each of the module units includes a static random access memory.

[0154] According to one or more embodiments of this disclosure, the at least one first standard unit includes an inverter and / or a buffer.

[0155] Secondly, according to one or more embodiments of this disclosure, a voltage drop repair device is used to repair the voltage drop of a chip, wherein the chip includes a plurality of standard cells, the voltage drop repair device includes a repair module, the repair module is configured to perform at least one repair operation on the plurality of standard cells until the plurality of standard cells meet the voltage drop convergence condition, wherein the repair module includes an analysis module, a movement module, and a legal placement module, in each repair operation: the analysis module is configured to analyze the plurality of standard cells to determine at least one first standard cell, wherein the plurality of standard cells include the at least one first standard cell, and the dynamic voltage drop corresponding to each first standard cell is greater than a dynamic voltage drop threshold; the movement module is configured to move the first standard cell to between two via groups corresponding to the first standard cell for each first standard cell; the legal placement module is configured to perform legal placement and rewinding operations on the at least one first standard cell.

[0156] Thirdly, according to one or more embodiments of the present disclosure, an electronic device includes: at least one memory storing computer-executable instructions non-transitory; and at least one processor configured to execute the computer-executable instructions, wherein the computer-executable instructions are executed by the at least one processor to implement the voltage drop repair method according to any embodiment of the present disclosure.

[0157] Fourthly, according to one or more embodiments of the present disclosure, a non-transitory computer-readable storage medium is provided, wherein the non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement the voltage drop repair method according to any embodiment of the present disclosure.

[0158] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0159] Furthermore, although the operations are described in a specific order, this should not be construed as requiring these...

[0160] Operations are performed in the specific order shown or in sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementations are included in the above discussion...

[0161] Details are provided, but these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0162] 0 Although this topic has been described using language specific to structural features and / or methodological logic,

[0163] However, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0164] The following points should be noted regarding this disclosure:

[0165] 5(1) The accompanying drawings of the embodiments disclosed herein only involve structures relevant to the embodiments disclosed herein; other structures are not included.

[0166] The structure can refer to a typical design.

[0167] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0168] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A voltage drop repair method for repairing voltage drop in a chip, wherein, The chip includes multiple standard units. The voltage drop repair method includes: Perform at least one repair operation on the plurality of standard cells until the plurality of standard cells meet the voltage drop convergence condition. Each repair operation includes: The plurality of standard units are analyzed to determine at least one first standard unit, wherein the plurality of standard units include the at least one first standard unit, and the dynamic voltage drop corresponding to each first standard unit is greater than the dynamic voltage drop threshold. For each first standard unit, move the first standard unit to the two via groups corresponding to the first standard unit; Perform a valid placement and rewinding operation on the at least one first standard unit; Moving the first standard unit to between the two via groups corresponding to the first standard unit includes: Based on the position of the first standard unit, M through-hole groups are determined from the plurality of through-hole groups whose distance from the first standard unit in the first direction is less than or equal to a distance threshold, where M is a positive integer greater than or equal to 2, and the plurality of through-hole groups are the through-hole groups closest to the plurality of standard units. In response to M being 3, the two through-hole groups with the smallest sum of distances to the first standard unit in the first direction and located on the same side of the first standard unit are selected as the two through-hole groups. In response to M being 2, the M through-hole groups are treated as the two through-hole groups.

2. The voltage drop repair method according to claim 1, wherein, The chip also includes a base layer, on which the plurality of standard units are disposed. Moving the first standard unit to between the two via groups corresponding to the first standard unit includes: The two through-hole groups are determined based on the position of the first standard unit; Move the first standard unit so that the orthographic projection of the first standard unit on the base layer covers the portion of the orthographic projection of the centerline between the two through-hole groups on the base layer.

3. The voltage drop repair method according to claim 2, wherein, The orthographic projection of the center point of the first standard unit on the base layer lies within the orthographic projection of the centerline between the two through-hole groups on the base layer.

4. The voltage drop repair method according to claim 2, wherein, The chip also includes a power network configured to transmit power voltage to the plurality of standard cells. The power network includes the plurality of through-hole groups, wherein, in the direction perpendicular to the substrate, the plurality of through-hole groups are the through-hole groups closest to the plurality of standard units. The plurality of through-hole groups are arranged along a first direction, and each of the plurality of through-hole groups includes a plurality of through-holes arranged along a second direction.

5. The voltage drop repair method according to claim 1, wherein, The two through-hole groups are arranged along the first direction. The line connecting the center point of the first standard unit before and after the first standard unit is moved is parallel to the first direction.

6. The voltage drop repair method according to any one of claims 1 to 5, wherein, The voltage drop convergence condition is that the number of the first standard cells in the plurality of standard cells is greater than the number of the first standard cells in the plurality of standard cells after the execution of the at least one repair operation.

7. The voltage drop repair method according to claim 6, wherein, Each repair operation also includes: After performing the repair operation, the plurality of standard units are analyzed to determine the number of the first standard units among the plurality of standard units after performing the repair operation, so as to obtain the first number; The number of first standard units among the plurality of standard units is determined before the at least one repair operation is performed, to obtain a second number; In response to the first quantity being less than the second quantity, it is determined that the plurality of standard units satisfy the voltage drop convergence condition.

8. The voltage drop repair method according to any one of claims 1 to 5, wherein, Analyzing the plurality of standard units to determine at least one first standard unit includes: Voltage drop analysis is performed on the plurality of standard cells to identify N standard cells whose dynamic voltage drop is greater than the dynamic voltage drop threshold, where N is a positive integer; The driving capability is analyzed among the N standard units, and the standard unit whose driving capability meets the driving capability condition is determined as the at least one first standard unit.

9. The voltage drop repair method according to any one of claims 1 to 5, wherein, The chip also includes a base layer and multiple module units, which are arranged in an array on the base layer to form multiple module unit columns. The multiple standard units are located within the voltage drop repair area, which includes the channel area between two adjacent module unit columns.

10. The voltage drop repair method according to claim 9, wherein, Each of the module units includes a static random access memory.

11. The voltage drop repair method according to any one of claims 1 to 5, wherein, The at least one first standard unit includes an inverter and / or a buffer.

12. A voltage drop repair device for repairing voltage drop in a chip, wherein, The chip includes multiple standard units. The voltage drop repair device includes a repair module configured to perform at least one repair operation on the plurality of standard units until the plurality of standard units meet the voltage drop convergence condition. The repair module includes an analysis module, a movement module, and a legal placement module. In each repair operation: The analysis module is configured to analyze the plurality of standard units to determine at least one first standard unit, wherein the plurality of standard units include the at least one first standard unit, and the dynamic voltage drop corresponding to each first standard unit is greater than a dynamic voltage drop threshold. The moving module is configured to move the first standard unit to between the two through-hole groups corresponding to the first standard unit for each first standard unit; The legal placement module is configured to perform legal placement and rewinding operations on the at least one first standard unit; Moving the first standard unit to between the two via groups corresponding to the first standard unit includes: Based on the position of the first standard unit, M through-hole groups are determined from the plurality of through-hole groups whose distance from the first standard unit in the first direction is less than or equal to a distance threshold, where M is a positive integer greater than or equal to 2, and the plurality of through-hole groups are the through-hole groups closest to the plurality of standard units. In response to M being 3, the two through-hole groups with the smallest sum of distances to the first standard unit in the first direction and located on the same side of the first standard unit are selected as the two through-hole groups. In response to M being 2, the M through-hole groups are treated as the two through-hole groups.

13. An electronic device, comprising: At least one memory stores computer-executable instructions non-transitory; At least one processor, configured to run the computer-executable instructions, The computer-executable instructions are executed by the at least one processor to implement the voltage drop repair method according to any one of claims 1 to 11.

14. A non-transitory computer-readable storage medium, wherein, The non-transitory computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the voltage drop repair method according to any one of claims 1 to 11.

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