A semiconductor-based lithography machine capacity planning method, system, device and medium

Abstract

The present application provides a method and system, equipment and medium for planning the capacity of semiconductor-based lithography machines, including: obtaining the number of machines and available capacity in the lithography area on the same day and process information of two types of work-in-progress from the MES system on the same day; obtaining the process information of the LOT to be put into production; constructing a mixed integer linear programming model with the daily load balance of the machines in the lithography area for 14 days as the goal, solving the key layer machine planning scheme of all LOTs and the load balance of the machines, and dispatching the LOTs with the system key layer machine labels to the corresponding lithography machines at different layers according to the lithography steps and label types during the processing; repeating the above steps every day. It can at least be used to solve the technical problem that the production strategy restricts the full utilization of the production efficiency of the lithography machine.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor-based lithography machine capacity planning method and system, equipment and medium. Background Art

[0002] In the production of 300mm 12-inch wafers, photolithography machines play a pivotal role. Due to the re-entry characteristics of semiconductor manufacturing, the photolithography area has always been the bottleneck area of ​​wafer processing plant (fab) production capacity. Photolithography machines are expensive, and the process is precise and complex. It is very important to arrange the production capacity of photolithography machines reasonably, and the planning of production capacity should take into account the needs and limitations of processed wafers.

[0003] As wafer manufacturing technology reaches a higher level of precision, the advanced IMM and ARF lithography machines in the lithography area have strict requirements for the consistency of critical dimensions (CD) between different layers of the wafer (the wafer returns to the lithography area for processing layer by layer. A wafer generally needs to go through hundreds of processing steps. It will return to the lithography area every 3-4 steps to change layers. The lithography step at this time is also called litho step, which is a sign of switching layers). In particular, the critical layers (critical layers) that have higher requirements for yield and precision in wafer layer-by-layer processing should ensure the alignment and connection (overlay matching) of their circuit patterns, otherwise it is easy to cause defective products. In practice, in order to maintain a good yield, when the first critical layer of the wafer is decided to be processed on a certain machine, all subsequent critical layers of the same processing capability type should be processed in this machine. This machine alignment between layers of a lot (wafer group) is called vertical machine limit. Because even machines of the same model still have certain differences in overlay / alignment accuracy, known as machine difference, vertical machine limits can ensure that all key layers of the same wafer are processed on the same machine, thereby preventing the increase of defects caused by machine differences and improving product yield. Therefore, it is necessary to consider the machine binding problem in the lithography area (referred to as the key layer machine planning problem).

[0004] However, the inventors found that there are at least the following technical problems in the related art:

[0005] There are currently two main ways to dispatch lithography machines: first, engineers query the MES system to obtain the current available status of the lithography machine, the available status and parameters of the mask, and the lot pool to be processed, and according to the engineer's experience, put the nearest mask and the wafer group using the mask into the corresponding machine. When the mask is far away, the next lot to be processed is determined based on experience and the required mask is transported. This simple manual dispatching method does not consider the relationship between the lot and the temperature change of the mask, and the decision on the next wafer group is too rough; another dispatching method is the real-time dispatching method, which calculates the priority ranking of the wafer group to be processed by considering the corresponding temperature layer value of the wafer group process and the required temperature of the mask, as well as the temperature layer difference between the wafer group to be processed and the wafer group being processed, thereby obtaining the real-time processing order of the wafer group and the mask on the machine. The real-time dispatching method solves the defects of the manual method, but only considering the difference in temperature layer values ​​without considering the vertical machine limit requirements of advanced process products may reduce wafer yield and another short-sighted problem: each decision only considers the consistency between the current processing status and the next processing status, without considering future consequences and the impact on the production capacity of the production lot. Such machine allocation decisions may cause machine load and imbalance, processing delays, and even machine waiting (idle) when the production lot re-enters the lithography area in the future, resulting in low production efficiency.

[0006] In view of the fact that traditional production strategies restrict the full utilization of the production efficiency of lithography machines, this paper proposes a mixed integer scheduling algorithm based on traditional capacity planning and machine dispatching methods, while taking into account the vertical machine limitation problem. A new production dispatch strategy for lots in the lithography area is given, which can not only meet the production quality of wafers in lithography machines, but also take into account the production efficiency of the equipment. Summary of the invention

[0007] One object of the present application is to provide a semiconductor-based lithography machine capacity planning method and system, equipment and medium, at least to solve the defects mentioned in the above-mentioned background technology.

[0008] To achieve the above objectives, some embodiments of the present application provide the following aspects:

[0009] In a first aspect, some embodiments of the present application further provide a semiconductor-based lithography machine capacity planning method, comprising the following steps:

[0010] On the day of decision making, obtain information from the MES system on the number of machines in the photolithography area, processing types, available capacity, and the target number of wafers processed per hour;

[0011] On the day of decision-making, the process information of the lots to be put into production is obtained from the MES system. The lots to be put into production are divided into two categories: the lots actually put into production today and the lots to be put into production in the next 13 days. The number of lots put into production every day in the future is predicted by statistical methods based on historical data;

[0012] On the day of decision making, obtain the lot process information currently in the processing pool and returning to the lithography area in the future from the MES system, including the key layer machine labels carried;

[0013] The above data are used as input parameters, and a mixed integer linear programming model is constructed with the goal of daily load balancing of the 14-day machine in the lithography area. The key layer machine planning scheme and machine load balancing of all lots are solved, and the lots with system key layer machine labels are dispatched to the corresponding lithography machines at different layers according to the lithography steps and label types during the processing process.

[0014] Repeat the above steps daily.

[0015] As a preferred technical solution of the present application: the processing types include IMM, ARF, KRF, and I_LINE.

[0016] As a preferred technical solution of the present application: the lot process information includes lot basic information, lithography processing time, total layer processing time, the wafer processing step currently in which the lot is located, and the key layer machine label carried by the lot.

[0017] As a preferred technical solution of the present application: in the step of obtaining the process information of the lot to be put into production, the serial number of the layer of the two types of lots in production and to be put into production on the processing route and the target processing type of the layer are also obtained.

[0018] As a preferred technical solution of the present application: in the step of constructing a mixed integer linear programming model with the daily load balancing of the machines in the lithography area for 14 days as the goal, a multi-objective solution for daily load balancing of each machine within 14 days is constructed:

[0019]

[0020] in, and They refer to the largest and smallest machine loads in the h-type machine group on the dth day, respectively. and They refer to the maximum load and minimum load of the machines in the H-type machine group within 14 days. and They respectively refer to the maximum load and minimum load of machine group k in 14 days.

[0021] As a preferred technical solution of the present application: the load balancing multi-objective solution satisfies the following constraints:

[0022] The wafers in each wafer group are returned to the lithography area layer by layer for processing and are processed on idle machines that meet the requirements of their processing type:

[0023]

[0024]

[0025] Among them, the binary decision variable x ijlk Indicates whether the l-th layer of the j-th lot of product i is allocated to machine k, which is 1 if yes and 0 if no; A hk Whether machine k has the hth type of processing capability, CR ilh Indicates whether product layer l requires type h capability, 1 if yes and 0 if no;

[0026] The returned wafer groups in the lot to be put into production and the processing pool all meet the following vertical machine limit constraints:

[0027]

[0028]

[0029]

[0030] Among them, CL il Indicates whether the layer l of product i is a key layer, which is 1 if it is and 0 if it is not. j1 indicates the lot put into production, dm ijhk and Indicates whether the first key layer of type h in the production lot and the production lot is assigned to machine k, which is 1 if yes and 0 if no; km ijhk Indicates that the i product jlot in production has been bound to the h type machine k. If yes, it is 1; if no, it is 0. j2 indicates the lot in production. CL il Indicates whether the layer l of product i is a key layer, 1 if yes and 0 if no;

[0031] The average daily processing time / wafer number / wph of the machine for all wafer groups to return to the lithography area for processing layer by layer meets the machine load capacity constraint:

[0032]

[0033]

[0034]

[0035] Among them, LoadT kd represents the time load of machine k in d days, p il represents the processing time of layer l of product i, LoadP kd represents the wafer load of machine k on day d, qij represents the number of wafers in product i jlot, W kd represents the available production time of machine k in d days, τ kd Represents the portion of the allocated load that exceeds the available time;

[0036]

[0037] Among them, R ild Indicates whether the arrival date of product i on level l is d days, where d represents the period from the 1st day to the dth day (d∈[1,…,14]), L i Indicates the total number of layers of product i, CT il represents the cycle time of product i at layer l, Indicates rounding up.

[0038] In a second aspect, some embodiments of the present application further provide a semiconductor-based lithography machine capacity planning system, including:

[0039] Machine data acquisition module: used to obtain the number of various types of machines in the photolithography area on that day, the processing type and available capacity, as well as the target number limit of wafers processed per hour;

[0040] WIP process information acquisition module: used to obtain two types of lot process information for the next 14 days, namely, the lot to be put into production and the lot to be re-entered into the lithography area after production. The wafer group returned from the processing pool obtains the re-entry date and the key layer machine label it carries.

[0041] Algorithm operation module: It is used to construct a mixed integer linear programming scheduling model to calculate the key layer machine optimization plan for all lots following the system settings, and transmit the results to the backend database;

[0042] Performance analysis module: used to perform secondary calculations based on the solution results of the algorithm operation module to obtain daily capacity allocation and load balancing indicators of all machines in the lithography area to analyze algorithm performance;

[0043] Execution module: used to allocate machines to different layers for all wafers in the lot pool according to the lithography step category and system label according to the algorithm results.

[0044] As a preferred technical solution of the present application: the algorithm operation module distinguishes whether the algorithm result is a key layer type, using the key layer machine field if it is a key layer type, and using the machine suggestion field if it is not a key layer type; and directly obtains the target machine information by screening the lot identification number and the layer's sequence number or processing capability type on its processing route; the algorithm operation module also analyzes the load fluctuation through the daily standard deviation of the load within each type of machine group; and at the same time, selects the time limit with the highest multi-objective optimization efficiency based on the algorithm result.

[0045] In a third aspect, some embodiments of the present application further provide a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method described above when executing the computer program.

[0046] In a fourth aspect, some embodiments of the present application further provide a computer-readable medium having computer program instructions stored thereon, wherein the computer program instructions can be executed by a processor to implement the method as described above.

[0047] Compared with the prior art, in the solution provided in the embodiment of the present application, the present application obtains the process information of all two types of work-in-progress through the MES system, including the production plan for the next 14 days and the number of layers that will be returned to the lithography area for processing layer by layer in different wafer groups in the processing pool that will re-enter the lithography area in the next 14 days, as well as the calculated re-entry date. It fully considers all possible loads and machine available capacity in the future period, and makes rolling decisions every day based on the latest actual production and machine availability. The machine capacity planning solution made in this way can ensure the long-term load balance and high utilization of the lithography machine, and is more practical and feasible.

[0048] This application considers the matching relationship between the reasonable machine type in the lithography area and the processing type required for each lot and layer process, and also considers the vertical machine limit constraints of the advanced process machine required for the key layer with higher requirements for accuracy and yield, to meet the machine consistency of the front and back processes of the bottleneck processing of high-precision products, reduce the difference in alignment accuracy caused by machine differences, ensure product production quality, and improve product yield. The capacity planning method proposed in this application makes a macro design from the perspective of long-term planning, and has a guiding function for the machine binding and machine capacity allocation of the advanced process of the product in the lithography area. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A flow chart of the method provided in the embodiment of the present application;

[0050] Figure 2 A system block diagram provided for an embodiment of the present application;

[0051] Figure 3 A schematic diagram of the vertical machine limit concept in the lithography machine capacity planning method provided in an embodiment of the present application;

[0052] Figure 4 A schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] Embodiment 1

[0055] The process includes:

[0056] Step S101, on the day of decision making, obtain information on the number of machines in the photolithography area, processing types and available capacity, as well as the target number of wafers processed per hour from the MES system;

[0057] Step S102, on the day of decision making, the process information of the lots to be put into production is obtained from the MES system. The lots to be put into production are divided into two categories: the lots actually put into production today and the lots to be put into production in the next 13 days. Here, the number of lots put into production every day in the future can be predicted based on historical data using statistical methods;

[0058] Step S103, on the day of decision making, obtain the lot process information of the lot currently in the processing pool that will return to the photolithography area in the future from the MES system, including the key layer machine label carried;

[0059] Step S104, using the above data as input parameters, building a mixed integer linear programming model with the goal of daily load balancing of the machines in the lithography area for 14 days, solving the key layer machine planning schemes and machine load balancing conditions for all lots, and dispatching the lots with system key layer machine labels to the corresponding lithography machines at different layers according to the lithography steps and label types during the processing process;

[0060] Step S105, repeating steps S101 to S104 every day.

[0061] In some embodiments of the present application, the processing types in S101 include IMM, ARF, KRF, and I_LINE.

[0062] In some embodiments of the present application, the lot process information in S102 includes lot basic information, lithography process time, total layer processing time, the wafer processing step currently in which the lot is located, and the key layer machine label carried by the lot.

[0063] In some embodiments of the present application, in S102, the serial numbers of the layers of the two types of lots, which are in production and to be put into production, and the target processing types of the layers in the processing route are also obtained.

[0064] In some embodiments of the present application, in S104, a multi-objective solution for daily load balancing of each machine within 14 days is constructed:

[0065]

[0066] in, and They refer to the largest and smallest machine loads in the h-type machine group on the dth day, respectively. and They refer to the maximum load and minimum load of the machines in the H-type machine group within 14 days. and They respectively refer to the maximum load and minimum load of machine group k in 14 days.

[0067] In some embodiments of the present application, the load balancing multi-objective solution satisfies the following constraints:

[0068] The wafers in each wafer group are returned to the lithography area layer by layer for processing and are processed on idle machines that meet the requirements of their processing type:

[0069]

[0070]

[0071] Among them, the binary decision variable x ijlk Indicates whether the l-th layer of the j-th lot of product i is allocated to machine k, which is 1 if yes and 0 if no; A hk Whether machine k has the hth type of processing capability, CR ilh Indicates whether product layer l requires type h capability, 1 if yes and 0 if no;

[0072] The returned wafer groups in the lot to be put into production and the processing pool all meet the following vertical machine limit constraints:

[0073]

[0074]

[0075]

[0076] Among them, CL il Indicates whether the layer l of product i is a key layer, which is 1 if it is and 0 if it is not. j1 indicates the lot put into production, dm ijhk and Indicates whether the first key layer of type h in the production lot and the production lot is assigned to machine k, which is 1 if yes and 0 if no; km ijhk Indicates that the i product jlot in production has been bound to the h type machine k. If yes, it is 1; if no, it is 0. j2 indicates the lot in production. CL il Indicates whether the layer l of product i is a key layer, 1 if yes and 0 if no;

[0077] The average daily processing time / wafer number / wph of the machine for all wafer groups to return to the lithography area for processing layer by layer meets the machine load capacity constraint:

[0078]

[0079]

[0080]

[0081] Among them, LoadT kd represents the time load of machine k in d days, p il represents the processing time of layer l of product i, LoadP kd represents the wafer load of machine k on day d, q ij represents the number of wafers in product i jlot, W kd represents the available production time of machine k in d days, τ kd Represents the portion of the allocated load that exceeds the available time;

[0082]

[0083] Among them, R ild Indicates whether the arrival date of product i on level l is d days, where d represents the period from the 1st day to the dth day (d∈[1,…,14]), L i Indicates the total number of layers of product i, CT il represents the cycle time of product i at layer l, Indicates rounding up.

[0084] Embodiment 2

[0085] The information and capacity usage of various machines in the current lithography area are obtained from the mes library. Whether machine k∈K has a certain processing capacity type h∈H (processing capacity type, divided into four types: IMM / ARF / KRF / I_LINE) is represented by a binary array A, which is 1 if it is and 0 if it is not; and the available capacity W of machine k on each day d is kd It is equal to the maximum daily capacity minus the unavailable time such as downtime and PM. It also obtains the process information of two types of work-in-progress. Work-in-progress refers to all wafer products being produced. The first type is the number of wafers cast in the lithography area in the next 14 days. The second type is the process information of the coming work-in-progress that will return to the lithography area in the future and the key layer machine (key layer machine) labels it carries. The number of wafers cast in the future can be estimated based on historical data using statistical methods such as time series prediction. It also obtains the process information of the lot currently in the processing pool based on the MES library, which mainly includes basic information such as product type, processing route, lot identification number, lithography process time (process time), layer total processing time (layer cycle time), and also includes the wafer processing step the lot is currently in and the key layer machine label it carries.

[0086] Get all the layer information of the two types of lots mentioned above, which are to be put into production and in production. In addition to basic information such as product type, it is also necessary to consider the layer serial number (layer_seq) in the lot processing route and the type of processing required by the layer. Among them, the critical dimensions (CD) of the layers of type IMM and ARF are required to be high. The machine alignment between the layers of a lot where the same type of critical layers need to be processed on the same machine is called vertical machine limit. Use the binary array CL il Indicates whether the layer l of product i is a key layer, 1 if yes and 0 if no; use the binary array CR ilh Indicates whether the i product l layer needs h type capacity, which is 1 if yes and 0 if no. Finally, according to the layercycletime, the expected arrival date of a layer can be obtained as the load action date:

[0087]

[0088] Among them, R ild Indicates whether the arrival date of product i on level l is d days, where d represents the period from the 1st day to the dth day (d∈[1,…,14]), L i Indicates the total number of layers of product i, CT il represents the cycle time of product i at layer l, Indicates rounding up.

[0089] To ensure that the layers of each wafer group that are processed in the photolithography area are processed layer by layer, they need to be processed on an available machine that meets the requirements of their processing type. Therefore, there are the following machine uniqueness and applicability constraints, where the binary decision variable x ijlk Indicates whether the l-th layer of the j-th lot of product i is allocated to machine k, which is 1 if yes and 0 otherwise.

[0090] Processing type required on idle machine:

[0091]

[0092]

[0093] Among them, the binary decision variable x ijlk Indicates whether the l-th layer of the j-th lot of product i is allocated to machine k, which is 1 if yes and 0 if no; A hk Whether machine k has the hth type of processing capability, CR ilh Indicates whether product layer l requires type h capability, 1 if yes and 0 if no;

[0094] It is also important that both the lot to be put into production and the returned wafer group in the processing pool must meet the following vertical machine dedication constraint, which can determine the key layer machine of the lot with key layers, that is, the machine for processing the IMM and ARF type layers respectively, and at the same time let the lot in production follow the key layer machine label of its own system; where dm ijhk and Indicates whether the first key layer of type h in the production lot and the in-production lot is assigned to machine k, which is 1 if yes and 0 otherwise.

[0095]

[0096]

[0097]

[0098] Among them, CL il Indicates whether the layer l of product i is a key layer, which is 1 if it is and 0 if it is not. j1 indicates the lot put into production, dm ijhk and Indicates whether the first key layer of type h in the production lot and the production lot is assigned to machine k, which is 1 if yes and 0 if no; km ijhk Indicates that the i product jlot in production has been bound to the h type machine k. If yes, it is 1; if no, it is 0. j2 indicates the lot in production. CL il Indicates whether the layer l of product i is a key layer, 1 if yes and 0 if no;

[0099] The third constraint is kmijhk =1, the corresponding allocation decision x ijlk It must satisfy the same machine k as the label; when km ijhk When = 0, the constraint will not take effect if the key layer machine of the production lot is not on the machine or does not exist.

[0100] In addition, the machine allocation plan for the layer decision of all wafers in the wafer group returning to the lithography area for processing needs to meet the load capacity constraints of the machine. The average daily load of the machine can be measured from three perspectives: processing time / number of wafers / wph:

[0101]

[0102]

[0103]

[0104] Among them, LoadT kd represents the time load of machine k in d days, p il represents the processing time of layer l of product i, LoadP kd represents the wafer load of machine k on day d, q ij represents the number of wafers in product i jlot, W kd represents the available production time of machine k in d days, τ kd Represents the portion of the allocated load that exceeds the available time;

[0105] In order to achieve the goal of daily load balancing for each machine within 14 days, the following multi-objective scheme is constructed: goal (1) ensures daily load balancing for each type of machine, goal (2) ensures load balancing for each type of machine within 14 days, goal (3) ensures load balancing for each machine within 14 days, and goal 4 is used as a soft constraint goal for machine time capacity; for example and They respectively refer to the largest machine load and the smallest machine load of the h-type machine group on the dth day.

[0106]

[0107]

[0108]

[0109]

[0110] in, and They refer to the largest and smallest machine loads in the h-type machine group on the dth day, respectively. and They refer to the maximum load and minimum load of the machines in the H-type machine group within 14 days. and They respectively refer to the maximum load and minimum load of machine group k in 14 days.

[0111] Embodiment 3

[0112] On the day of decision making, obtain information from the MES system, such as the number of machines in the photolithography area, processing types, available capacity, and the target number of wafers processed per hour;

[0113] Whether a machine k∈K has a certain processing capability type (also called processing capability type or process window, divided into four types: IMM / ARF / KRF / I_LINE) is represented by a binary array A, where each 0-1 element A hk ∈{0,1} is 1 or 0, refer to Table 1:

[0114] Table 1 Lithography machine information

[0115]

[0116]

[0117]

[0118] Table 1 lists all the lithography machines that can be used at this time, and each machine has a subordinate processing type.

[0119] The available capacity W of machine k on day d kd It is equal to the maximum daily capacity minus the unavailable time such as downtime and PM, so the daily available capacity of each machine needs to be calculated as:

[0120] W kd =1440-time down -time pm

[0121] Among them, time down and time pm They are the down time and PM unavailable time respectively;

[0122] The obtained lot information to be put into production includes the identification number of each lot (lot set j∈J), the product type (set i∈I), the processing route (processing route_id), the recipe, and the number of wafers and layers included (layer set l∈L of product i i). Each lot is uniquely identified by the lot identification number. The product type, processing route, recipe and number of wafers are obtained from the mes library. Different lots can belong to the same product and processing route, and the naming method should be unified. The number of layers in each lot is the number of layers on the processing route that will be passed in the next 14 days. The calculation method is: based on the current time point and the remaining processing time of the current layer_seq, all layer counts of the layer completion time point included in the next 14 days are:

[0123] lot-layerarriveday

[0124] =roundlayerremaintime(min)+layercycletime(min)≤14

[0125] Please refer to Table 2:

[0126] Table 2 Lot information for the next 14 days

[0127]

[0128]

[0129]

[0130] Table 2 lists the daily production quantities for the next 14 days. Each production lot has a matching processing route and product. In general, the daily production plan should meet the output requirements of the fab factory to ensure continuous and stable output.

[0131] On the day of decision-making, the process information of the lot currently in the processing pool is obtained from the MES system, mainly the process information of the coming work-in-progress that will return to the lithography area in the future and the labels of the key layer machines (key layer machines) they carry.

[0132] The specific information of the returned wafer group includes product type, processing route, lot identification number, number of wafers, number of layers within 14 days, the current step of the lot (step seq), including photolithography process time (process time), total layer processing time (CT layer＝l =∑ step ∈lCT step, that is, the layer cycle time is equal to the sum of the step cycle times. Since advanced IMM and ARF lithography equipment have strict requirements on the consistency of critical dimensions (CD) between different layers, it is also necessary to use the binary parameter km ijhk Indicates whether the key layer machine bound to the lithography layer of the j-th lot of product i with processing type h is machine k. If yes, it is 1, otherwise it is 0. If no, it is also 0, indicating that there is no label. In this case, it needs to be bound to an advanced machine like the lot to be produced.

[0133] Please refer to Table 3:

[0134] Table 3 Returned wafer group information in production

[0135]

[0136]

[0137] In Table 3, the label on the lot itself is specific to a machine, which needs to be determined based on the same type of machines that have already processed in the system. If there is no label, it must be indicated.

[0138] In addition to the information of the two types of lots themselves, information on all layer levels is also required. In addition to product type, processing route, process time, and cycle time, it is also necessary to consider the layer serial number (layer_seq) in the processing route and the type of processing required by the layer. Among them, the critical dimensions (CD) of layers requiring types IMM and ARF are higher and are also called critical layers (critical layers). In practice, in order to ensure high yield, critical layers of the same type need to be processed on the same machine. This machine alignment between layers of a lot is called vertical machine limitation, that is, vertical machine limitation. For details, refer to Figure 3 Using the binary array CL il Indicates whether the layer l of product i is a key layer, 1 if yes and 0 if no; use the binary array CR ilh Indicates whether product i layer l needs type h capacity, which is 1 if yes and 0 if no. Finally, according to the layer cycle time, the expected arrival date of a layer can be obtained as the load action date:

[0139]

[0140] Among them, R ild Indicates whether the arrival date of product i on level l is d days, where d represents the period from the 1st day to the dth day (d∈[1,…,14]), L i Indicates the total number of layers of product i, CTil represents the cycle time of product i at layer l, Indicates rounding up.

[0141] Please refer to Table 4:

[0142] Table 4 Layer information of all processed wafer groups when the wafers are returned to the photolithography area for processing layer by layer

[0143]

[0144] * The 4 data are process time (min / lot), layer cycle time (day), process capability type, whether or not a critical layer (0-1)

[0145] In Table 4, the progress of the current photolithography step of each lot of each product type is different, that is, the remaining processing time of the current layer is different. There may be a different number of layers experienced within 14 days and a difference in the expected arrival date of each layer. Here, the time granularity is accurately calculated based on minutes.

[0146] The above data is used as input parameters, and a mixed integer linear programming model is constructed with the goal of daily machine load balancing in the lithography area for the next 14 days. The key layer machine planning scheme and machine load balancing of all lots are solved. These lots with system key layer machine labels will be dispatched to the corresponding lithography machines at different layers according to the lithography steps and label types during the processing process. The same decision-making process is repeated every day.

[0147] Then, a mixed integer programming model is constructed and various constraints are satisfied; finally, the daily load and change of each type of each machine generated by the capacity planning optimization solution obtained by the larger-scale embodiment 1 are shown in Table 5, taking the IMM type lithography machine as an example:

[0148] Table 5 Daily load of each machine of IMM type

[0149]

[0150] Embodiment 4

[0151] In this embodiment, a semiconductor-based machine capacity planning system is disclosed, including:

[0152] The machine data acquisition module 100 is used to obtain the number and available capacity information of various types of machines in the photolithography area on that day and the target number limit of wafers processed per hour;

[0153] The WIP process information acquisition module 200 is used to obtain the process information of two types of lots, namely, the lot to be put into production and the lot in production that will re-enter the photolithography area every day in the next 14 days. Except for the actual value of the day of production, the remaining 13 days of production are estimated values. The wafer group returned from the processing pool obtains the expected re-entry date and the key layer machine label it carries;

[0154] The algorithm operation module 300 is used to calculate the optimization plan of the key layer machines set by the system for all lots based on the parameters obtained and processed above, and the proposed allocation of machines for non-key layers, based on the constructed mixed integer linear programming scheduling model, and transmit the results to the backend database;

[0155] The performance analysis module 400 is used to analyze the algorithm performance by performing secondary calculations to obtain indicators related to the daily capacity allocation and load balancing of all machines in the lithography area according to the running algorithm model and the solution results, including the algorithm solution efficiency under different scale scenarios, the daily load time / lot number / wafer number / wph of each machine in each of the four capacity types, and the 14-day load fluctuation;

[0156] The execution module 500 is used to allocate machines to different layers for all wafers in the lot pool according to the lithography step category and system label according to the algorithm result, and prepare the machine for the next layer in advance.

[0157] Embodiment 5

[0158] In addition, the present application also provides a computer device, the structure of which is as follows: Figure 4 As shown, the device includes a memory 1 for storing computer-readable instructions and a processor 2 for executing the computer-readable instructions, wherein when the computer-readable instructions are executed by the processor, the processor is triggered to execute the described method.

[0159] The methods and / or embodiments in the embodiments of the present application may be implemented as computer software programs. For example, the embodiments of the present disclosure include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes program code for executing the method shown in the flowchart. When the computer program is executed by the processing unit, the above functions defined in the method of the present application are executed.

[0160] It should be noted that the computer-readable medium described in the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device.

[0161] In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, device, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0162] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0163] The flow chart or block diagram in the accompanying drawings shows the possible architecture, function and operation of the equipment, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated system for hardware that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0164] As another aspect, the embodiments of the present application further provide a computer-readable medium, which may be included in the device described in the above embodiments; or may exist independently without being assembled into the device. The above computer-readable medium carries one or more computer-readable instructions, which may be executed by a processor to implement the steps of the methods and / or technical solutions of the above multiple embodiments of the present application.

[0165] In a typical configuration of the present application, the terminal and the equipment of the service network each include one or more processors (CPU), input / output interface, network interface and memory.

[0166] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0167] Computer readable media include permanent and non-permanent, removable and non-removable media, and can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, modules of programs or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0168] In addition, an embodiment of the present application further provides a computer program, which is stored in a computer device, so that the computer device executes the method for controlling code execution.

[0169] It should be noted that the present application can be implemented in software and / or a combination of software and hardware, for example, can be implemented using an application specific integrated circuit (ASIC), a general purpose computer or any other similar hardware device. In certain embodiments, the software program of the present application can be executed by a processor to implement the above steps or functions. Similarly, the software program of the present application (including related data structures) can be stored in a computer-readable recording medium, for example, a RAM memory, a magnetic or optical drive or a floppy disk and similar devices. In addition, some steps or functions of the present application can be implemented using hardware, for example, as a circuit that cooperates with a processor to perform each step or function.

[0170] It is obvious to those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and that the present application can be implemented in other specific forms without departing from the spirit or basic features of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the present application is limited by the attached claims rather than the above description, so it is intended to include all changes that fall within the meaning and scope of the equivalent elements of the claims in the present application. Any figure mark in the claims should not be regarded as limiting the claims involved. In addition, it is obvious that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices stated in the device claim can also be implemented by one unit or device through software or hardware. The words first, second, etc. are used to indicate names, and do not indicate any particular order.

Claims

1. A semiconductor-based lithography machine capacity planning method, characterized in that: The steps include: On the day of decision making, obtain information from the MES system on the number of machines in the photolithography area, processing types, available capacity, and the target number of wafers processed per hour; On the day of decision-making, the process information of the lots to be put into production is obtained from the MES system. The lots to be put into production are divided into two categories: the lots actually put into production today and the lots to be put into production in the next 13 days. The number of lots put into production every day in the future is predicted by statistical methods based on historical data; On the day of decision making, obtain the lot process information currently in the processing pool and returning to the lithography area in the future from the MES system, including the key layer machine labels carried; The above data are used as input parameters, and a mixed integer linear programming model is constructed with the goal of daily load balancing of the 14-day machine in the lithography area. The key layer machine planning scheme and machine load balancing of all lots are solved, and the lots with system key layer machine labels are dispatched to the corresponding lithography machines at different layers according to the lithography steps and label types during the processing process. In the step of constructing a mixed integer linear programming model with the goal of daily load balancing of the machines in the lithography area for 14 days, a multi-objective solution for daily load balancing of each machine within 14 days is constructed: in, and They refer to the largest and smallest machine loads in the h-type machine group on the dth day, respectively. and They refer to the maximum load and minimum load of the machines in the H-type machine group within 14 days. and They refer to the maximum load and minimum load of machine group k in 14 days respectively; The load balancing multi-objective solution satisfies the following constraints: The wafers in each wafer group are returned to the lithography area layer by layer for processing and are processed on idle machines that meet the requirements of their processing type: Among them, the binary decision variable x ijlk Indicates whether the l-th layer of the j-th lot of product i is allocated to machine k, which is 1 if yes and 0 if no; A hk Whether machine k has the hth type of processing capability, CR ilh Indicates whether product layer l requires type h capability, 1 if yes and 0 if no; The returned wafer groups in the lot to be put into production and the processing pool all meet the following vertical machine limit constraints: Among them, CL il Indicates whether the layer l of product i is a key layer, which is 1 if it is and 0 if it is not. j1 indicates the lot put into production, dm ijhk and Indicates whether the first key layer of type h in the production lot and the production lot is assigned to machine k, which is 1 if yes and 0 if no; km ijhk Indicates that the i product jlot in production has been bound to the h type machine k, which is 1 if yes and 0 if no. j2 indicates the lot in production; The average daily processing time / wafer number / wph of the machine for all wafer groups to return to the lithography area for processing layer by layer meets the machine load capacity constraint: Among them, LoadT kd represents the time load of machine k in d days, p il represents the processing time of layer l of product i, LoadP kd represents the wafer load of machine k on day d, q ij represents the number of wafers in product i jlot, W kd represents the available production time of machine k in d days, τ kd Represents the portion of the allocated load that exceeds the available time; Among them, R ild Indicates whether the arrival date of product i on level l is d days, where d represents the period from the 1st day to the dth day (d∈[1,…,14]), L i Indicates the total number of layers of product i, CT il represents the cycle time of layer l of product i, Indicates rounding up; Repeat the above steps daily.

2. The semiconductor-based lithography machine capacity planning method according to claim 1, characterized in that: The processing types include IMM, ARF, KRF and I_LINE.

3. The semiconductor-based lithography machine capacity planning method according to claim 1, characterized in that: The lot process information includes lot basic information, lithography process time, total layer processing time, the wafer processing step currently in the lot and the key layer machine label carried by the lot.

4. The semiconductor-based lithography machine capacity planning method according to claim 3, characterized in that: In the step of obtaining process information of lots to be put into production, the serial numbers of the layers of the two types of lots, which are in production and to be put into production, on the processing route and the target processing types of the layers are also obtained.

5. A semiconductor-based lithography machine capacity planning system, characterized in that: include: A machine data acquisition module (100): used to obtain the number of machines of various types, processing types and available production capacity in the photolithography area on that day, as well as the target number limit of wafers processed per hour; The WIP process information acquisition module (200) is used to acquire two types of lot process information, namely, lot information to be put into production and lot information to be re-entered into the photolithography area after production, for the next 14 days. The wafer group returned from the processing pool obtains the re-entry date and the key layer machine label it carries. Algorithm operation module (300): used to construct a mixed integer linear programming scheduling model to calculate the key layer machine optimization plan for all lots following the system settings, and transmit the results to the backend database; Performance analysis module (400): used to perform secondary calculation according to the solution result of the algorithm operation module (300), obtain daily capacity allocation and load balancing indicators of all machines in the lithography area to analyze algorithm performance; An execution module (500) is used to allocate machines to different layers for all wafers in the lot pool according to the photolithography step category and system label according to the algorithm result; The algorithm operation module (300) constructs a mixed integer linear programming model with the daily load balance of the machines in the lithography area for 14 days as the goal, and constructs a multi-objective solution for the daily load balance of each machine within 14 days: in, and They refer to the largest and smallest machine loads in the h-type machine group on the dth day, respectively. and They refer to the maximum load and minimum load of the machines in the H-type machine group within 14 days. and The maximum and minimum loads of machine group k in 14 days respectively. The load balancing multi-objective solution satisfies the following constraints: The wafers in each wafer group are returned to the lithography area layer by layer for processing and are processed on idle machines that meet the requirements of their processing type: Among them, the binary decision variable x ijlk Indicates whether the l-th layer of the j-th lot of product i is allocated to machine k, which is 1 if yes and 0 if no; A hk Whether machine k has the hth type of processing capability, CR ilh Indicates whether product layer l requires type h capability, 1 if yes and 0 if no; The returned wafer groups in the lot to be put into production and the processing pool all meet the following vertical machine limit constraints: Among them, CL il Indicates whether the layer l of product i is a key layer, which is 1 if it is and 0 if it is not. j1 indicates the lot put into production, dm ijhk and Indicates whether the first key layer of type h in the production lot and the production lot is assigned to machine k, which is 1 if yes and 0 if no; km ijhk Indicates that the i product jlot in production has been bound to the h type machine k, which is 1 if yes and 0 if no. j2 indicates the lot in production; The average daily processing time / wafer number / wph of the machine for all wafer groups to return to the lithography area for processing layer by layer meets the machine load capacity constraint: Among them, LoadT kd represents the time load of machine k in d days, p il represents the processing time of layer l of product i, LoadP kd represents the wafer load of machine k on day d, q ij represents the number of wafers in product i jlot, W kd represents the available production time of machine k in d days, τ kd Represents the portion of the allocated load that exceeds the available time; Among them, R ild Indicates whether the arrival date of product i on level l is d days, where d represents the period from the 1st day to the dth day (d∈[1,…,14]), L i Indicates the total number of layers of product i, CT il represents the cycle time of product i at layer l, Indicates rounding up.

6. The semiconductor-based lithography machine capacity planning system according to claim 5, characterized in that: The algorithm operation module (300) distinguishes the algorithm result according to whether it is a key layer type, using the key layer machine field when it is a key layer type, and using the machine suggestion field when it is not a key layer type; and directly obtains the target machine information by screening the lot identification number and the layer sequence number or processing capability type on its processing route; the algorithm operation module (300) also analyzes the load fluctuation through the daily load standard deviation of each type of machine group; and at the same time selects the time limit with the highest multi-objective optimization efficiency according to the algorithm result.

7. A computer device, characterized in that: The device comprises: One or more processors; and a memory storing computer program instructions, which, when executed, cause the processor to perform the method as claimed in any one of claims 1 to 4.

8. A computer readable medium having computer program instructions stored thereon, wherein the computer program instructions can be executed by a processor to implement the method according to any one of claims 1 to 4.

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