A power clamp circuit

Abstract

The embodiment of the present application provides a power clamp circuit. When the voltage at the second terminal of the second power supply tube is greater than a preset threshold voltage, the detection circuit is turned on to generate a current which flows through the first resistor to reduce the voltage at the first terminal of the second power supply tube, thereby reducing the voltage at the second terminal of the second power supply tube. The voltage required by the device can be obtained through the embodiment of the present application.

Description

Technical Field

[0001] The embodiments of the present application belong to the technical field of clamping circuits, and in particular, relate to a power clamping circuit. Background Art

[0002] When using a power supply to power other devices, the power supply needs to supply the voltage required by the device, such as Figure 1 As shown, if the voltage of the power supply needs to be controlled within the required voltage range, Figure 1 The circuit is subject to two factors: (1) the breakdown voltage of the Zener diode, which may vary under different processes; (2) the need to use a low-on-voltage PMOS tube and a Zener diode in combination. Low-on-voltage PMOS devices on different process platforms require additional masks, and the circuit of the prior art will experience a voltage drop when M3 is turned off to M4. Based on the above problems, a new solution is proposed. Summary of the invention

[0003] The embodiments of the present application are intended to alleviate or solve the problems in the prior art.

[0004] The embodiment of the present application provides a power clamp circuit, comprising: a bias circuit, a first power supply tube, a second power supply tube, a charge pump and a detection circuit;

[0005] The output end of the bias circuit is connected to the first end of the first power supply tube, and the second end of the first power supply tube is connected to the input end of the charge pump;

[0006] The output end of the charge pump is connected to the first end of the second power supply tube through the first resistor, and the second end of the second power supply tube is connected to the voltage output circuit;

[0007] The bias circuit input terminal, the third terminal of the first power supply tube and the third terminal of the second power supply tube are respectively connected to the power supply, and the bias circuit and the charge pump are also respectively connected to the ground terminal;

[0008] One end of the detection circuit is connected to the common end between the voltage output circuit and the second end of the second power supply tube, and the other end of the detection circuit is connected to the common end between the first resistor and the first end of the second power supply tube;

[0009] When the voltage at the second end of the second power supply tube is greater than a preset threshold voltage, the detection circuit is turned on to generate a current which flows through the first resistor to reduce the voltage at the first end of the second power supply tube, thereby reducing the voltage at the second end of the second power supply tube.

[0010] As a preferred embodiment of the present application, a second resistor is provided in series with the circuit where the bias circuit is located so as to stabilize the voltage output by the power supply;

[0011] A common end between the second resistor and the bias circuit is connected to the first end of the first power supply tube.

[0012] As a preferred embodiment of the present application, the bias circuit is composed of a plurality of NMOS tubes or PMOS tubes connected in series.

[0013] As a preferred embodiment of the present application, the circuit further includes a first protection circuit;

[0014] One end of the first protection circuit is connected to a common end between the output end of the charge pump and the first resistor, and the other end of the first protection circuit is connected to a ground end.

[0015] As a preferred embodiment of the present application, the first protection circuit includes a first capacitor and a Zener diode;

[0016] One end of the first capacitor and one end of the Zener diode are both connected to a common end between the output end of the charge pump and the first resistor;

[0017] The other end of the first capacitor and the other end of the Zener diode are both connected to the ground end.

[0018] As a preferred embodiment of the present application, the detection circuit includes a third resistor, a detection branch and a current mirror which are sequentially arranged in series;

[0019] The first end of the third resistor is connected to the common end between the second end of the second power supply tube and the voltage output circuit;

[0020] The second end of the third resistor is connected to the current mirror through a detection branch, and the current mirror is connected to a common end between the first resistor and the first end of the second power supply tube;

[0021] The current mirror is also connected to the ground terminal.

[0022] As a preferred embodiment of the present application, a second protection circuit is further provided between the current mirror and a common end between the first resistor and the first end of the second power supply tube.

[0023] As a preferred embodiment of the present application, the detection branch includes NMOS tubes connected in series.

[0024] As a preferred embodiment of the present application, the voltage output circuit includes a second capacitor.

[0025] Compared with the prior art, in the power clamp circuit provided by the present application, when the voltage at the second end of the second power supply tube is greater than a preset threshold voltage, the detection circuit is turned on to generate current, which flows through the first resistor for voltage division, so as to reduce the voltage at the first end of the second power supply tube, thereby reducing the voltage at the second end of the second power supply tube. Through the embodiments of the present application, it is not necessary to use a low-on voltage PMOS tube and a Zener diode in combination as in the prior art, and there are strict requirements on the Zener diode, etc., in order to obtain an ideal output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. Some specific embodiments of the present application will be described in detail in an illustrative and non-restrictive manner with reference to the drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0027] Figure 1 It is a structural diagram of a power clamp circuit provided by the prior art;

[0028] Figure 2 is a graph showing changes in output voltage in the prior art;

[0029] Figure 3 This is a structural diagram of a power clamp circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0031] like Figure 1As shown in the figure, a power clamping circuit provided in the prior art. In the prior art circuit, M1 and M2 are low-threshold-voltage vth PMOS transistors, M3 is a high-voltage PMOS transistor, M4 is a high-voltage NMOS transistor, and the breakdown voltage Vz of the Zener diode is 5.6V. When VIN < Vz + vth(M1), M3 conducts, and the clamping voltage vclamp is approximately equal to the power supply input voltage VIN. When VIN > Vz + vth(M1), the Zener diode D2 breaks down, M1 and M2 conduct, causing M3 to turn off. At this time, the Zener diode D1 has already broken down, and the clamping voltage VCLAMP is finally clamped at Vz - Vth(M4), and the output voltage can be guaranteed to be lower than 6V;

[0032] However, this solution is restricted by two factors: (1) The breakdown voltage of the Zener diode may vary under different processes; (2) A low-on-voltage PMOS transistor and a Zener diode need to be used in combination, and additional masks are required for low-on-voltage PMOS devices on different process platforms.

[0033] In the prior art circuit, the voltage drops when M3 turns off to M4 turns off (see Figure 2 ), and a new solution is proposed based on the above problems.

[0034] As Figure 3 shown, an embodiment of the present application provides a power clamping circuit, including: a bias circuit 01, a first power supply transistor M15, a second power supply transistor M16, a charge pump 02, and a detection circuit 03;

[0035] In the embodiment of the present application, both the first power supply transistor M15 and the second power supply transistor M16 are NMOS transistors.

[0036] The output end of the bias circuit 01 is connected to the gate of the first power supply transistor M15, and the source of the first power supply transistor M15 is connected to the input end of the charge pump 02;

[0037] The output end of the charge pump 02 is connected to the gate of the second power supply transistor M16 through a first resistor R5, and the source of the second power supply transistor M16 is connected to the voltage output circuit;

[0038] The input end of the bias circuit 01, the drain of the first power supply transistor M15, and the drain of the second power supply transistor M16 are respectively connected to the power supply, and the bias circuit 01 and the charge pump 02 are respectively also connected to the ground terminal;

[0039] One end of the detection circuit 03 is connected to the common terminal between the voltage output circuit and the source of the second power supply transistor M16, and the other end of the detection circuit 03 is connected to the common terminal between the first resistor R5 and the gate of the second power supply transistor M16;

[0040] When the source voltage of the second power supply tube M16 is greater than the preset threshold voltage, the detection circuit 03 is turned on to generate current which flows through the first resistor R5 to reduce the gate voltage of the second power supply tube M16, thereby reducing the source voltage of the second power supply tube M16.

[0041] In the present application, the charge pump 02 includes switches S1A, S2A, S3B, S4B and a flying capacitor C5. When the charge pump 02 is in the charging stage, switches S1A and S2A are turned on, switches S3B and S4B are turned off, and the flying capacitor C5 is charged. When the charge pump 02 is in the discharging stage, switches S3B and S4B are turned on, switches S1A and S2A are turned off, and C4 is charged through the flying capacitor C5. The source of the first power supply tube M15 is connected to the gate of the second power supply tube M16 through the charge pump 02 to power the voltage output circuit.

[0042] In the embodiment of the present application, the bias circuit 01 is used to control the first power supply tube M15 to be at a working point. The working point is that the gate voltage of the first power supply tube M15 is VDDL through the output voltage of the first power supply tube M15 through the setting of the bias circuit 01, and then the VDDL is boosted by the charge pump 02. The output voltage of the charge pump 02 is transmitted to the voltage output circuit through the second power supply tube M16. The source voltage of the second power supply tube M16 is detected by the detection circuit 03. If the source voltage of the second power supply tube M16 is large, the detection circuit 03 is turned on to generate current and then flows through the first resistor R5 for voltage division, so as to reduce the gate voltage of the second power supply tube M16, thereby reducing the source voltage of the second power supply tube M16. Preferably, the bias circuit 01 is composed of a plurality of NMOS tubes (M5-M8) or PMOS tubes (M5-M8) arranged in series.

[0043] As a preferred embodiment of the present application, a second resistor R4 is arranged in series on the circuit where the bias circuit 01 is located to stabilize the voltage output by the power supply; the common end between the second resistor R4 and the bias circuit 01 is connected to the first end of the first power supply tube M15.

[0044] As a preferred embodiment of the present application, the circuit further includes a first protection circuit 04;

[0045] One end of the protection circuit 04 is connected to the common end between the output end of the charge pump 02 and the first resistor R5 , and the other end of the first protection circuit 04 is connected to the ground end.

[0046] Further, the protection circuit 04 includes a first capacitor C5 and a Zener diode D3;

[0047] One end of the first capacitor C5 and one end of the Zener diode D3 are both connected to the common end between the output end of the charge pump O2 and the first resistor R5; the other end of the first capacitor C5 and the other end of the Zener diode D3 are both connected to the ground end.

[0048] In the embodiment of the present application, the output voltage of the charge pump 02 is transmitted to the voltage output circuit through the second power supply tube M16, and the source voltage of the second power supply tube M16 is detected by the detection circuit 03. If the source voltage of the second power supply tube M16 is large, the detection circuit 03 is turned on to generate current, which flows through the first resistor R5 to reduce the gate voltage of M16, thereby achieving the purpose of stabilizing the output voltage.

[0049] As a preferred embodiment of the present application, the detection circuit 03 includes a third resistor R6, a detection branch and a current mirror arranged in series in sequence;

[0050] The first end of the third resistor R6 is connected to the common end between the second end of the second power supply tube M16 and the voltage output circuit; a second protection circuit is also provided between the current mirror and the common end between the first end of the first resistor R5 and the first end of the second power supply tube M16; the current mirror is also connected to the ground end.

[0051] In the embodiment of the present application, the output voltage of the charge pump 02 is transmitted to the voltage output circuit through the second power supply tube M16, and the magnitude of the source voltage of the second power supply tube M16 is detected by the detection circuit 03. If the source voltage of the second power supply tube M16 exceeds the preset threshold voltage, the detection branch is turned on, and the current is mirrored by the current mirror, and then flows through the first resistor R5 for voltage division, so as to reduce the voltage of the gate of the second power supply tube M16, thereby reducing the source voltage of the second power supply tube M16. In the embodiment of the present application, since the second power supply tube M16 and the first resistor R5 are in the high voltage area, the current mirror is in the low voltage area, and the current mirror can be protected by the high voltage protection circuit M13, the high voltage protection circuit is the NMOS tube M13, and the current mirror is composed of the NMOS tubes M9 and M14.

[0052] Preferably, the detection branch includes NMOS tubes (M9-M12) connected in series.

[0053] As a preferred embodiment of the present application, the voltage output circuit includes a second capacitor C3.

[0054] The output voltage is filtered by the second capacitor C3.

[0055] The first power supply tube M15 and the second power supply tube M16 are both high-voltage NMOS tubes. When the power input voltage Vin is low, since the charge pump 02 has started to work, the gate voltage Vgate=min (Vz, VddL+Vclamp) of the second power supply tube M16 is in a switch state and is fully turned on, and the voltage Vclamp of the voltage output circuit is approximately equal to VIN. When VIN increases, the voltage vclamp of the voltage output circuit rises accordingly until M9, M10, M11 and M12 are turned on, and a voltage drop is generated on R5. The gate voltage Vgate of the second power supply tube M16 will decrease (Vgate=Vz-(Vclamp-4*Vth2)*R5 / R6), where Vth2 is the turn-on voltage of M9, M10, M11 and M12, and Vz is the breakdown voltage of the Zener diode D3. Reasonable resistance values ​​and MOS The size of the tube is to ensure that the voltage Vclamp of the voltage output circuit is within the safe working voltage Vclamp=Vz-Vth1-(Vclamp-4*Vth2)R5 / R6, where Vth1 is the turn-on voltage of the second power supply tube M16. The voltage Vclamp of the voltage output circuit in the embodiment of the present application will not appear as Figure 1 In the case of a voltage drop in the circuit shown in the figure, when the output voltage of the embodiment of the present application rises to the detection circuit, the negative feedback mechanism of the output detection circuit stabilizes the output voltage, and the situation as Figure 1 The circuit of the prior art will experience a voltage drop when M3 is turned off and M4 is turned off.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A power clamp circuit, characterized in that: include: A bias circuit, a first power supply tube, a second power supply tube, a charge pump, a detection circuit and a voltage output circuit; The bias circuit is composed of four NMOS tubes connected in series, the gate and drain of each NMOS tube are connected, the gate and drain of the top NMOS tube in the bias circuit are connected to the gate of the first power supply tube and one end of the second resistor, the other end of the second resistor and the drain of the first power supply tube are connected to a power source, and the source of the bottom NMOS tube is grounded; The source of the first power supply tube is connected to the input end of the charge pump, the output end of the charge pump is connected to the gate of the second power supply tube through a first resistor, the source of the second power supply tube is connected to the voltage output circuit, the drain of the second power supply tube is connected to the power supply, and the charge pump is also connected to the ground end; The detection circuit comprises a third resistor, a detection branch and a current mirror which are sequentially connected in series, wherein the first end of the third resistor is connected to the source of the second power supply tube, the second end of the third resistor is connected to the current mirror through the detection branch, the current mirror is also connected to the common end between the first resistor and the gate of the second power supply tube, and the current mirror is also connected to the ground end; the detection branch comprises NMOS tubes which are mutually connected in series; When the source voltage of the second power supply tube is greater than a preset threshold voltage, the detection circuit is turned on to generate a current which flows through the first resistor to reduce the voltage of the gate of the second power supply tube, thereby reducing the source voltage of the second power supply tube.

2. A power clamp circuit as claimed in claim 1, characterized in that: The bias circuit is composed of a plurality of PMOS tubes connected in series.

3. A power clamp circuit as claimed in claim 1, characterized in that: The circuit also includes a first protection circuit; One end of the first protection circuit is connected to a common end between the output end of the charge pump and the first resistor, and the other end of the first protection circuit is connected to a ground end.

4. A power clamp circuit as claimed in claim 3, characterized in that: The first protection circuit includes a first capacitor and a Zener diode; One end of the first capacitor and one end of the Zener diode are both connected to a common end between the output end of the charge pump and the first resistor; The other end of the first capacitor and the other end of the Zener diode are both connected to the ground end.

5. A power clamp circuit as claimed in claim 1, characterized in that: A second protection circuit is also provided between the current mirror and a common end between the first resistor and the gate of the second power supply tube.

6. A power clamp circuit as claimed in claim 1, characterized in that: The voltage output circuit includes a second capacitor.

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