Systems and methods for fast memory access

Abstract

Systems and methods for fast memory access are disclosed. In one aspect, a processor, such as a control circuit in a system-on-chip (SoC) coupled to an external memory (such as a universal flash storage (UFS) memory (e.g., NAND flash memory), where a partial logical-to-physical (L2P) mapping table is stored in the external memory and a local L2P mapping table is stored in a local memory (e.g., dynamic random access memory (DRAM))). The control circuit can evaluate the percentage of active entries compared to non-active entries in the local L2P mapping table. If the number of non-active entries exceeds the number of active entries, the control circuit can send a read command without accessing the local L2P mapping table.

Description

[0001] Priority Application

[0002] This application claims priority to U.S. Patent Application Serial No. 17 / 453,572, filed on November 4, 2021, entitled "SYSTEMS AND METHODS FOR FAST MEMORY ACCESS", which is hereby incorporated by reference in its entirety. BACKGROUND OF THE INVENTION

[0003] I. Technical Field

[0004] The technology of the present disclosure generally relates to accessing data stored in NAND flash memory.

[0005] II. Background Art

[0006] Computing devices, and more particularly mobile communication devices, are becoming increasingly common in modern society. The popularity of these mobile communication devices is due in part to the many functions now enabled on such devices. The increased processing power in such devices means that mobile communication devices have evolved from pure communication tools to sophisticated mobile entertainment centers, resulting in an enhanced user experience. Almost every computing device relies on different levels of memory to store data and operating instructions. For example, there may be a system memory that accesses NAND flash memory. Because access to NAND flash memory is relatively slow, there may be a cache memory associated with the processor that facilitates address mapping to accelerate memory access. Even though there are various ways to improve memory access, there always seems to be room for improvement. SUMMARY OF THE INVENTION

[0007] Aspects disclosed in the detailed description include systems and methods for fast memory access. Specifically, exemplary aspects of the present disclosure contemplate a processor, such as a control circuit in a system-on-chip (SoC) coupled to an external memory (such as a universal flash storage (UFS) memory (e.g., NAND flash memory)), where a partial logical-to-physical (L2P) mapping table is stored in the external memory and a local L2P mapping table is stored in local memory (e.g., dynamic random access memory (DRAM)). The control circuit can evaluate the percentage of active entries compared to non-active entries in the local L2P mapping table. If the number of non-active entries exceeds the number of active entries, the control circuit can send a read command without accessing the local L2P mapping table. Skipping the local memory in this way relies on the most recent entries in the external memory, which may result in faster memory calls to the UFS memory, leading to a better user experience.

[0008] In this regard, in one aspect, a System-on-Chip (SoC) is disclosed. The SoC includes a memory bus interface configured to couple to a Universal Flash Storage (UFS) memory having an external cache memory. The external cache memory includes a partial L2P mapping table of the UFS memory. The SoC also includes a local cache memory that includes a local L2P mapping table of the UFS memory. The SoC further includes a control circuit coupled to the memory bus interface and the local cache memory. The control circuit is configured to determine an active size of an active portion of the local L2P mapping table in the local cache memory. The control circuit is further configured to compare the active size of the active portion with a threshold.

[0009] In another aspect, a System-on-Chip (SoC) is disclosed. The SoC includes a memory bus interface configured to couple to a Universal Flash Storage (UFS) memory having an external cache memory. The external cache memory includes a partial L2P mapping table of the UFS memory. The SoC also includes a local cache memory that includes a local L2P mapping table of the UFS memory. The SoC further includes a control circuit coupled to the memory bus interface and the local cache memory. The control circuit is configured to determine an inactive size of an inactive portion of the local L2P mapping table in the local cache memory. The control circuit is further configured to compare the inactive size of the inactive portion with a threshold.

[0010] In another aspect, a method of accessing a memory from a host is disclosed. The method includes determining an active size of an active portion of a local L2P mapping table in a local cache memory associated with the host relative to a partial L2P mapping table in an external cache memory in a remote memory device. The method also includes comparing the active size of the active portion with a threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram of a conventional computing system having a host and a Universal Flash Storage (UFS) memory associated therewith;

[0012] Figure 2 is a block diagram of an exemplary computing system having a UFS memory associated therewith, using a Host Performance Booster (HPB) to improve memory access time and further improving memory access time using exemplary aspects of the present disclosure;

[0013] Figure 3 is a signal-versus-time plot of conventional memory access times with cache hits and cache misses;

[0014] Figure 4is a block diagram of a computing device having a host and a UFS memory associated therewith, showing memory access in accordance with an exemplary aspect of the present disclosure;

[0015] Figure 5 is a signal-versus-time plot of memory access times in accordance with an exemplary aspect of the present disclosure;

[0016] Figure 6 is a flowchart of a process associated with an exemplary aspect of the present disclosure, the process being applicable to traditional and enabled devices; and

[0017] Figure 7 is a block diagram of a computing device having a host and a UFS memory that can operate in accordance with the fast memory access aspect of the present disclosure. DETAILED DESCRIPTION

[0018] Referring now to the drawings, several exemplary aspects of the present disclosure are described. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or having an advantage over other aspects.

[0019] Aspects disclosed in the detailed description include systems and methods for fast memory access. Specifically, exemplary aspects of the present disclosure contemplate a processor, such as a control circuit in a system-on-chip (SoC) coupled to an external memory, such as a universal flash storage (UFS) memory (e.g., NAND flash memory), where a partial logical-to-physical (L2P) mapping table is stored in the external memory and a local L2P mapping table is stored in local memory (e.g., dynamic random access memory (DRAM)). The control circuit can evaluate the percentage of active entries in the local L2P mapping table compared to the non-active entries. If the number of non-active entries exceeds the number of active entries, the control circuit can send a read command without accessing the local L2P mapping table. Skipping the local memory in this way relies on the latest entries in the external memory, which can result in a faster memory call to the UFS memory, leading to a better user experience.

[0020] In Figure 1 a brief overview of a computing device having a host and a UFS memory is provided. Figure 2 A similar computing device is shown on which a host performance booster (HPB) is enabled and the exemplary aspects of the present disclosure can be implemented. Figure 3 Illustrates a situation where a memory call that results in a cache miss can negatively impact performance to emphasize how the exemplary aspects of the present disclosure can improve performance, as better illustrated starting from Figure 4 on.

[0021] In this regard, Figure 1Illustrates a computing device 100 having a system-on-chip (SoC) 102, which has a UFS controller 104 therein. The SoC 102 can be a single integrated circuit (IC) having multiple functions therein (the multiple functions may be on different layers, such as implemented using three-dimensional (3D) IC manufacturing technology), can be a set of stacked dies (e.g., flip-chip arrangement), etc. The SoC 102 is coupled to a UFS memory 106 via a UFS bus 108. The UFS memory 106 can include NAND memory elements 110 and SRAM memory elements 112. The NAND memory elements 110 can store the entire L2P mapping table therein, and this entire L2P mapping table is always up-to-date. The SRAM memory elements 112 can include an external cache that includes a partial L2P mapping table having entries corresponding to recently (and / or most frequently) accessed logical addresses. Compared with the SRAM memory elements 112, the NAND memory elements 110 can have a relatively slow read time.

[0022] It should be understood that in use, the UFS controller 104 can generate a read command that initially queries the SRAM memory elements 112 to find a physical address. If the partial L2P mapping table includes an L2P mapping for the requested address, the UFS memory 106 retrieves the L2P mapping entry from the SRAM memory elements 112. Then, the UFS memory 106 reads the logical block from the NAND memory elements 110 and transfers the data to the SoC 102 (generally referring to Figure 3 the signaling scenario 300 in). However, if the partial L2P mapping table does not include the logical address, the UFS memory 106 receives the read command and reads the physical address from the entire L2P mapping table in the NAND memory elements 110. The UFS memory 106 stores the entry in the partial L2P mapping table in the SRAM memory elements 112. Then, the L2P mapping entry is retrieved from the SRAM memory elements 112. Then, the UFS memory 106 reads the logical block from the NAND memory elements 110 and transfers the data to the SoC 102 (generally referring to Figure 3 the signaling scenario 310 in).

[0023] Although using a cache such as provided in the SRAM memory elements 112 can accelerate access to the logical blocks in the NAND memory elements 110 when there are entries in the partial L2P mapping table, there will be times when there is a cache miss that results in signaling scenario 310. The additional time to retrieve the address from the entire L2P mapping table in the NAND memory elements 110 negatively affects the user experience and can add unacceptable latency to certain operations within the computing device 100.

[0024] To improve performance, the industry has moved to the concept of HPB, which moves the entire L2P mapping table into the SoC, as Figure 2 exemplified better in Figure 3 cases 320 and 330. In this regard, Figure 2 a computing device 200 with an SoC 202 is exemplified, which has a UFS controller 204 therein. The SoC 202 can be coupled to a UFS memory 206 via a UFS bus 208. The UFS memory 206 can include NAND memory elements 210 and SRAM memory elements 212. The NAND memory elements 210 can store the entire L2P mapping table therein, and this entire L2P mapping table is always up-to-date. The SRAM memory elements 212 can include a cache that includes a partial L2P mapping table having entries corresponding to the most recently (and / or most frequently) accessed logical addresses. Additionally, the SoC 202 can also include a DRAM element 214 that stores a local L2P mapping table therein. The DRAM element 214 acts as a cache and allows the SoC 202 to immediately access physical addresses. Then, the SoC 202 can send a physical address and a read command to the UFS memory 206 (generally referring to Figure 3 signaling case 320 in

[0025] ). Figure 3 However, there are times when the entries in the local L2P mapping table in the DRAM element 214 are outdated or incorrect. For example, sometimes it is necessary to move data to another physical area of the NAND memory element 210 for internal maintenance purposes (e.g., refresh operations, garbage collection, read reclaim, read disturb, etc.). In such cases, the local L2P mapping table in the DRAM element 214 may be out of sync with the entire L2P mapping table in the NAND memory element 210. Traditionally, HPB allows the UFS memory 206 to send an update to the SoC 202. However, this update is periodic and not instantaneous. Therefore, read operations for out-of-sync addresses may also result in cache misses (generally referring to

[0026] Figure 3 signaling case 330 in Figure 3 ). Such cache misses can negatively impact the user experience and / or potentially introduce unacceptable latency for the computing device 200.Provide a comparison of signaling scenarios 300, 310, 320, and 330. Signaling scenario 300 begins with issuing a read command 302 and sending the read command to the UFS memory 106, which retrieves an L2P mapping entry from a partial L2P mapping table in the SRAM memory element 112 at 304. At 306, using the logical address from the partial L2P mapping table, the UFS memory 106 reads a logical block from the NAND memory element 110 and transfers the data to the SoC 102. Although not precisely to scale, the size of 306 indicates that accessing the NAND memory element 110 is relatively slow compared to accessing the SRAM memory element 112 at 304.

[0027] Signaling scenario 310 illustrates a cache miss in the computing device 100 and begins with issuing a read command 312 and sending the read command to the UFS memory 106. At 314, the UFS memory 106 looks at the SRAM memory element 112, does not find a mapping entry, and thus reads the entire L2P mapping table from the NAND memory element 110 and stores the entry in the SRAM memory element 112, introducing a delay. Then, at 316, the address is retrieved from the SRAM memory element 112. At 318, using the logical address from the partial L2P mapping table, the UFS memory 106 reads a logical block from the NAND memory element 110 and transfers the data to the SoC 102. The additional delay introduced by the cache miss can prove unacceptable.

[0028] Signaling scenario 320 begins with the UFS controller 204 accessing the DRAM element 214 at 322 to retrieve a logical address from a local L2P mapping table. Then, at 324, a read command with the logical address is sent to the UFS memory 206. At 326, using the logical address, the UFS memory 206 reads a logical block from the NAND memory element 210 and transfers the data to the SoC 202. Using the HPB in this way reduces the delay caused by the cache miss of signaling scenario 310. However, there are still cache misses, as illustrated by signaling scenario 330.

[0029] The signaling scenario 330 begins with the UFS controller 204 accessing the DRAM component 214 at 332 to retrieve a logical address from the local L2P mapping table. Then, at 334, a read command with the logical address is sent to the UFS memory 206. However, at 336, the logical address provided in the read command is incorrect, and the UFS device must read the L2P entry from the entire L2P mapping table in the NAND memory component 210. At 338, using the address from the entire L2P mapping table, the UFS memory 206 reads the logical block from the NAND memory component 210 and transfers the data to the SoC 202. Also, this cache miss may introduce unacceptable latency.

[0030] Exemplary aspects of the present disclosure reduce the probability of cache misses such as those shown in signaling scenario 330 by estimating how much of the local L2P mapping table in a local cache (e.g., DRAM) is active relative to an inactive local L2P mapping table. Based on this estimate, when the inactive portion is less than the active portion, the SoC uses only the HPB method. In essence, when the active portion is greater than the inactive portion, the SoC determines that the address is more likely to be within the active portion and is thus accurate and up-to-date. Conversely, when the inactive portion is greater than the active portion, the SoC determines that the address is more likely to be within the inactive portion and may be inaccurate and not up-to-date, and thus should not be used. In such a case, using a partial L2P mapping table in an external cache (e.g., SRAM) and its possible cache misses is more efficient than the possible cache misses of using the HPB method.

[0031] Active is a term defined in the HPB industry and, as used herein, means that an entry in the local L2P mapping table is the same as an entry in the partial L2P mapping table. Also, inactive as used herein means that an entry in the local L2P mapping table does not have an entry or has a different entry in the partial L2P mapping table. In an exemplary aspect, the UFS memory may actively (assuming initiator device control mode) transfer active and inactive addresses or regions to the SoC, such as after or during a maintenance activity (e.g., a refresh operation) at the UFS memory. Based on these updates, the SoC may update the local L2P mapping table in the local cache (e.g., DRAM).

[0032] In this regard, Figure 4An example computing device 400 including a SoC 402 is illustrated, which has a UFS host controller or control circuit 404 therein. The SoC 402 is coupled to a UFS memory 406 via a memory bus 408, which may be a UFS bus. The SoC 402 may include a memory bus interface 408A, which may be a UFS bus interface. Similarly, the UFS memory 406 may include a memory bus interface 408B. The SoC 402 may further include a local cache memory, such as DRAM 410, which stores a local L2P mapping table 412 for the UFS memory 406. In an exemplary aspect, the local L2P mapping table 412 is a whole L2P mapping table having physical addresses for each logical address. In another exemplary aspect, the local L2P mapping table 412 is a partial L2P mapping table. The presence of the DRAM 410 with the local L2P mapping table 412 contemplates that the HPB method is possible for read commands to the UFS memory 406.

[0033] The UFS memory 406 may include a memory controller 414, an external cache memory (e.g., SRAM 416), and NAND memory elements 418. The NAND memory elements 418 may store a whole L2P mapping table 420 therein, and this whole L2P mapping table 420 is always up-to-date. The SRAM 416 may be or include an external cache that includes a partial L2P mapping table 422 of the UFS memory 406 having entries corresponding to the most recently (and / or most frequently) accessed logical addresses.

[0034] As described above, exemplary aspects of the present disclosure contemplate determining the active size of the active portion of the local L2P mapping table 412 in the DRAM 410 and comparing the active size of the active portion with a threshold. The threshold may be the inactive size of the inactive portion of the local L2P mapping table 412. There are various ways to determine the active size. In an exemplary aspect, the circuit 430 may include one or more counters, registers, and comparators. When there is an update from the UFS memory 406, the counter counts each active entry and optionally each inactive entry. Then, the comparator may compare the value of the counter with the total size of the local L2P mapping table 412 stored in the register to determine a percentage, etc. In other words, the present disclosure contemplates determining the inactive size of the inactive portion of the local L2P mapping table 412 and comparing the inactive size of the inactive portion with a threshold. Similarly, there are various ways to determine the inactive size.

[0035] Based on this comparison, as Figure 5Exemplarily, two possible signaling scenarios 500 and 510 may occur. Specifically, when the control circuit 404 (e.g., using circuit 430) determines that the active portion is greater than the inactive portion, signaling scenario 500 occurs. Based on this determination, the control circuit 404 infers that the information in the local L2P mapping table 412 is more likely to be correct and blindly turns to the local L2P mapping table 412 for all read transactions. Thus, after determining that the active portion exceeds the threshold, signaling scenario 500 is similar to signaling scenario 320, starting with retrieving the logical address from the local L2P mapping table 412 in the DRAM 410 at 502, and then sending a read command containing the logical address to the UFS memory 406 at 504. This overall process is shown by the dashed line 500 in Figure 4 The UFS memory 406 then reads the logical block from the NAND memory element 418. Then, the read data is transferred to the SoC 402 at 506.

[0036] However, when the control circuit 404 determines that the active size of the active portion does not exceed the threshold (e.g., the inactive size of the inactive portion), then despite the HPB method, the exemplary aspects of the present disclosure may skip or omit the use of the local L2P mapping table 412 in the DRAM 410 and use signaling scenario 510. Signaling scenario 510 is based on the inference that random read transactions are more likely to have inaccurate addresses in the local L2P mapping table 412. Thus, in signaling scenario 510, at 512, the control circuit 404 sends a read command to the UFS memory 406 (and specifically, the SRAM 416) via the memory bus 408. At 514, the SRAM 416 checks the partial L2P mapping table 422 for the logical address. Then, at 516, the UFS memory 406 reads the logical block from the NAND memory element 418 and transfers the read data to the SoC 402. Signaling scenario 510 avoids the cache miss of signaling scenario 330 and improves performance.

[0037] Refer to Figure 6 A more complete explanation of the process 600 associated with the present disclosure is provided. Process 600 begins with initiating a read request from the file system in the SoC 402 (block 602). The host controller or control circuit 404 begins command retrieval (block 604). The control circuit 404 may determine whether the HPB is enabled (block 606).

[0038] If the answer to box 606 is no, the HPB is not enabled, process 600 enters the legacy mode and obtains an address from the memory controller 414 (box 608), which updates an entry to the SRAM 416 (box 610) and reads data from the original NAND memory element 418 (box 612). Note that this path corresponds to possible signaling scenarios 300 and 310.

[0039] However, if the answer to box 606 is yes, the HPB is enabled and process 600 determines the active size of the active portion of the local L2P mapping table 412 in the DRAM 410 (box 614). In other words, although not shown, process 600 (and specifically control circuit 404) may determine the inactive size of the inactive portion. This determination of the active size can be made directly (e.g., how many addresses are active) or indirectly (e.g., find out how many addresses are inactive and then subtract the number of inactive addresses from the total number of addresses to determine how many addresses are active). Then, control circuit 404 may compare the active size with a threshold (box 616). As described above, an exemplary threshold is the number of inactive addresses or inactive sub-regions. Note that this threshold can also be a scaled value of the inactive addresses. For example, the active size is greater than fifty-five percent of the inactive size. Another example is that if the number of active addresses exceeds the number of inactive addresses, the number of inactive addresses is actually the threshold.

[0040] Based on this comparison, process 600 branches. In the first path, control circuit 404 has determined that the active size in the DRAM 410 exceeds the inactive size (box 618). Thus, control circuit 404 obtains a physical address from the DRAM 410 (box 620), and specifically obtains the physical address from the local L2P mapping table 412. Upon receiving a read command with the physical address, the UFS memory 406 executes a transaction to read the original data from the NAND memory element 418 (box 622).

[0041] In the second path, control circuit 404 has determined that the active size in the DRAM 410 is less than the threshold (box 624). Thus, control circuit 404 obtains a physical address from the SRAM 416 (box 626), and specifically obtains the physical address from the partial L2P mapping table 422 rather than the DRAM 410. If there is no entry in the SRAM 416, the process may protect the address by entering the legacy mode as described above. Once the physical address is located, the UFS memory 406 executes a transaction to read the original data from the NAND memory element 418 (box 622).

[0042] Systems and methods for fast memory access according to aspects disclosed herein may be provided in or integrated into any processor - based device. Non - limiting examples include: set - top boxes, entertainment units, navigation devices, communication devices, fixed - location data units, mobile - location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smart phones, Session Initiation Protocol (SIP) phones, tablet devices, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi - rotor aircraft.

[0043] In this regard, Figure 7 illustrates an example of a processor - based system 700 that may employ Figures 4 to 6 the illustrated fast memory access process. While a mobile terminal with UFS memory may be particularly envisioned as being able to benefit from the exemplary aspects of the present disclosure, it should be understood that the present disclosure is not limited thereto and may be used in any system having NAND - based memory elements.

[0044] Continuing to refer to Figure 7 , the processor - based mobile terminal 700 includes an application processor 704 (sometimes referred to as the host), which communicates with a mass storage element 706 (e.g., UFS memory 406) via a UFS bus 708 (e.g., UFS bus 408). The application processor 704 may further be connected to a display 710 via a Display Serial Interface (DSI) bus 712 and to a camera 714 via a Camera Serial Interface (CSI) bus 716. Various audio components (such as a microphone 718, a speaker 720, and an audio codec 722) may be coupled to the application processor 704 via a Serial Low - Power Inter - Chip Multimedia Bus (SLIMbus) 724. Additionally, the audio components may communicate with each other via a SOUNDWIRE bus 726. A modem 728 may also be coupled to the SLIMbus 724 and / or the SOUNDWIRE bus 726. The modem 728 may further be connected to the application processor 704 via a Peripheral Component Interconnect (PCI) or a High - Speed PCI (PCIe) bus 730 and / or a System Power Management Interface (SPMI) bus 732.

[0045] Continuing to refer to Figure 7, the SPMI bus 732 can also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 734, a power management integrated circuit (PMIC) 736, an accompanying IC (sometimes referred to as a bridge chip) 738, and a radio frequency IC (RFIC) 740. It should be understood that separate PCI buses 742 and 744 can also couple the application processor 704 to the accompanying IC 738 and the WLAN IC 734. The application processor 704 can further be connected to the sensor 746 through the sensor bus 748. The modem 728 and the RFIC 740 can communicate using the bus 750.

[0046] Continuing to refer Figure 7 , the RFIC 740 can be coupled to one or more RFFE components, such as an antenna tuner 752, a switch 754, and a power amplifier 756, through a radio frequency front end (RFFE) bus 758. Additionally, the RFIC 740 can be coupled to an envelope tracking power supply (ETPS) 760 through the bus 762, and the ETPS 760 can communicate with the power amplifier 756. These RFFE components (including the RFIC 740) together can be considered an RFFE system 764. It should be understood that the RFFE bus 758 can be formed by a clock line and a data line (not illustrated).

[0047] Those skilled in the art will further understand that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the master and slave devices described herein can be employed in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functions of the various illustrative components, blocks, modules, circuits, and steps have been generally described above. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each particular application, but such specific implementation decisions should not be construed as causing a departure from the scope of the present disclosure.

[0048] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or performed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0049] Aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. The exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0050] It is also noted that the operational steps described in any of the exemplary aspects herein are described for purposes of example and discussion. The described operations may be performed in many different orders other than the illustrated order. Further, the operations described in a single operational step may in fact be performed in multiple different steps. Additionally, one or more of the operational steps discussed in the exemplary aspects may be combined. It will be understood that numerous different modifications may be made to the operational steps illustrated in the flowcharts, as will be apparent to those of ordinary skill in the art. Those of ordinary skill in the art will also understand that any of a variety of different technologies and processes may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0051] The foregoing description of the disclosure enables any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0052] Specific embodiments are described in the following numbered clauses:

[0053] 1. A system-on-chip (SoC) comprising:

[0054] A memory bus interface configured to couple to a universal flash storage (UFS) memory having an external cache memory, the external cache memory including a local logical-to-physical (L2P) mapping table of the UFS memory;

[0055] A local cache memory including a local L2P mapping table of the UFS memory; and

[0056] A control circuit coupled to the memory bus interface and the local cache memory and configured to:

[0057] Determine an active size of an active portion of the local L2P mapping table in the local cache memory; and

[0058] Compare the active size of the active portion with a threshold.

[0059] 2. The SoC according to clause 1, wherein the control circuit configured to determine the active size is configured to determine the active size by determining an inactive size of an inactive portion of the local L2P mapping table in the local cache memory.

[0060] 3. The SoC according to clause 1 or 2, wherein the threshold includes an inactive size of an inactive portion of the local L2P mapping table in the local cache memory.

[0061] 4. The SoC according to clauses 1 to 3, wherein the control circuit is further configured that when the active size does not meet the threshold:

[0062] Perform a read call by sending a read command to the external cache memory without referring to the local L2P mapping table in the local cache memory.

[0063] 5. The SoC according to clause 4, wherein the control circuit is further configured to, for the read command, retrieve the L2P mapping entry from the partial L2P mapping table in the external cache memory.

[0064] 6. The SoC according to clause 4 or 5, wherein the control circuit is further configured to, for the read command, when the partial L2P mapping table does not have an entry for the logical address in the read command, issue a direct call to the NAND memory element in the UFS memory.

[0065] 7. The SoC according to any one of the preceding clauses, wherein the control circuit is further configured to access an address within the local L2P mapping table in the local cache memory when the active size exceeds the threshold.

[0066] 8. The SoC according to any one of the preceding clauses, wherein the control circuit is further configured to synchronize the local L2P mapping table in the local cache memory to the address table in the UFS memory.

[0067] 9. The SoC according to any one of the preceding clauses, wherein the control circuit is further configured to determine whether host performance enhancement is enabled.

[0068] 10. The SoC according to any one of the preceding clauses, wherein the control circuit configured to determine the active size is determined based on how many entries are the same between the local L2P mapping table and the partial L2P mapping table.

[0069] 11. The SoC according to any one of the preceding clauses, wherein the local cache memory includes dynamic random access memory (DRAM).

[0070] 12. A system-on-chip (SoC) comprising:

[0071] A memory bus interface configured to be coupled to a universal flash storage (UFS) memory having an external cache memory, the external cache memory including a partial logical-to-physical (L2P) mapping table of the UFS memory;

[0072] A local cache memory including a local L2P mapping table of the UFS memory;

[0073] A control circuit coupled to the memory bus interface and the local cache memory and configured to:

[0074] Determine the inactive size of the inactive portion of the local L2P mapping table in the local cache memory; and

[0075] Compare the inactive size of the inactive portion with a threshold value.

[0076] 13. The SoC according to clause 12, wherein the control circuit configured to determine the inactive size is configured to determine the inactive size by determining the active size of the active portion of the local L2P mapping table in the local cache memory.

[0077] 14. The SoC according to clause 12 or 13, wherein the threshold value includes the active size of the active portion of the local L2P mapping table in the local cache memory.

[0078] 15. The SoC according to any one of clauses 12 to 14, wherein the control circuit is further configured that when the inactive size does not meet the threshold value:

[0079] Execute a read miss by sending a read command to the external cache memory without referring to the local L2P mapping table in the local cache memory.

[0080] without referring to the local L2P mapping table in the local cache memory.

[0081] 16. The SoC according to clause 15, wherein the control circuit is further configured to retrieve L2P mapping entries from the partial L2P mapping table in the external cache memory for the read command.

[0082] 17. The SoC according to clause 15, wherein the control circuit is further configured to, for the read command, when the partial L2P mapping table does not have an entry for the logical address in the read command, issue a direct call to the NAND memory element in the UFS memory.

[0083] 18. The SoC according to any one of clauses 12 to 17, wherein the control circuit is further configured to access an address within the local L2P mapping table in the local cache memory when the inactive size exceeds the threshold value.

[0084] 19. The SoC according to any one of clauses 12 to 18, wherein the control circuit is further configured to synchronize the local L2P mapping table in the local cache memory to an address table in the UFS memory.

[0085] 20. The SoC according to any one of clauses 12 to 19, wherein the control circuit is further configured to determine whether a host performance booster is enabled.

[0086] 21. The SoC according to any one of clauses 12 to 20, wherein the control circuit configured to determine the inactive size determines based on how many entries within the partial L2P mapping table are not found in the local L2P mapping table.

[0087] 22. A method of accessing a memory from a host, comprising:

[0088] determining an active size of an active portion of a local logical-to-physical (L2P) mapping table in a local cache memory associated with the host relative to a partial L2P mapping table in an external cache memory in a remote memory device; and

[0089] comparing the active size of the active portion with a threshold.

[0090] 23. The method according to clause 22, wherein determining the active size includes determining an inactive size of an inactive portion of the local L2P mapping table in the local cache memory.

[0091] 24. The method according to clause 22 or 23, wherein comparing the active size includes comparing the active size with an inactive size of an inactive portion of the local L2P mapping table in the local cache memory.

[0092] 25. The method according to any one of clauses 22 to 24, further comprising, when the active size does not meet the threshold:

[0093] performing a read invocation by sending a read command to the external cache memory without referring to the local L2P mapping table in the local cache memory.

[0094] and not referring to the local L2P mapping table in the local cache memory.

[0095] 26. The method according to clause 25, further comprising: for the read command, retrieving an L2P mapping entry from the partial L2P mapping table in the external cache memory.

[0096] 27. The method according to clause 25 or 26, further comprising, for the read command, when the partial L2P mapping table does not have an entry for a logical address in the read command, making a direct call to a NAND memory element in the UFS memory.

[0097] 28. The method according to any one of clauses 22 to 27 further includes accessing an address in the local L2P mapping table in the local cache memory when the activity size exceeds the threshold.

[0098] 29. The method according to any one of clauses 22 to 28 further includes determining whether a host performance booster is enabled.

Claims

1. A system-on-chip (SoC) comprising: A memory bus interface configured to couple to a Universal Flash Storage (UFS) memory having an external cache memory, the external cache memory including a partial logical-to-physical (L2P) mapping table of the UFS memory; A local cache memory including a local L2P mapping table of the UFS memory; And Control circuitry coupled to the memory bus interface and the local cache memory and configured to: Determine an active size of an active portion of the local L2P mapping table in the local cache memory; Compare the active size of the active portion with a threshold; And When the active size is less than the threshold: Perform a read call by sending a read command to the external cache memory without referring to the local L2P mapping table in the local cache memory.

2. The SoC of claim 1, wherein the control circuitry configured to determine the active size is configured to determine the active size by determining an inactive size of an inactive portion of the local L2P mapping table in the local cache memory.

3. The SoC of claim 1, wherein the threshold includes an inactive size of an inactive portion of the local L2P mapping table in the local cache memory.

4. The SoC of claim 1, wherein the control circuitry is further configured to, for the read command, retrieve an L2P mapping entry from the partial L2P mapping table in the external cache memory.

5. The SoC of claim 1, wherein the control circuitry is further configured to, for the read command, when the partial L2P mapping table does not have an entry for a logical address in the read command, issue a direct call to a NAND memory element in the UFS memory.

6. The SoC of claim 1, wherein the control circuitry is further configured to access an address within the local L2P mapping table in the local cache memory when the active size exceeds the threshold.

7. The SoC of claim 1, wherein the control circuitry is further configured to synchronize the local L2P mapping table in the local cache memory to an address table in the UFS memory.

8. The SoC of claim 1, wherein the control circuitry is further configured to determine whether host performance enhancement is enabled.

9. The SoC of claim 1, wherein the control circuitry configured to determine the active size is determined based on how many entries are the same between the local L2P mapping table and the partial L2P mapping table.

10. The SoC of claim 1, wherein the local cache memory includes dynamic random access memory (DRAM).

11. A system-on-chip (SoC) comprising: A memory bus interface configured to couple to a Universal Flash Storage (UFS) memory having an external cache memory, the external cache memory including a partial Logical to Physical (L2P) mapping table of the UFS memory; A local cache memory including a local L2P mapping table of the UFS memory; A control circuit coupled to the memory bus interface and the local cache memory and configured to: Determine an inactive size of an inactive portion of the local L2P mapping table in the local cache memory; Compare the inactive size of the inactive portion with a threshold; And When the inactive size exceeds the threshold: Execute a read call by sending a read command to the external cache memory without referring to the local L2P mapping table in the local cache memory.

12. The SoC according to claim 11, wherein the control circuit configured to determine the inactive size is configured to determine the inactive size by determining an active size of an active portion of the local L2P mapping table in the local cache memory.

13. The SoC according to claim 11, wherein the threshold includes an active size of an active portion of the local L2P mapping table in the local cache memory.

14. The SoC according to claim 11, wherein the control circuit is further configured to, for the read command, retrieve an L2P mapping entry from the partial L2P mapping table in the external cache memory.

15. The SoC according to claim 11, wherein the control circuit is further configured to, for the read command, when the partial L2P mapping table does not have an entry for a logical address in the read command, issue a direct call to a NAND memory element in the UFS memory.

16. The SoC according to claim 11, wherein the control circuit is further configured to access an address within the local L2P mapping table in the local cache memory when the inactive size is less than the threshold.

17. The SoC according to claim 11, wherein the control circuit is further configured to synchronize the local L2P mapping table in the local cache memory to an address table in the UFS memory.

18. The SoC according to claim 11, wherein the control circuit is further configured to determine whether a host performance booster is enabled.

19. The SoC according to claim 11, wherein the control circuit configured to determine the inactive size is determined based on how many entries within the partial L2P mapping table are not found in the local L2P mapping table.

20. A method of accessing a memory from a host, comprising: Determine an active size of an active portion of a local logical-to-physical (L2P) mapping table in a local cache memory associated with a host relative to a partial L2P mapping table in an external cache memory in a remote memory device; Compare the active size of the active portion with a threshold; And When the active size is less than the threshold: Perform a read call by sending a read command to the external cache memory without referring to the local L2P mapping table in the local cache memory.

21. The method according to claim 20, wherein determining the active size includes determining an inactive size of an inactive portion of the local L2P mapping table in the local cache memory.

22. The method according to claim 20, wherein comparing the active size includes comparing the active size with the inactive size of the inactive portion of the local L2P mapping table in the local cache memory.

23. The method according to claim 20, further comprising, for the read command, retrieving an L2P mapping entry from the partial L2P mapping table in the external cache memory.

24. The method according to claim 20, further comprising, for the read command, when the partial L2P mapping table does not have an entry for a logical address in the read command, issuing a direct call to a NAND memory element in the UFS memory.

25. The method according to claim 20, further comprising accessing an address within the local L2P mapping table in the local cache memory when the active size exceeds the threshold.

26. The method according to claim 20, further comprising determining whether a host performance booster is enabled.

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