Pressure sensor, method of manufacturing pressure sensor, air conditioning device, and vehicle

Abstract

The present disclosure provides a pressure sensor, a manufacturing method of the pressure sensor, an air conditioning device and a vehicle. The pressure sensor comprises a silicon substrate, a plurality of doped leads, a plurality of piezoresistors, a plurality of contact plugs and a sealing cover. The silicon substrate comprises opposite first and second surfaces, and the second surface is formed with a cavity. The plurality of doped leads are located in the silicon substrate and close to the first surface. The plurality of piezoresistors are formed on the first surface of the silicon substrate and correspondingly connected with the plurality of doped leads. The plurality of piezoresistors correspond to the position of the cavity. The plurality of contact plugs are formed on the first surface of the silicon substrate and correspondingly connected with the plurality of doped leads. The sealing cover is buckled on the substrate to form a closed cavity between the substrate, the plurality of piezoresistors are located in the closed cavity, and at least part of the sealing cover is connected to the region between the piezoresistors and the contact plugs on the first surface. The pressure sensor provided by the present disclosure improves the reliability of the pressure sensor.

Description

Technical Field

[0001] This disclosure relates to the field of sensors, and more specifically, to a pressure sensor, a method for manufacturing the pressure sensor, an air conditioning device, and a vehicle. Background Technology

[0002] With the development of new energy vehicle technology and the general trend of energy conservation and environmental protection, the market penetration rate of new energy vehicles is gradually increasing, becoming a development trend in the automotive industry. Since new energy vehicles lack an engine heat source, they require additional electricity for heating, resulting in low conversion efficiency. Therefore, air conditioning heating has become the largest non-power loss in new energy vehicles. Due to the limitations of battery and fast-charging technology, which are difficult to improve and have long development cycles, optimizing the energy consumption of onboard thermal management systems has become an important development direction for new energy vehicles.

[0003] In vehicle thermal management systems, pressure sensors are placed in the refrigerant piping. By sensing the pressure in the piping, the operating power of the compressor and evaporator is adjusted to achieve temperature control and energy saving. Therefore, the requirements for pressure sensors are becoming increasingly stringent.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a pressure sensor, a method for manufacturing the pressure sensor, an air conditioning device, and a vehicle, thereby improving the reliability of the pressure sensor.

[0006] According to one aspect of this disclosure, a pressure sensor is provided, the pressure sensor comprising:

[0007] A silicon substrate, the silicon substrate including opposite first and second surfaces, the second surface having a cavity formed therein;

[0008] Multiple doped leads, wherein the multiple doped leads are located in the silicon substrate and close to the first surface;

[0009] Multiple varistors are formed on the first surface of the silicon substrate, and the multiple varistors are connected to the multiple doped leads accordingly; the multiple varistors correspond to the positions of the cavity;

[0010] Multiple contact plugs are formed on the first surface of the silicon substrate, and the multiple contact plugs are correspondingly connected to multiple doped leads;

[0011] A sealing cover is fastened to the substrate to form a sealed cavity between the sealing cover and the substrate. A plurality of varistors are located in the sealed cavity, and at least a portion of the sealing cover is connected to the area between the varistors and the contact plug on the first surface.

[0012] In one exemplary embodiment of this disclosure, the pressure sensor further includes:

[0013] A molding compound layer is located on the silicon substrate and the contact plug, and is located around the periphery of the sealing cover;

[0014] A conductive post is located in a via of the molding compound, with one end connected to the contact plug and the other end exposed from the side of the molding compound away from the silicon substrate.

[0015] In one exemplary embodiment of this disclosure, the pressure sensor further includes:

[0016] A metal layer is formed at one end of the conductive pillar away from the silicon substrate;

[0017] A contact terminal is formed on the side of the metal layer opposite to the silicon substrate.

[0018] According to another aspect of this disclosure, a method for manufacturing a pressure sensor is provided, the method comprising:

[0019] A silicon substrate is provided, the silicon substrate comprising opposite first and second surfaces;

[0020] Multiple doped leads are formed in the silicon substrate, close to the first surface and spaced apart.

[0021] A plurality of varistors are formed on the first surface of the silicon substrate, and the plurality of varistors are connected to the plurality of doped leads accordingly;

[0022] A plurality of contact plugs are formed on the first surface of the silicon substrate, and the plurality of contact plugs are connected to the plurality of doped leads accordingly;

[0023] A sealing cover is formed on a first surface of the silicon substrate. The sealing cover is fastened to the substrate and forms a sealed cavity between the sealing cover and the substrate. A plurality of varistors are located in the sealed cavity, and at least a portion of the sealing cover is connected to the area between the varistors and the contact plug on the first surface.

[0024] A cavity is formed on the second surface of the silicon substrate, and the position of the cavity corresponds to the position of the varistor.

[0025] In one exemplary embodiment of this disclosure, the manufacturing method further includes:

[0026] A conductive post and a molding compound are disposed on a first surface of the silicon substrate. The molding compound is located on the silicon substrate and is located around the periphery of the sealing cover. The conductive post is located in the molding compound, with one end connected to the contact plug and the other end exposed from the side of the molding compound away from the silicon substrate.

[0027] In one exemplary embodiment of this disclosure, a sealing cover, conductive pillars, and a molding layer are formed on a first surface of the silicon substrate, including:

[0028] A conductive post is formed on the contact plug;

[0029] A sealing cover is provided, and the sealing cover is fastened onto the silicon substrate;

[0030] A plastic encapsulation layer is formed on the silicon substrate and around the periphery of the sealing cover, encapsulating the conductive pillar, with the conductive pillar exposed from the side of the plastic encapsulation layer away from the silicon substrate.

[0031] In one exemplary embodiment of this disclosure, a sealing cover is formed on a first surface of the silicon substrate, comprising:

[0032] A sealing cover is provided, the sealing cover including a sealing part and a clamping part;

[0033] The sealing cover is fastened onto the silicon substrate, and the sealing part forms the sealed cavity between the sealing part and the silicon substrate. The clamping part is located on the side of the sealing part away from the silicon substrate.

[0034] The sealing cover is thinned to remove the clamping portion.

[0035] In one exemplary embodiment of this disclosure, a sealing cover is provided, comprising:

[0036] Provide glass substrates;

[0037] Laser-induced technology is used to modify a predetermined area of ​​the glass substrate; then, the glass sheet is etched with an etching solution to obtain a first recess in the middle region of the glass substrate and a second recess in the edge region. The portion of the glass substrate that forms the first recess is the sealing portion, and the portion that forms the second recess is the clamping portion.

[0038] In one exemplary embodiment of this disclosure, a sealing cover, conductive pillars, and a molding layer are formed on a first surface of the silicon substrate, including:

[0039] A sealing cover is provided, and the sealing cover is fastened onto the silicon substrate;

[0040] A molding layer is formed on the silicon substrate and around the periphery of the sealing cover;

[0041] A via is formed in the encapsulation layer, and a conductive post connecting the contact plug is formed in the via.

[0042] In one exemplary embodiment of this disclosure, a sealing cover is formed on a first surface of the silicon substrate, comprising:

[0043] Silicon wafers are supplied;

[0044] A protrusion is formed on one side of the silicon wafer to connect with the silicon substrate;

[0045] The silicon wafer is fastened onto the silicon substrate, and the protrusion is connected to the silicon substrate;

[0046] Remove the portion of the silicon wafer near the periphery of the protrusion.

[0047] In one exemplary embodiment of this disclosure, prior to providing the sealing cover, the manufacturing method further includes: forming a protective layer at least on the contact plug;

[0048] After attaching the sealing cover to the silicon substrate, the manufacturing method further includes removing the protective layer.

[0049] In an exemplary embodiment of this disclosure, before forming a plurality of doped leads spaced apart from the first surface in the silicon substrate, the manufacturing method further includes: forming a first positioning mark on the silicon substrate;

[0050] Forming a sealing cover on a first surface of the silicon substrate includes: providing a sealing cover, on which a second positioning mark is formed; and forming a snap-fit ​​positioning between the sealing cover and the silicon substrate by means of the first positioning mark and the second positioning mark.

[0051] In one exemplary embodiment of this disclosure, the manufacturing method further includes:

[0052] A metal layer is formed at the end of the conductive pillar that is away from the silicon substrate;

[0053] A contact terminal is formed on the side of the metal layer opposite to the silicon substrate.

[0054] According to another aspect of this disclosure, an air conditioning device is provided, which includes the pressure sensor described above.

[0055] According to another aspect of this disclosure, a vehicle is provided that includes the aforementioned air conditioning unit.

[0056] The pressure sensor disclosed herein comprises multiple varistors connected by multiple doped leads to form a Wheatstone bridge. The doped leads can be led out to connect to external circuits via contact plugs. The doped leads connecting the varistors and contact plugs are located within the silicon substrate, i.e., not directly exposed from the surface of the silicon substrate. Since the varistors are located within the area covered by the sealing cover on the silicon substrate, and the contact plugs are located outside the area covered by the sealing cover on the silicon substrate, the sealing cover and the doped leads inevitably have overlapping portions. Because the doped leads are located within the silicon substrate and not directly exposed from the surface of the silicon substrate, there are no protruding metal traces on the bonding surface, avoiding the sealing cover being located on metal traces. The bonding surfaces of the sealing cover and the silicon substrate are both located on the surface of the silicon substrate, thereby achieving a good bonding effect between the sealing cover and the silicon substrate, avoiding the influence of metal traces on the bonding yield, improving the airtightness of the sealed cavity, and improving the accuracy of the measurement results.

[0057] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0058] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0059] Figure 1 This is a schematic diagram of a pressure sensor provided for one embodiment of the present disclosure.

[0060] Figures 2 to 14 A process diagram illustrating a method for manufacturing a pressure sensor according to an embodiment of this disclosure.

[0061] Figures 15-30 A process diagram illustrating a method for manufacturing a pressure sensor according to another embodiment of this disclosure.

[0062] Figure 31 A flowchart illustrating a method for manufacturing a pressure sensor according to an embodiment of this disclosure.

[0063] Figure 32 A schematic diagram of a Wheatstone bridge provided for one embodiment of this disclosure.

[0064] Explanation of reference numerals in the attached figures:

[0065] 100. Silicon substrate; 110. First positioning mark; 120. Doped lead; 130. Varistor; 140. Contact plug; 150. Cavity; 160. Protective layer;

[0066] 200, Sealing cover; 210, Second positioning mark; 221, Sealing part; 222, Clamping part; 231, First recessed part; 232, Second recessed part; 233, Protrusion;

[0067] 300. Sealed cavity;

[0068] 410, Conductive post; 420, Molding layer; 421, Via; 430, Metal layer; 440, Contact terminal. Detailed Implementation

[0069] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0070] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0071] The terms “a,” “one,” “the,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first” and “second” are used only as markers and are not a limitation on the number of objects.

[0072] MEMS pressure sensors utilize the piezoresistive effect principle. Through integrated process technology, strain resistors are fabricated along specific crystal orientations on a single-crystal silicon wafer by doping and diffusion, forming a Wheatstone bridge. Taking advantage of the elastic mechanical properties of silicon, anisotropic micromachining is performed on the same silicon material to create a diffused silicon sensor that integrates force sensitivity and force-to-electricity conversion detection.

[0073] MEMS pressure sensors typically have four piezoresistors fabricated on the silicon diaphragm, such as... Figure 32As shown, R1, R2, R3, and R4 are four varistors with equal resistance. They form a Wheatstone bridge on the silicon film. When no external force is applied, the bridge is balanced and the output voltage is zero. When the diaphragm is subjected to external pressure, the bridge loses its balance. By applying an excitation power supply to the bridge, an output voltage proportional to the measured pressure can be obtained, thereby achieving the purpose of measuring pressure.

[0074] The embodiments of this disclosure first provide a pressure sensor, such as Figure 1 As shown, the pressure sensor includes: a silicon substrate 100, multiple doped leads 120, multiple piezoresistors 130, multiple contact plugs 140, and a sealing cover 200.

[0075] The silicon substrate 100 includes a first surface and a second surface opposite to each other, with a cavity 150 formed on the second surface; multiple doped leads 120 are located in the silicon substrate 100 and close to the first surface; multiple varistors 130 are formed on the first surface of the silicon substrate 100, and the multiple varistors 130 are correspondingly connected to the multiple doped leads 120; the multiple varistors 130 are positioned corresponding to the cavity 150; multiple contact plugs 140 are formed on the first surface of the silicon substrate 100, and the multiple contact plugs 140 are correspondingly connected to the multiple doped leads 120; a sealing cover 200 is fastened to the silicon substrate 100 and forms a sealed cavity 300 between the silicon substrate 100 and the silicon substrate 100, the multiple varistors 130 are located in the sealed cavity 300, and at least a portion of the sealing cover 200 is connected to the area between the varistors 130 and the contact plugs 140 on the first surface.

[0076] The sealed cavity 300 formed between the sealing cover 200 and the silicon substrate 100 of the MEMS pressure sensor has airtightness requirements. The sealed cavity 300 is obtained by bonding the sealing cover 200 to the silicon substrate 100. When the metal trace or metal pad is higher than the surface of the silicon substrate 100, the electrical signal of the piezoresistor 130 in the sealed cavity 300 after bonding needs to be led out by the metal trace. The bonding area covers the metal trace. Direct bonding between the metal trace and the silicon / glass material sealing cover 200 will lead to incomplete bonding or even gaps, resulting in poor bonding. This will lead to poor airtightness in the sealed cavity 300, ultimately affecting the accuracy of the measurement results.

[0077] The pressure sensor disclosed herein comprises multiple pressure-sensitive resistors 130 connected by multiple doped leads 120 to form a Wheatstone bridge. The doped leads 120 are led out through contact plugs 140 to connect to external circuits. The doped leads 120 connecting the pressure-sensitive resistors 130 and the contact plugs 140 are located within the silicon substrate 100, i.e., not directly exposed from the surface of the silicon substrate 100. Since the pressure-sensitive resistors 130 are located within the area covered by the sealing cover 200 on the silicon substrate 100, and the contact plugs 140 are located outside the area covered by the sealing cover 200 on the silicon substrate 100, therefore, the sealing... The cover 200 and the doped lead 120 inevitably have an intersection. Since the doped lead 120 is located in the silicon substrate 100 and does not directly expose from the surface of the silicon substrate 100, there are no protruding metal traces on the bonding surface. This avoids the cover 200 being located on the metal traces. The bonding surfaces of the cover 200 and the silicon substrate 100 are both located on the surface of the silicon substrate 100, which results in a good bonding effect between the cover 200 and the silicon substrate 100. This avoids the influence of metal traces on the bonding yield, improves the airtightness of the sealed cavity 300, and improves the accuracy of the measurement results.

[0078] Specifically, four varistors 130 may be formed on the silicon substrate 100, and the four varistors 130 may be connected together by doped leads 120 located in the silicon substrate 100; or, the portion of the leads connecting the four varistors 130 that overlaps with the bonding region of the sealing cover 200 may be made of doped leads 120 located in the silicon substrate 100, and the portion that does not overlap with the spacing region of the sealing cover 200 may be made of conductive leads located on the silicon substrate 100.

[0079] The doped leads 120 can be formed in the silicon substrate 100 by ion implantation technology. The depth of the doped leads 120 is sufficient to not affect the bonding of the sealing cover 200 to the surface of the silicon substrate 100. This disclosure does not impose any restrictions on this.

[0080] like Figure 1 As shown, the pressure sensor also includes a molding compound 420 and a conductive post 410. The molding compound 420 is located on the silicon substrate 100 and the contact plug 140, and is located on the periphery of the sealing cover 200. The conductive post 410 is located in the through hole 421 of the molding compound 420, and one end is connected to the contact plug 140, while the other end is exposed from the side of the molding compound 420 away from the silicon substrate 100.

[0081] The molding layer 420 surrounds the sealing cover 200, replacing the original sealing cover structure. When the conductive pillar 410 is set, a via 421 can be formed in the molding layer 420, thus avoiding the formation of vias on the sealing cover 200. When the sealing cover 200 is made of glass, the processing efficiency of deep glass trenches is low. Traditional deep glass trench processing uses ICP etching (Inductively Coupled Plasma), but the etching rate of glass material is slow, less than 1μm / min, which is very inefficient. Moreover, the temperature rises continuously during the etching process, and the excessive temperature can easily damage the glass. When the sealing cover 200 is a silicon wafer, when a via 421 is formed on the silicon wafer, over-etching will cause damage to the structural layer silicon wafer and metal traces. The depth of deep silicon etching is uncontrollable, and the thickness within the silicon wafer fluctuates. Deep silicon etching must use over-etching, and the structural wafer is easily etched without a protective layer.

[0082] When the sealing cover 200 is made of glass, the TGV (Glass Through-Via) / TSV (Through Silicon Via) and the silicon substrate 100 delaminate and crack. The CTE (Coefficient of Thermal Expansion) of the TGV / TSV metal and materials such as silicon wafers, glass sheets, and PI (Polyimide) differs significantly. The MEMS device manufacturing process involves multiple thermal processes, such as PI adhesive curing and Cu Pillar reflow. During the process, the materials expand and contract with temperature rise and fall. The different CTEs and thermal stresses of the materials lead to different expansion and contraction, which causes pulling or squeezing, resulting in delamination and cracking between materials. The thermal problems between the TGV / TSV metal and the silicon wafers and glass sheets are even more serious.

[0083] This disclosure forms a molding compound 420 around the periphery of the sealing cover 200, and forms a conductive post 410 connecting the contact plug 140 in the molding compound 420. That is, the molding compound material is used to replace part of the silicon material sealing cover 200 or the glass material sealing cover 200, that is, TMV (molded through-hole) replaces TSV / TGV. This reduces the difficulty of the electroplating filling process, improves the thermal stress problem caused by CTE mismatch, such as material cracks and warping, and improves the yield of pressure sensors.

[0084] like Figure 1 As shown, the pressure sensor also includes a metal layer 430 and a contact terminal 440. The metal layer 430 is formed at one end of the conductive post 410 away from the silicon substrate 100, and the contact terminal is formed on the side of the metal layer 430 away from the silicon substrate 100.

[0085] In this process, grooves are formed at the ends of the conductive pillars 410 through etching and other processes. Then, a metal layer 430 is formed on the grooves of the conductive pillars 410 through a deposition process. The metal layer 430 is formed conformally on the ends of the conductive pillars 410, that is, grooves are also formed on the surface of the metal layer 430. A seed layer is made using PVD (Physical Vapor Deposition) technology. The pattern is obtained by photolithography, resulting in photoresist grooves. The seed layer is thickened using electroplating technology. The photoresist is removed by stripping solution and cleaning. The surface seed layer is removed using etching technology. Finally, a nickel-palladium metal layer is formed on the copper layer using chemical plating technology.

[0086] Contact terminals 440 can be formed on the metal layer 430 through processes such as applying flux, placing solder balls, reflowing, and cleaning. The contact terminals 440 can be solder balls.

[0087] like Figure 1 As shown, a cavity 150 is formed on the side of the silicon substrate 100 away from the sealing cover 200, and the positions of multiple piezoresistors 130 correspond to the positions of the cavity 150. When the silicon substrate 100 is subjected to external pressure, the resistance of the piezoresistors 130 changes, causing the bridge circuit to become unbalanced. By applying an excitation power supply to the bridge circuit, an output voltage proportional to the measured pressure can be obtained, thereby achieving the purpose of measuring pressure.

[0088] Embodiments of this disclosure also provide a method for manufacturing a pressure sensor, such as... Figure 31 As shown, the manufacturing method of the pressure sensor includes:

[0089] Step S100: Provide a silicon substrate, the silicon substrate including a first side and a second side opposite to each other;

[0090] Step S200: Form multiple doped leads in the silicon substrate that are close to the first surface and spaced apart;

[0091] Step S300: A plurality of varistors are formed on the first surface of the silicon substrate, and the plurality of varistors are connected to a plurality of doped leads accordingly;

[0092] Step S400: A plurality of contact plugs are formed on the first surface of the silicon substrate, and the plurality of contact plugs are connected to a plurality of doped leads accordingly;

[0093] Step S500: A sealing cover is formed on the first surface of the silicon substrate. The sealing cover is fastened to the substrate and a closed cavity is formed between the sealing cover and the substrate. A plurality of varistors are located in the closed cavity, and at least a portion of the sealing cover is connected to the area between the varistor and the contact plug on the first surface.

[0094] Step S600: A cavity is formed on the second side of the silicon substrate, and the position of the groove corresponds to the position of the varistor.

[0095] The pressure sensor manufacturing method disclosed herein allows multiple varistors to be connected via multiple doped leads to form a Wheatstone bridge. These doped leads are led out through contact plugs to connect to external circuits. The doped leads connecting the varistors and contact plugs are formed within a silicon substrate, i.e., not directly exposed from the surface of the silicon substrate. Since the varistors are located within the area covered by a sealing cover on the silicon substrate, and the contact plugs are located outside the area covered by the sealing cover, the sealing cover and the doped leads inevitably have overlapping portions. Because the doped leads are located within the silicon substrate and not directly exposed from the surface, there are no protruding metal traces on the bonding surface, thus avoiding the sealing cover being located on metal traces. The bonding surfaces of the sealing cover and the silicon substrate are both located on the surface of the silicon substrate, resulting in a good bonding effect between the sealing cover and the silicon substrate. This avoids the influence of metal traces on the bonding yield, improves the airtightness of the sealed cavity, and enhances the accuracy of the measurement results.

[0096] In one embodiment, the detailed description of each step in the method for manufacturing the pressure sensor provided in this disclosure is as follows.

[0097] In step S100, a silicon substrate is provided, the silicon substrate including a first side and a second side opposite to each other.

[0098] Specifically, such as Figure 2 As shown, a silicon wafer is provided, and the silicon wafer is ultrasonically cleaned with acetone and isopropanol (IPA) organic matter, followed by RCA standard cleaning (wet chemical cleaning method). After cleaning, the silicon wafer is baked in an oven to ensure that the silicon wafer is clean and dry, forming a silicon substrate 100.

[0099] Specifically, a first positioning mark 110 can be formed on the silicon substrate 100. The surface of the silicon substrate 100 can be oxidized using a high-temperature oxidation process on the first side of the silicon substrate 100, i.e. the bonding surface. The patterning is completed using photolithography, including photoresist coating, pre-baking, exposure, and development. The silicon substrate 100 is etched using DRIE (deep silicon etching) technology to obtain a groove of a specified shape as the first positioning mark 110. Finally, the substrate is cleaned using a photoresist remover.

[0100] In step S200, multiple doped leads are formed in the silicon substrate, close to the first surface and spaced apart.

[0101] Specifically, such as Figure 3 As shown, a patterned photoresist layer is formed on the bonding surface of the silicon substrate 100 using photolithography. The steps include photoresist coating, pre-baking, exposure, and development. The patterned photoresist layer exposes the area on the silicon substrate 100 where doped leads 120 need to be formed. Then, the silicon substrate 100 is doped using ion implantation technology to form multiple doped leads 120 in the silicon substrate 100. After the doped leads 120 are formed, the photoresist can be removed by photoresist removal solution.

[0102] The area where doped leads 120 need to be formed can be preset in advance, that is, the pattern formed on the photoresist layer is preset.

[0103] In step S300, a plurality of varistors are formed on the first surface of the silicon substrate, and the plurality of varistors are connected to a plurality of doped leads.

[0104] Specifically, such as Figure 4 As shown, a patterned photoresist layer is formed on the bonding surface of the silicon substrate 100 using photolithography. The steps include photoresist coating, pre-baking, exposure, and development. The patterned photoresist layer exposes the area on the silicon substrate 100 where the varistor 130 needs to be formed. Then, the silicon substrate 100 is doped using ion implantation technology to form multiple varistors 130 in the silicon substrate 100. After the varistor 130 is formed, the photoresist can be removed by removing the photoresist with a photoresist remover.

[0105] Among them, an integrated process technology can be used to dope and diffuse along a specific crystal orientation on a single-crystal silicon substrate 100 to form a strain resistor, which constitutes a Wheatstone bridge. By utilizing the elastic mechanical properties of silicon material, anisotropic micromachining can be performed on the same silicon material to produce a diffused silicon sensor that integrates force sensitivity and force-to-electric conversion detection.

[0106] The area where the varistor 130 needs to be formed can be preset in advance, that is, the pattern formed on the photoresist layer is preset.

[0107] In step S400, a plurality of contact plugs are formed on the first surface of the silicon substrate, and the plurality of contact plugs are connected to a plurality of doped leads.

[0108] Specifically, such as Figure 5 As shown, a photoresist material layer is formed on the first surface of the silicon substrate 100. The photoresist material layer is patterned using photolithography to form a patterned photoresist layer. The silicon above the doped layer in the silicon substrate 100 is removed using dry etching or wet etching techniques to obtain a silicon trench. The photoresist layer is then cleaned using a resist remover. A seed layer is then fabricated using a deposition process, such as PVD. The silicon trench is then filled using electroplating. Finally, excess metal is removed using a chemical mechanical polishing (CMP) process to form multiple contact plugs 140 that are connected to the multiple doped leads 120.

[0109] like Figure 6 As shown, after the contact plug 140 is formed, conductive pillars 410 are then formed on the contact plug 140. The conductive pillars 410 of the contact plug 140 are formed by photolithography on the silicon substrate 100 and by PVD, electroplating, and resist removal processes.

[0110] Among them, the conductive post 410 can be a copper post.

[0111] In step S500, a sealing cover is formed on the first surface of the silicon substrate. The sealing cover is fastened to the substrate and a sealed cavity is formed between the sealing cover and the substrate. A plurality of varistors are located in the sealed cavity, and at least a portion of the sealing cover is connected to the area between the varistors and the contact plug on the first surface.

[0112] Specifically, the sealing cover 200 can be a glass cover, such as... Figure 7 As shown, a glass substrate is provided; as Figure 8 As shown, shallow grooves and deep grooves are made on the glass substrate to form shallow grooves and deep grooves, namely a first recess 231 and a second recess 232, thereby making the formed sealing cover 200 include a sealing part 221 and a clamping part 222.

[0113] The formation of the first recess 231 and the second recess 232 is equivalent to the formation of a bonding ring on the glass cover. The bonding ring in the glass cover process participates in the bonding, reducing the bonding area and thus reducing the bonding pressure, preventing excessive pressure from damaging the silicon substrate 100, while improving the bonding yield and airtightness.

[0114] In this process, a laser-induced glass substrate can be used to modify a predetermined area of ​​the glass substrate. Then, an etching solution is used to etch the glass sheet, resulting in a first recess 231 located in the middle region of the glass substrate and a second recess 232 located in the edge region. The portion of the glass substrate forming the first recess 231 serves as a sealing portion 221, and the portion forming the second recess 232 serves as a clamping portion 222. The etching solution can be, for example, an acidic solution or an alkaline solution; an acidic solution can be, for example, hydrofluoric acid (HF), and an alkaline solution can be, for example, sodium hydroxide (NaOH).

[0115] like Figure 9 As shown, the sealing cover 200 is then fastened onto the silicon substrate 100, so that the sealing cover 200 and the silicon substrate 100 are bonded together, and a sealed cavity 300 is formed between the sealing part 221 of the sealing cover 200 and the silicon substrate 100, and the clamping part 222 is located on the side of the sealing part 221 away from the silicon substrate 100.

[0116] The sealing cover 200 may also form a second positioning mark 210. The first positioning mark 110 and the second positioning mark 210 form a snap-fit ​​positioning between the sealing cover 200 and the silicon substrate 100, that is, the positioning during bonding.

[0117] When forming the second positioning mark 210 on the sealing cover 200, the glass substrate can be ultrasonically cleaned using acetone and isopropanol, followed by RCA standard cleaning. After cleaning, the glass substrate is baked in an oven to ensure the silicon wafer is clean and dry. Patterning is achieved using photolithography, including photoresist coating, pre-baking, exposure, and development. Wet etching is then used to etch a groove of a specified shape on the bottom of the glass substrate as the second positioning mark 210. Finally, a photoresist remover is used for cleaning.

[0118] like Figure 10 As shown, a glass thinning process can be used to thin the sealing cover 200 to a certain thickness in order to remove the clamping part 222.

[0119] like Figure 11 As shown, using vacuum technology, molding compound is applied to the silicon substrate 100 and the sealing cover 200. Then, grinding and thinning technology is used to thin the molding compound to a specified thickness, exposing the copper pillars and the sealing cover 200, forming the molding layer 420.

[0120] The molding layer 420 surrounds the sealing cover 200, replacing the original sealing cover 200 structure. When the conductive pillars 410 are set, vias can be formed in the molding layer 420, thus avoiding the formation of vias on the sealing cover 200. When the sealing cover 200 is made of glass, TGV / TSV delaminates and cracks with the wafer. The CTE of TGV / TSV metal differs significantly from that of silicon wafers, glass wafers, PI, and other materials. MEMS device manufacturing processes involve multiple thermal processes, such as PI adhesive curing and CuPillar reflow. During the process, the materials expand and contract with heating and cooling. Different CTEs and thermal stresses of materials lead to different expansion and contraction, causing tension or compression, which in turn leads to delamination and cracking between materials. The thermal problems between TGV / TSV metal and silicon wafers and glass wafers are even more severe.

[0121] This disclosure improves the yield of pressure sensors by forming a plastic sealing layer 420 around the sealing cover 200 and forming a conductive post 410 connecting the contact plug 140 in the plastic sealing layer 420, that is, using a plastic sealing material instead of a glass material for the sealing cover 200, i.e., TMV instead of TGV / TSV. This reduces the difficulty of the electroplating filling process, improves the thermal stress problems caused by CTE mismatch, such as material cracks and warping.

[0122] In step S600, a cavity is formed on the second surface of the silicon substrate 100, and the position of the cavity corresponds to the position of the varistor 130.

[0123] Specifically, such as Figure 13As shown, a cavity 150 is formed on the second surface of the silicon substrate 100, and the positions of multiple varistors 130 correspond to the positions of the cavity 150. When the silicon substrate 100 is subjected to external pressure, the resistance of the varistor 130 changes, causing the bridge circuit to become unbalanced. By applying an excitation power supply to the bridge circuit, an output voltage proportional to the measured pressure can be obtained, thereby achieving the purpose of measuring pressure.

[0124] like Figure 12 As shown, before forming the cavity 150 on the second surface of the silicon substrate 100, a metal layer 430 (UBM) is formed at the end of the conductive pillar 410. Grooves can be formed at the end of the conductive pillar 410 through processes such as etching. Then, the metal layer 430 is formed on the grooves of the conductive pillar 410 through a deposition process. The metal layer 430 is formed conformally on the end of the conductive pillar 410, meaning that grooves are also formed on the surface of the metal layer 430. For example, a seed layer can be created using electroplating technology and PVD technology; a photolithography technique can be used to pattern the photoresist grooves; the seed layer can be thickened using electroplating technology; a resist remover can be used for cleaning; the surface seed layer can be removed using etching technology; and a nickel-palladium metal layer can be formed on the copper layer using chemical plating technology. The UBM structure may include an adhesive layer, a barrier layer, a wetting layer, and an antioxidant layer covering the conductive pillar 410.

[0125] like Figure 14 As shown, contact terminals 440 can be formed on metal layer 430 through processes such as applying flux, placing solder balls, reflowing, and cleaning. Contact terminals 440 can be solder balls.

[0126] Alternatively, after forming a cavity 150 on the second surface of the silicon substrate 100, a metal layer 430 may be formed at the end of the conductive pillar 410. This disclosure does not limit this.

[0127] In another embodiment, the detailed description of each step in the method for manufacturing the pressure sensor provided in this disclosure is as follows.

[0128] In step S100, a silicon substrate is provided, the silicon substrate including a first side and a second side opposite to each other.

[0129] Specifically, such as Figure 15 As shown, a silicon wafer is provided, and the silicon wafer is ultrasonically cleaned using acetone + isopropanol (IPA) organic matter, followed by RCA standard cleaning. After cleaning, the silicon wafer is baked in an oven to ensure that the silicon wafer is clean and dry, forming a silicon substrate 100.

[0130] Specifically, a first positioning mark 110 can be formed on the silicon substrate 100. The surface of the silicon substrate 100 can be oxidized using a high-temperature oxidation process on the first side of the silicon substrate 100, i.e. the bonding surface. The patterning is completed using photolithography, including photoresist coating, pre-baking, exposure, and development. The silicon substrate 100 is etched using DRIE (deep silicon etching) technology to obtain a groove of a specified shape as the first positioning mark 110. Finally, the substrate is cleaned using a photoresist remover.

[0131] In step S200, multiple doped leads are formed in the silicon substrate, close to the first surface and spaced apart.

[0132] Specifically, such as Figure 16 As shown, a patterned photoresist layer is formed on the bonding surface of the silicon substrate 100 using photolithography. The steps include photoresist coating, pre-baking, exposure, and development. The patterned photoresist layer exposes the area on the silicon substrate 100 where doped leads 120 need to be formed. Then, the silicon substrate 100 is doped using ion implantation technology to form multiple doped leads 120 in the silicon substrate 100. After the doped leads 120 are formed, the photoresist can be removed by photoresist removal solution.

[0133] The area where doped leads 120 need to be formed can be preset in advance, that is, the pattern formed on the photoresist layer is preset.

[0134] In step S300, a plurality of varistors are formed on the first surface of the silicon substrate, and the plurality of varistors are connected to a plurality of doped leads.

[0135] Specifically, such as Figure 17 As shown, a patterned photoresist layer is formed on the bonding surface of the silicon substrate 100 using photolithography. The steps include photoresist coating, pre-baking, exposure, and development. The patterned photoresist layer exposes the area on the silicon substrate 100 where the varistor 130 needs to be formed. Then, the silicon substrate 100 is doped using ion implantation technology to form multiple varistors 130 in the silicon substrate 100. After the varistor 130 is formed, the photoresist can be removed by removing the photoresist with a photoresist remover.

[0136] Among them, an integrated process technology can be used to dope and diffuse along a specific crystal orientation on a single-crystal silicon substrate 100 to form a strain resistor, which constitutes a Wheatstone bridge. By utilizing the elastic mechanical properties of silicon material, anisotropic micromachining can be performed on the same silicon material to produce a diffused silicon sensor that integrates force sensitivity and force-to-electric conversion detection.

[0137] The area where the varistor 130 needs to be formed can be preset in advance, that is, the pattern formed on the photoresist layer is preset.

[0138] In step S400, a plurality of contact plugs are formed on the first surface of the silicon substrate, and the plurality of contact plugs are connected to a plurality of doped leads.

[0139] Specifically, such as Figure 18 As shown, a photoresist material layer is formed on the first surface of the silicon substrate 100. The photoresist material layer is patterned using photolithography to form a patterned photoresist layer. Then, the silicon above the doped layer in the silicon substrate 100 is removed using etching technology to obtain a silicon trench. Next, the photoresist layer is cleaned using a resist remover. Then, a seed layer is formed using a deposition process, such as PVD. Then, the silicon trench is filled using electroplating technology. Finally, excess metal is removed using a chemical mechanical polishing (CMP) process to form multiple contact plugs 140 that are connected to multiple doped leads 120.

[0140] In step S500, a sealing cover is formed on the first surface of the silicon substrate. The sealing cover is fastened to the substrate and a sealed cavity is formed between the sealing cover and the substrate. A plurality of varistors are located in the sealed cavity, and at least a portion of the sealing cover is connected to the area between the varistors and the contact plug on the first surface.

[0141] Specifically, such as Figure 19 As shown, at least a protective layer 160 is formed on the contact plug 140.

[0142] like Figure 20 As shown, a silicon wafer is provided. The wafer is ultrasonically cleaned using acetone and isopropanol, followed by RCA standard cleaning. After cleaning, the wafer is baked in an oven to ensure it is clean and dry. A second positioning mark 210 can be formed on the silicon wafer. Patterning is achieved using photolithography, including photoresist coating, pre-baking, exposure, and development. Using DRIE technology, grooves of a specified shape are etched onto the silicon wafer to serve as the second positioning mark 210. Finally, a photoresist remover is used for cleaning.

[0143] like Figure 21 As shown, a protrusion 233 connected to the silicon substrate 100 is formed on one side of the silicon wafer. Patterning is completed using photolithography, the steps of which include photoresist coating, pre-baking, exposure, and development; using DRIE technology, the silicon wafer is etched to obtain a groove of a specified shape as a second positioning mark 210; finally, the silicon wafer is cleaned using a photoresist remover.

[0144] like Figure 22 As shown, a silicon wafer is fastened onto a silicon substrate 100, and a protrusion 233 is connected to the silicon substrate 100, so that the sealing cover 200 is bonded to the silicon substrate 100. A sealed cavity 300 is formed between the sealing part 221 of the sealing cover 200 and the silicon substrate 100, and the clamping part 222 is located on the side of the sealing part 221 away from the silicon substrate 100.

[0145] The sealing cover 200 has a second positioning mark 210. The first positioning mark 110 and the second positioning mark 210 form a snap-fit ​​positioning between the sealing cover 200 and the silicon substrate 100, that is, the positioning during bonding.

[0146] like Figure 23 As shown, a thinning process can be used to thin the silicon wafer to a certain thickness.

[0147] like Figure 24 As shown, patterning can be achieved using photolithography, the steps of which include photoresist coating, pre-baking, exposure, and development; using DRIE technology, the silicon wafer is etched to remove the portion near the periphery of the protrusion 233, i.e., the clamping portion 222, and finally, the photoresist is removed and cleaned using a photoresist remover.

[0148] like Figure 25 As shown, the protective layer 160 on the bonding surface of the silicon wafer is then removed using a wet etching process; using vacuum technology, a molding compound is applied to the silicon substrate 100 and the sealing cover 200; then, a grinding and thinning technique is used to thin the molding compound to a specified thickness, while exposing the sealing cover 200, forming a molding layer 420.

[0149] like Figure 26 As shown, the molding layer 420 is then etched using an etching process to obtain multiple vias 421 that expose the contact plug 140.

[0150] like Figure 27 As shown, a seed layer is made using PVD in each via 421; each via 421 of the molding compound 420 is filled using electroplating technology; and finally, excess metal is removed by CMP or wet etching to form multiple conductive pillars 410 that correspond one-to-one with multiple contact plugs 140. The conductive pillars 410 can be copper pillars.

[0151] The molding layer 420 surrounds the sealing cover 200, replacing the original sealing cover 200 structure. When the conductive pillar 410 is set, vias 421 can be formed in the molding layer 420, thus avoiding the formation of vias 421 on the sealing cover 200. When the sealing cover 200 is a silicon wafer, the formation of vias 421 on the silicon wafer will cause damage to the structural layer silicon wafer and metal traces due to over-etching. The depth of deep silicon etching is uncontrollable, and the thickness inside the silicon wafer fluctuates. Deep silicon etching must use over-etching. The structural wafer is easily etched without a protective layer 160.

[0152] This disclosure forms a molding compound 420 around the periphery of the sealing cover 200, and forms a conductive post 410 connecting the contact plug 140 in the molding compound 420. That is, the sealing cover 200 is made of molding compound material instead of silicon material, that is, TMV replaces TGV / TSV. This reduces the difficulty of the electroplating filling process, improves the thermal stress problem caused by CTE mismatch, such as material cracks and warping, and improves the yield of pressure sensor.

[0153] In step S600, a cavity is formed on the second surface of the silicon substrate, and the position of the cavity corresponds to the position of the varistor.

[0154] Specifically, such as Figure 29 As shown, a cavity 150 is formed on the second surface of the silicon substrate 100, and the positions of multiple varistors 130 correspond to the positions of the cavity 150. When the silicon substrate 100 is subjected to external pressure, the resistance of the varistor 130 changes, causing the bridge circuit to become unbalanced. By applying an excitation power supply to the bridge circuit, an output voltage proportional to the measured pressure can be obtained, thereby achieving the purpose of measuring pressure.

[0155] like Figure 28 As shown, before forming the cavity 150 on the second surface of the silicon substrate 100, a metal layer (UBM) 430 is formed at the end of the conductive pillar 410. Grooves can be formed at the end of the conductive pillar 410 using processes such as etching. Then, the metal layer 430 is formed on the grooves of the conductive pillar 410 using a deposition process. The metal layer 430 is formed conformally on the end of the conductive pillar 410, meaning that grooves are also formed on the surface of the metal layer 430. A seed layer is fabricated using PVD technology; photolithography is used to pattern the photoresist grooves; electroplating is used to thicken the seed layer; a resist remover is used for cleaning; the surface seed layer is removed using etching; and a nickel-palladium metal layer is formed on the copper layer using electroless plating. The UBM structure may include an adhesive layer, a barrier layer, a wetting layer, and an antioxidant layer covering the conductive pillar 410.

[0156] like Figure 30 As shown, contact terminals 440 can be formed on metal layer 430 through processes such as applying flux, placing solder balls, reflowing, and cleaning. Contact terminals 440 can be solder balls.

[0157] Alternatively, after forming a cavity on the second surface of the silicon substrate 100, a metal layer 430 may be formed at the end of the conductive pillar 410, but this disclosure does not limit this.

[0158] The method for manufacturing the pressure sensor disclosed herein can be used to manufacture the pressure sensor provided herein.

[0159] The embodiments of this disclosure also provide an air conditioning device, which includes the pressure sensor provided in the above embodiments. This air conditioning device can be, for example, a vehicle air conditioner, a household wall-mounted air conditioner, a floor-standing air conditioner, or a central air conditioning system.

[0160] The pressure sensor can be installed in the refrigerant pipes of the air conditioning unit. By sensing the pressure in the pipes, the operating power of the compressor and evaporator can be adjusted to achieve temperature control and energy saving. For further details on the beneficial effects of the air conditioning unit provided in this disclosure, please refer to the descriptions in the above-mentioned embodiments of the pressure sensor device and manufacturing method, which will not be repeated here.

[0161] Embodiments of this disclosure also provide a vehicle including the aforementioned air conditioning device. The vehicle may be, for example, an automobile, truck, train, high-speed train, or engineering vehicle. The beneficial effects of the vehicle provided by this disclosure are discussed in the embodiments of the pressure sensor device and manufacturing method described above, and will not be repeated here.

[0162] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0163] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A pressure sensor, characterized in that, include: A silicon substrate, the silicon substrate including opposite first and second surfaces, the second surface having a cavity formed therein; Multiple doped leads, wherein the multiple doped leads are located in the silicon substrate and close to the first surface; Multiple varistors are formed on the first surface of the silicon substrate, and the multiple varistors are correspondingly connected to multiple doped leads; the positions of the multiple varistors correspond to the cavity. Multiple contact plugs are formed on the first surface of the silicon substrate, and the multiple contact plugs are correspondingly connected to multiple doped leads; A sealing cover is fastened to the substrate to form a sealed cavity between the sealing cover and the substrate, a plurality of varistors are located in the sealed cavity, and at least a portion of the sealing cover is connected to the area between the varistor and the contact plug on the first surface; The doped lead connecting the varistor and the contact plug is located in the silicon substrate and is not directly exposed from the first surface of the silicon substrate; the bonding surface between the sealing cover and the silicon substrate is located on the first surface of the silicon substrate.

2. The pressure sensor according to claim 1, characterized in that, The pressure sensor also includes: A molding compound layer is located on the silicon substrate and the contact plug, and is located around the periphery of the sealing cover; A conductive post is located in a via of the molding compound, with one end connected to the contact plug and the other end exposed from the side of the molding compound away from the silicon substrate.

3. The pressure sensor according to claim 2, characterized in that, The pressure sensor also includes: A metal layer is formed at one end of the conductive pillar away from the silicon substrate; Contact terminals are formed on the side of the metal layer opposite to the silicon substrate.

4. A method for manufacturing a pressure sensor, characterized in that, include: A silicon substrate is provided, the silicon substrate comprising opposite first and second surfaces; Multiple doped leads are formed in the silicon substrate, close to the first surface and spaced apart. A plurality of varistors are formed on the first surface of the silicon substrate, and the plurality of varistors are connected to the plurality of doped leads accordingly; A plurality of contact plugs are formed on the first surface of the silicon substrate, and the plurality of contact plugs are connected to the plurality of doped leads accordingly; A sealing cover is formed on a first surface of the silicon substrate. The sealing cover is fastened to the substrate, forming a sealed cavity between the sealing cover and the substrate. A plurality of varistors are located in the sealed cavity, and at least a portion of the sealing cover is connected to the region between the varistors and the contact plugs on the first surface. The doped leads connecting the varistors and the contact plugs are located in the silicon substrate and are not directly exposed from the first surface of the silicon substrate. The bonding surface between the sealing cover and the silicon substrate is located on the first surface of the silicon substrate. A cavity is formed on the second surface of the silicon substrate, and the position of the cavity corresponds to the position of the varistor.

5. The manufacturing method according to claim 4, characterized in that, The manufacturing method further includes: Conductive pillars and a molding compound are formed on a first surface of the silicon substrate. The molding compound is located on the silicon substrate and is located around the periphery of the sealing cover. The conductive pillars are located in the molding compound, with one end connected to the contact plug and the other end exposed from the side of the molding compound away from the silicon substrate.

6. The manufacturing method according to claim 5, characterized in that, A sealing cover, conductive pillars, and a molding layer are formed on the first surface of the silicon substrate, including: A conductive post is formed on the contact plug; A sealing cover is provided, and the sealing cover is fastened onto the silicon substrate; A plastic encapsulation layer is formed on the silicon substrate and around the periphery of the sealing cover, encapsulating the conductive pillar, with the conductive pillar exposed from the side of the plastic encapsulation layer away from the silicon substrate.

7. The manufacturing method according to claim 6, characterized in that, A sealing shield is formed on a first surface of the silicon substrate, comprising: A sealing cover is provided, the sealing cover including a sealing part and a clamping part; The sealing cover is fastened onto the silicon substrate, and the sealing part forms the sealed cavity between the sealing part and the silicon substrate. The clamping part is located on the side of the sealing part away from the silicon substrate. The sealing cover is thinned to remove the clamping portion.

8. The manufacturing method according to claim 7, characterized in that, Provide a sealing cover, including: Provide glass substrates; Laser-induced technology is used to modify a predetermined area of ​​the glass substrate; then, the glass sheet is etched with an etching solution to obtain a first recess in the middle area of ​​the glass substrate and a second recess in the edge area. The portion of the glass substrate that forms the first recess is the sealing portion, and the portion that forms the second recess is the clamping portion.

9. The manufacturing method according to claim 5, characterized in that, A sealing cover, conductive pillars, and a molding layer are formed on the first surface of the silicon substrate, including: A sealing cover is provided, and the sealing cover is fastened onto the silicon substrate; A molding layer is formed on the silicon substrate and around the periphery of the sealing cover; A via is formed in the encapsulation layer, and a conductive post connecting the contact plug is formed in the via.

10. The manufacturing method according to claim 9, characterized in that, A sealing shield is formed on a first surface of the silicon substrate, comprising: Silicon wafers are supplied; A protrusion is formed on one side of the silicon wafer to connect with the silicon substrate; The silicon wafer is fastened onto the silicon substrate, and the protrusion is connected to the silicon substrate; Remove the portion of the silicon wafer near the periphery of the protrusion.

11. The manufacturing method according to claim 7, characterized in that, Prior to providing the sealing cover, the manufacturing method further includes: forming a protective layer at least on the contact plug; After attaching the sealing cover to the silicon substrate, the manufacturing method further includes removing the protective layer.

12. The manufacturing method according to claim 4, characterized in that, Before forming a plurality of doped leads spaced apart from the first surface in the silicon substrate, the manufacturing method further includes: forming a first positioning mark on the silicon substrate; Forming a sealing cover on a first surface of the silicon substrate includes: providing a sealing cover, on which a second positioning mark is formed; and forming a snap-fit ​​positioning between the sealing cover and the silicon substrate by means of the first positioning mark and the second positioning mark.

13. The manufacturing method according to claim 5, characterized in that, The manufacturing method further includes: A metal layer is formed at the end of the conductive pillar that is away from the silicon substrate; A contact terminal is formed on the side of the metal layer opposite to the silicon substrate.

14. An air conditioning device, characterized in that, Includes the pressure sensor described in any one of claims 1 to 3.

15. A vehicle, characterized in that, Includes the air conditioning device as described in claim 14.

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