Display panel, mother board thereof and preparation method of display panel

Abstract

The application discloses a display panel and a mother board thereof, and a preparation method of the display panel. The mother board of the display panel comprises a plurality of panel areas and a non-panel area, each panel area has a display panel, and the display panel in the non-display area comprises: an array substrate comprising a first substrate and a common electrode trace and a test trace which are arranged at one side of the first substrate, both of which comprise a first metal layer, a cover layer, a first transparent conductive layer and a first alignment film; a counter substrate comprising a second substrate and a second transparent conductive layer and a second alignment film arranged at one side of the second substrate; a plurality of first conductive balls arranged between the common electrode trace and the counter substrate, and a plurality of second conductive balls arranged between the test trace and the counter substrate; and the mother board further comprises: a first test pad electrically connected with the test trace; and a second test pad spaced from the first test pad and electrically connected with each common electrode trace through a common electrode connection trace. Through the above arrangement, the problem of poor conduction of the conductive balls can be detected in advance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel, a mother board thereof, and a preparation method of the display panel. BACKGROUND

[0002] Due to the small size (usually 1.8 inches, 2.0 inches, 2.4 inches, 2.8 inches, etc.), the functional machine is usually suitable for small generation production lines, such as 4.5 generation lines and 5.5 generation lines. With the continuous downturn of the panel industry, the profit of the small generation production line is low. In order to pursue profit, many panel enterprises gradually closed the small generation production line, resulting in that the production of the functional machine needs to be carried out on a large generation production line, such as 8.6 generation line, which can design 1000-2000pcs of small pieces. Since the large generation is usually used to produce large size products, for example, 32 inches, 55 inches, 65 inches, etc., in order not to affect the normal production of large size products and effectively utilize the edge material position, the functional machine needs to be designed at the edge position of the large panel, so as to meet the demand of large size products on the one hand, and produce the functional machine to make up for the demand caused by the closure of the small generation line on the market, which is a "win-win" design.

[0003] Since the functional machine belongs to a narrow frame product, the border is small, and the PI of the narrow frame product or the frameless product on the market can effectively control the coating precision of the PI, and the PI does not spread to the seal coating area. However, for the companies using PI Inject equipment, considering that the cost of equipment modification is high and not realistic, and if a Coater equipment is purchased, the cost is high and a series of additional expenditures are needed, so for the use of PI Inject equipment in narrow frame products or frameless products, how to reduce the impact of PI & VCOM Transfer pad partial overlap or full overlap caused by PI precision problem becomes an important issue. The product coated by PI Inject equipment, since the PI alignment film is a liquid with a certain precision range and the PI liquid has a certain hardness after solidification and is not conductive, the Au ball (Au in Seal or Au dot) at the VCOM Transfer pad is covered by TFT-PI & CF-PI, which causes the Au to not break TFT-PI & CF-PI, resulting in poor conduction and a series of functional problems, which seriously affect the product quality. After the functional machine cell is output, it is sent to the module factory for cutting into small pieces, cleaning, drying, Bonding IC, BD FPC, POL, preliminary lighting test, defoaming, assembling backlight module, secondary lighting test and a series of steps. The flicker of the functional machine can be observed in the preliminary lighting test and the secondary lighting test, especially when the cutting section position of the functional machine is touched by hand, the flicker will be more serious, so it can be determined that the functional machine has Au conduction problem.

[0004] In the prior art, after the functional machine cell is produced, the problem of gold ball conduction failure of the functional machine cannot be detected in advance before the steps of cutting into small pieces, cleaning, drying, bonding IC, BDFPC, pasting POL, preliminary lighting test, defoaming, assembling the backlight module, secondary lighting test, etc. SUMMARY

[0005] The present application mainly provides a display panel and a mother board thereof, and a preparation method of the display panel, to solve the problem that the gold ball conduction failure of the functional machine cannot be detected in advance before the step of cutting the functional machine cell into small pieces in the prior art.

[0006] To solve the above technical problems, one technical solution adopted by the present application is to provide a mother board of a display panel, comprising a plurality of panel areas and a non-panel area, each of the panel areas having a display panel; each of the display panels comprises a display area and a non-display area; and each of the display panels in the non-display area portion comprises:

[0007] An array substrate comprising a first substrate, a common electrode trace and a test trace which are insulatively arranged on one side of the first substrate, the common electrode trace and the test trace each comprising a first metal layer, a covering layer, a first transparent conductive layer and a first alignment film which are sequentially stacked, the covering layer covering the first metal layer and having a through hole, the first transparent conductive layer covering the covering layer and being electrically connected with the first metal layer through the through hole, and the first alignment film covering the first transparent conductive layer;

[0008] A counter substrate which is oppositely arranged with the array substrate and comprises a second substrate and a second transparent conductive layer and a second alignment film which are sequentially stacked on one side of the second substrate close to the array substrate;

[0009] A plurality of first conductive balls arranged between the common electrode trace and the counter substrate for electrically connecting the common electrode trace and the second transparent conductive layer;

[0010] A plurality of second conductive balls arranged between the test trace and the counter substrate for electrically connecting the test trace and the second transparent conductive layer;

[0011] Wherein, the first substrate further extends to the non-panel area; and the mother board of the display panel further comprises:

[0012] A first test pad arranged in the non-panel area of the first substrate and electrically connected with the test trace;

[0013] The common electrode connection wire is arranged in the non-panel area of the first substrate and is electrically connected with the common electrode wire of each display panel.

[0014] The second test pad is arranged in the non-panel area of the first substrate, is arranged apart from the first test pad, and is electrically connected with the common electrode connection wire.

[0015] In some embodiments, the first substrate does not cover the first test pad and the second test pad.

[0016] In some embodiments, the first test pad comprises a first metal layer, a covering layer and a first transparent conductive layer arranged in sequence, the covering layer covers the first metal layer and has a through hole, the first transparent conductive layer covers the covering layer and is electrically connected with the first metal layer through the through hole, and the first transparent conductive layer of the first test pad is directly electrically connected with the first transparent conductive layer of the test wire; or

[0017] The first test pad comprises a first metal layer, and the first metal layer of the first test pad is directly electrically connected with the first metal layer of the test wire; or

[0018] The first test pad comprises a first metal layer, and the first metal layer of the first test pad is directly electrically connected with the first transparent conductive layer of the test wire; or

[0019] The first test pad comprises a first transparent conductive layer, and the first transparent conductive layer of the first test pad is directly electrically connected with the first transparent conductive layer of the test wire.

[0020] In some embodiments, the common electrode wire is arranged around the display area, and the test wire is arranged apart from the common electrode wire on a side away from the display area.

[0021] In some embodiments, a plurality of test wires are arranged apart from each other corresponding to the same side edge of the display panel, and a plurality of first test pads are one-to-one electrically connected with a plurality of test wires.

[0022] In some embodiments, a plurality of common electrode wires corresponding to the same side edge of the display panel have a plurality of gaps arranged apart on a side close to the side edge of the display panel, a plurality of test wires are arranged one-to-one in the plurality of gaps, and are all arranged apart from the common electrode wire in insulation.

[0023] To solve the above technical problems, another technical solution adopted by the present application is to provide a display panel comprising a display area and a non-display area, and the display panel located in the non-display area part comprises:

[0024] An array substrate includes a first substrate, a common electrode trace and a test trace which are spaced apart from each other and disposed on one side of the first substrate; the common electrode trace and the test trace each include a first metal layer, a cover layer, a first transparent conductive layer and a first alignment film which are sequentially stacked; the cover layer covers the first metal layer and has a through hole; the first transparent conductive layer covers the cover layer and is electrically connected with the first metal layer through the through hole; and the first alignment film covers the first transparent conductive layer.

[0025] An opposite substrate spaced apart from the array substrate includes a second substrate and a second transparent conductive layer and a second alignment film which are sequentially stacked on a side of the second substrate close to the array substrate.

[0026] A plurality of first conductive balls are disposed between the common electrode trace and the opposite substrate; the first conductive balls are used to pierce the first alignment film of the common electrode trace and the second alignment film to electrically connect the first transparent conductive layer of the common electrode trace and the second transparent conductive layer.

[0027] A plurality of second conductive balls are disposed between the test trace and the opposite substrate; the second conductive balls are used to pierce the first alignment film of the test trace and the second alignment film to electrically connect the first transparent conductive layer of the test trace and the second transparent conductive layer.

[0028] In some embodiments, the common electrode trace is disposed around the display area, and the test trace is spaced apart from the common electrode trace on a side away from the display area.

[0029] The display panel includes the test trace, and a plurality of the test traces are spaced apart from each other corresponding to one side of the display panel; a plurality of the first test pads are electrically connected with a plurality of the test traces one by one.

[0030] A plurality of the common electrode traces corresponding to one side of the display panel have a plurality of spaced-apart notches on a side close to the side of the display panel, a plurality of the test traces are disposed in the plurality of notches one by one, and are spaced apart from the common electrode traces.

[0031] To solve the above technical problems, another technical solution adopted by the present application is to provide a display panel manufacturing method, including:

[0032] A display panel mother board is provided; the display panel mother board is any one of the display panel mother boards described above.

[0033] The detection electrode of the detection device is electrically connected to the first test pad and the second test pad respectively to detect whether the array substrate and the counter substrate of the display panel are conductive.

[0034] The mother board of the display panel is cut to obtain a plurality of display panels.

[0035] In some embodiments, the cutting of the mother board of the display panel to obtain a plurality of display panels comprises:

[0036] The non-panel area of the mother board of the display panel is cut to obtain a plurality of display panels; or,

[0037] The non-panel area and the test trace of the mother board of the display panel are cut to obtain a plurality of display panels.

[0038] The beneficial effects of the present application are: different from the prior art, the present application discloses a display panel, a mother board thereof and a preparation method of the display panel. The mother board of the display panel comprises a plurality of panel areas and a non-panel area, each panel area has one display panel, each display panel comprises a display area and a non-display area, and each non-display area part of the display panel comprises: an array substrate comprising a first substrate and a common electrode trace and a test trace which are insulated from each other and arranged on one side of the first substrate, the common electrode trace and the test trace each comprise a first metal layer, a cover layer, a first transparent conductive layer and a first alignment film which are sequentially stacked, the cover layer covers the first metal layer and has a through hole, the first transparent conductive layer covers the cover layer and is electrically connected to the first metal layer through the through hole, and the first alignment film covers the first transparent conductive layer; a counter substrate which is arranged in a spaced-apart manner opposite to the array substrate and comprises a second substrate and a second transparent conductive layer and a second alignment film which are sequentially stacked on one side of the second substrate close to the array substrate; a plurality of first conductive balls arranged between the common electrode trace and the counter substrate for electrically connecting the common electrode trace and the second transparent conductive layer; a plurality of second conductive balls arranged between the test trace and the counter substrate for electrically connecting the test trace and the second transparent conductive layer; wherein the first substrate further extends to the non-panel area, and the mother board of the display panel further comprises: a first test pad arranged in the non-panel area of the first substrate and electrically connected to the test trace; a common electrode connection trace arranged in the non-panel area of the first substrate and electrically connected to the common electrode trace of each display panel; and a second test pad arranged in the non-panel area of the first substrate and arranged in a spaced-apart manner with the first test pad and electrically connected to the common electrode connection trace. Through the above arrangement, it can be detected in advance whether the display panel has the problem of poor conduction of the conductive balls before the mother board of the display panel is cut, thereby improving the product detection yield. BRIEF DESCRIPTION OF DRAWINGS

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0040] Figure 1 This is a schematic diagram of the structure of the motherboard of the display panel provided in the first embodiment of this application;

[0041] Figure 2 yes Figure 1 A partially enlarged schematic diagram of area A of the motherboard of the provided display panel;

[0042] Figure 3 yes Figure 2 A partially enlarged schematic diagram of area B of the motherboard of the provided display panel;

[0043] Figure 4 yes Figure 3 A cross-sectional schematic diagram of one embodiment of the motherboard of the provided display panel along the CC line;

[0044] Figure 5 yes Figure 3 A cross-sectional schematic diagram of another embodiment of the motherboard of the provided display panel along the CC line;

[0045] Figure 6 yes Figure 3 A cross-sectional schematic diagram of the motherboard of the provided display panel along the CC line in another embodiment;

[0046] Figure 7 yes Figure 3 A cross-sectional schematic diagram of another embodiment of the motherboard of the provided display panel along the CC line;

[0047] Figure 8 This is a schematic diagram of the structure of an embodiment of the display panel provided in the second embodiment of this application;

[0048] Figure 9 This is a schematic diagram of another embodiment of the display panel provided in the second embodiment of this application;

[0049] Figure 10 This is a schematic flowchart of the method for preparing a display panel according to the third embodiment of this application.

[0050] Icon labels:

[0051] The motherboard 400 of the display panel; the panel area 100; the non-panel area 200; the display panel 300; the display area 1; the non-display area 2; the array substrate 3; the first substrate 31; the common electrode wire 32; the test wire 33; the first metal layer 34; the cover layer 35; the gate insulating layer 351; the passivation layer 352; the first transparent conductive layer 36; the first alignment film 37; the via hole 38; the notch 39; the counter substrate 4; the second substrate 41; the second transparent conductive layer 42; the second alignment film 43; the black matrix 44; the first conductive ball 5; the second conductive ball 6; the first test pad 7; the common electrode connection wire 8; the second test pad 9; the detection device 500. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0053] The terms "first", "second", "third" in the embodiments of the present application are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise explicitly specified. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0054] In this document, the reference to "embodiments" means that the specific features, structures or properties described in connection with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily mean the same embodiment is referred to, nor does it mean independent or alternative embodiments that are not mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0055] Reference Figures 1 to 7 , Figure 1 is a structural schematic diagram of the motherboard of the display panel provided by the first embodiment of the present application, Figure 2 is Figure 1 is a partial enlarged schematic diagram of the area A of the motherboard of the display panel provided by the first embodiment of the present application,Figure 3 is Figure 2 A partial enlarged schematic view of the area B of the mother board of the display panel provided by the present application, Figure 4 is Figure 3 A cross-sectional schematic view of an embodiment of the mother board of the display panel provided by the present application along the line C-C, Figure 5 is Figure 3 A cross-sectional schematic view of another embodiment of the mother board of the display panel provided by the present application along the line C-C, Figure 6 is Figure 3 A cross-sectional schematic view of still another embodiment of the mother board of the display panel provided by the present application along the line C-C, Figure 7 is Figure 3 A cross-sectional schematic view of yet another embodiment of the mother board of the display panel provided by the present application along the line C-C.

[0056] Referring to Figure 1 and Figure 2 , the present application provides a mother board 400 of a display panel, which comprises a plurality of panel areas 100 and non-panel areas 200, each of the panel areas 100 has one display panel 300, and each of the display panels 300 comprises a display area 1 and a non-display area 2.

[0057] Referring to Figures 3 to 7 , each of the display panels 300 in the non-display area 2 part comprises an array substrate 3, a counter substrate 4, a plurality of first conductive balls 5 and a plurality of second conductive balls 6.

[0058] The array substrate 3 comprises a first substrate 31 and a common electrode trace 32 and a test trace 33 arranged on one side of the first substrate 31, the common electrode trace 32 and the test trace 33 are arranged on the same side of the first substrate 31 in an insulated manner, and specifically, the common electrode trace 32 and the test trace 33 are arranged on the same surface of the first substrate 31 in an insulated manner.

[0059] Specifically, the common electrode trace 32 and the test trace 33 each comprise a first metal layer 34, a covering layer 35, a first transparent conductive layer 36 and a first alignment film 37 arranged in sequence, wherein the covering layer 35 covers the first metal layer 34, the covering layer 35 has a through hole 38, the first transparent conductive layer 36 covers the covering layer 35 and is electrically connected with the first metal layer 34 through the through hole 38, and the first alignment film 37 covers the first transparent conductive layer 36.

[0060] As Figures 3 to 7In some embodiments, the cover layer 35 includes a gate insulating layer 351 and a passivation layer 352 which are sequentially arranged, the gate insulating layer 351 is arranged on the side of the first metal layer 34 away from the first substrate 31 and covers the first metal layer 34, and the passivation layer 352 is arranged on the side of the gate insulating layer 351 away from the first substrate 31 and covers the gate insulating layer 351. The through hole 38 penetrates the gate insulating layer 351 and the passivation layer 352, so that the first metal layer 34 is partially exposed. The materials and thicknesses of the gate insulating layer 351 and the passivation layer 352 are not limited, for example, the gate insulating layer 351 is a SiO2insulating layer, and the passivation layer 352 is a PV layer.

[0061] The first transparent conductive layer 36 is arranged on the side of the cover layer 35 away from the first substrate 31, covers the passivation layer 352, and is electrically connected to the first metal layer 34 through the through hole 38. The first transparent conductive layer 36 can be a seamless continuous structure or have an open continuous structure. Specifically, the first transparent conductive layer 36 is an indium tin oxide (ITO) layer. The first alignment film 37 is arranged on the side of the first transparent conductive layer 36 away from the first substrate 31 and covers the first transparent conductive layer 36. Specifically, the first alignment film 37 is a polyimide (PI) film.

[0062] The counter substrate 4 is arranged opposite to and spaced apart from the array substrate 3. Specifically, the counter substrate 4 includes a second substrate 41, a second transparent conductive layer 42, and a second alignment film 43 which are sequentially arranged on the side of the second substrate 41 close to the array substrate 3. In an embodiment, the counter substrate 4 further includes a black matrix 44 which is arranged on the side of the second transparent conductive layer 42 close to the first substrate 31. Specifically, the black matrix 44 is arranged on the surface of the second substrate 41 close to the array substrate 3 and covers the second substrate 41, the second transparent conductive layer 42 is arranged on the surface of the black matrix 44 away from the second substrate 41 and covers the black matrix 44, and the second alignment film 43 covers the second transparent conductive layer 42. The material and arrangement of the second transparent conductive layer 42 can be the same as those of the first transparent conductive layer 36, and the material and arrangement of the second alignment film 43 can be the same as those of the first alignment film 37, which will not be described herein again.

[0063] A plurality of first conductive balls 5 are arranged between the common electrode trace 32 of the array substrate 3 and the counter substrate 4, for electrically connecting the common electrode trace 32 and the second transparent conductive layer 42. Specifically, the first conductive balls 5 are used to pierce the first alignment film 37 of the common electrode trace 32 and the second alignment film 43 of the counter substrate 4, so as to connect the first transparent conductive layer 36 of the common electrode trace 32 and the second transparent conductive layer 42 of the counter substrate 4. The first conductive balls 5 can be conductive gold balls or silver balls, or other conductive materials.

[0064] A plurality of second conductive balls 6 are arranged between the test trace 33 of the array substrate 3 and the counter substrate 4, and are used to electrically connect the test trace 33 and the second transparent conductive layer 42. Specifically, the second conductive ball 6 is used to pierce the first alignment film 37 of the test trace 33 and the second alignment film 43 of the counter substrate 4, so as to connect the first transparent conductive layer 36 of the test trace 33 and the second transparent conductive layer 42 of the counter substrate 4. The second conductive ball 6 can be a conductive gold ball or a silver ball, or other conductive materials. The structure of the first conductive ball 5 is the same as that of the second conductive ball 6, so as to improve the consistency and accuracy of the measurement results.

[0065] As shown in Figures 3 to 7 , in the embodiment, the first substrate 31 of the array substrate 3 further extends into the non-panel area 200 of the mother board 400 of the display panel, as shown in Figure 1 and Figure 2 , the mother board 400 of the display panel further comprises a first test pad 7, a common electrode connection trace 8 and a second test pad 9.

[0066] Specifically, as shown in Figure 1 , the first test pad 7 is arranged in the non-panel area 200 of the first substrate 31 and is electrically connected with the test trace 33. The common electrode connection trace 8 is arranged in the non-panel area 200 of the first substrate 31 and is electrically connected with the common electrode trace 32 of each display panel 300, that is, the common electrode traces 32 of the plurality of display panels 300 of the mother board 400 of the display panel are electrically connected with the common electrode connection trace 8. The second test pad 9 is arranged in the non-panel area 200 of the first substrate 31, the second test pad 9 is arranged spaced apart from the first test pad 7 and is electrically connected with the common electrode connection trace 8. The first test pad 7 and the second test pad 9 are respectively electrically connected with the two detection electrodes of the detection device 500 one by one, so as to test whether the first conductive ball 5 and the second conductive ball 6 are connected between the array substrate 3 and the corresponding counter substrate 4.

[0067] Since the first test pad 7 and the second test pad 9 are arranged in the non-panel area 200 of the mother board 400 of the display panel, they do not affect the size of the display panel 300, so the size of the first test pad 7 and the second test pad 9 can be set to a larger size, which is more conducive to electrical connection with the detection electrodes of the detection device 500, without the need for manual operation, facilitating online detection, improving detection efficiency and convenience, and further improving the accuracy of the detection results. Moreover, the common electrode traces 32 of the plurality of display panels 300 are electrically connected to the same second test pad 9 through the same common electrode connection trace 8, which can be batch detected without consuming a large amount of manpower and material resources.

[0068] In one embodiment, the detection device 500 is a multimeter, which can determine whether the first conductive ball 5 and the second conductive ball 6 pass through the array substrate 3 and the corresponding counter substrate 4 by measuring the resistance value. Specifically, the multimeter is adjusted to the resistance value measuring position, and the two detection electrodes of the multimeter are electrically connected to the first test pad 7 and the second test pad 9, respectively, to detect the resistance value. If the resistance value detected by the multimeter is very large, greater than or equal to a preset threshold value, for example, the resistance value detected by the multimeter is in the order of MΩ, or the multimeter cannot display the resistance value, it indicates that the first test pad 7 and the second test pad 9 are not connected, that is, the first conductive ball 5 and the second conductive ball 6 do not pass through the array substrate 3 and the corresponding counter substrate 4, that is, the first conductive ball 5 and the second conductive ball 6 do not pierce the first transparent conductive layer 36 and the second transparent conductive layer 42, and there is a problem of poor conduction of the gold ball. If the resistance value detected by the multimeter is very small, for example, less than the preset threshold value, it indicates that the first test pad 7 and the second test pad 9 are connected, that is, the first conductive ball 5 and the second conductive ball 6 pass through the array substrate 3 and the corresponding counter substrate 4, that is, the first conductive ball 5 and the second conductive ball 6 pierce the first transparent conductive layer 36 and the second transparent conductive layer 42, and there is no problem of poor conduction of the gold ball.

[0069] In other embodiments, the detection device 500 can also be configured in other structures, or can also determine whether the first conductive ball 5 and the second conductive ball 6 pass through the array substrate 3 and the corresponding counter substrate 4 by detecting other parameters, such as voltage.

[0070] In this application, by configuring the mother board 400 of the display panel in the above structure, the problem of poor conduction of the gold ball can be quickly detected in advance before the mother board 400 of the display panel is cut into a plurality of display panels 300, that is, before the steps of cutting into small pieces, cleaning, drying, Bonding IC, BDFPC, POL, preliminary lighting test, defoaming, assembling backlight module, secondary lighting test, etc. are not performed. The detection method is simple, convenient and efficient, and can realize direct online detection, which is beneficial to improve the product detection yield and avoid the operation in the later stage, as well as the delivery of the functional machine with poor conduction of the gold ball to the customer or subsequent process, thereby avoiding the loss of the customer end.

[0071] Further, in one embodiment, as shown in FIG. 8, the non-panel area 200 of the mother board 400 of the display panel is also provided with other test lines or signal lines. Figure 1 Figure 1 ​As shown, the non-panel area 200 is also provided with signal traces such as switch control line (SW), odd row data line (D-ODD), odd row scan line (G-ODD), even row data line (D-EVEN), and even row scan line (G-EVEN). Each display panel 300 in the panel area 100 is electrically connected to each signal trace, and each signal trace is electrically connected to a signal input pad. The signal input pads are located in the non-panel area 200 and are spaced apart from the first test pad 7 and the second test pad 9 to facilitate signal input.

[0072] In one specific embodiment, the substrate 4 does not cover the first test pad 7 and the second test pad 9 located in the non-panel area 200. For example, the substrate 4 may only be disposed in the panel area 100, so that the first test pad 7 and the second test pad 9 are exposed, making it easier to make contact and electrical connection with the detection electrodes of the detection device 500 for detection. In other embodiments, the substrate 4 may also extend into the non-panel area 200, but still not cover the first test pad 7 and the second test pad 9.

[0073] like Figures 1 to 3 As shown, in some embodiments, the common electrode trace 32 of the display panel 300 is arranged around the display area 1, and the test traces 33 are spaced apart on the side of the common electrode trace 32 away from the display area 1. In one specific embodiment, as... Figure 1 As shown, the test trace 33 and the common electrode connection trace 8 are located on opposite sides of the display area 1, and one end of the common electrode trace 32 extends to be electrically connected to the common electrode connection trace 8.

[0074] like Figures 1 to 3 As shown, in some embodiments, each display panel 300 has a plurality of test traces 33 in its non-display area 2, and a plurality of first test pads 7 are also provided in the non-panel area 200 corresponding to the plurality of test traces 33. The plurality of test traces 33 are spaced apart along the same side of the display panel 300, and the plurality of first test pads 7 are electrically connected to the plurality of test traces 33 in a one-to-one correspondence. For example, each display panel 300 has three test traces 33 in its non-display area 2, and a plurality of first test pads 7 are also provided in the non-panel area 200 corresponding to the three test traces 33. The three test traces 33 are insulated along a side of the display panel 300 away from the common electrode connection trace 8, and the three first test pads 7 are electrically connected to the three test traces 33 in a one-to-one correspondence. When using the detection device 500 to detect the conduction state of the first conductive ball 5 and the second conductive ball 6 between the array substrate 3 and the counter substrate 4, one detection electrode of the detection device 500 can be electrically connected to the second test pad 9, and the other detection electrode can be electrically connected to the three first test pads 7 in sequence to perform three detections, thereby further improving the detection accuracy and avoiding measurement errors or misjudgments.

[0075] In other embodiments, only one first test pad 7 may be provided, and the two detection electrodes of the detection device 500 may be directly electrically connected to the first test pad 7 and the second test pad 9 respectively for detection. The number of test traces 33 and the number of first test pads 7 may also be set to two, four, or any other arbitrary number, which can be designed according to needs.

[0076] like Figure 3 As shown, in one specific embodiment, a portion of the common electrode traces 32 corresponding to the same side of the display panel 300 has multiple spaced notches 39 on the side closest to the display panel 300. Multiple test traces 33 are correspondingly disposed within the multiple notches 39, and are all spaced and insulated from the common electrode traces 32. Specifically, a portion of the common electrode traces 32 corresponding to the side of the display panel 300 away from the common electrode connection trace 8 has three spaced notches 39 on that side closest to the display panel 300. Three test traces 33 are correspondingly disposed within the three notches 39, and are all spaced and insulated from the common electrode traces 32.

[0077] In other embodiments, the portion of the common electrode trace 32 corresponding to the side of the display panel 300 away from the common electrode connection trace 8 may not have a notch 39, and the test traces 33 may be directly spaced on the side of the common electrode trace 32 away from the common electrode connection trace 8.

[0078] like Figure 4 As shown, in one embodiment, the first test pad 7 includes a first metal layer 34, a cover layer 35, and a first transparent conductive layer 36 stacked sequentially. The cover layer 35 covers the first metal layer 34 and has a through hole 38. The first transparent conductive layer 36 covers the cover layer 35 and is electrically connected to the first metal layer 34 through the through hole 38. The first transparent conductive layer 36 of the first test pad 7 is directly electrically connected to the first transparent conductive layer 36 of the test trace 33. For example, the first transparent conductive layer 36 of the test trace 33 extends into the non-panel area 200 and is connected to the first transparent conductive layer 36 of the first test pad 7 to form a single piece, so as to realize the electrical connection between the first test pad 7 and the test trace 33.

[0079] In this embodiment, when the two detection electrodes of the detection device 500 are electrically connected to the first test pad 7 and the second test pad 9 respectively, such as Figure 4As shown, the VCOM voltage of the common electrode trace 32 on one side of the array substrate 3 passes through the first metal layer 34 and the first transparent conductive layer 36 in sequence and is then transmitted to the first conductive ball 5. If the first conductive ball 5 punctures the first alignment film 37 and the second alignment film 43, the VCOM voltage will be transmitted to the second transparent conductive layer 42 of the opposing substrate 4. Since the second transparent conductive layer 42 is a whole-surface structure, the second transparent conductive layer 42 of the opposing substrate 4 transmits the VCOM voltage to the corresponding positions of the test trace 33 and the second conductive ball 6. If the second conductive ball 6 punctures the first alignment film 37 and the second alignment film 43, the second conductive ball 6 transmits the VCOM voltage to the first transparent conductive layer 36 of the test trace 33. Since the first transparent conductive layer 36 of the first test pad 7 is connected to the first transparent conductive layer 36 of the test trace 33, the VCOM voltage is transmitted to the first transparent conductive layer 36 of the first test pad 7, so that there is a VCOM voltage on the first test pad 7. That is, the first conductive ball 5 and the second conductive ball 6 conduct the first transparent conductive layer 36 and the second transparent conductive layer 42.

[0080] In this embodiment, the common electrode trace 32, test trace 33, and the first test pad 7 of the array substrate 3 have the same film structure and can be fabricated using the same process. This method is simple and efficient, requiring only one mask, thus avoiding an increase in the number of masks and saving on process time and cost. Furthermore, the identical structural design of the common electrode trace 32 and test trace 33 ensures consistent conductivity of the first conductive ball 5 and the second conductive ball 6 in the regions of the common electrode trace 32 and test trace 33. The identical structure of the first test pad 7 on the array substrate 3 also contributes to more stable and effective detection with higher accuracy.

[0081] like Figure 5 As shown, in another embodiment, the first test pad 7 may also consist only of a first metal layer 34. The first metal layer 34 of the first test pad 7 is directly electrically connected to the first metal layer 34 of the test trace 33. Specifically, the first metal layer 34 of the test trace 33 extends directly into the non-panel area 200 and communicates with the first metal layer 34 of the first test pad 7. That is, the first metal layer 34 of the test trace 33 and the first metal layer 34 of the first test pad 7 are connected as one piece, both disposed in the same layer, and can be formed using the same process to achieve electrical connection between the test trace 33 and the first test pad 7. In other embodiments, the first metal layer 34 of the first test pad 7 may also be formed separately, as long as it is electrically connected to the first metal layer 34 of the test trace 33.

[0082] like Figure 6As shown in the figure, in another embodiment, the first test pad 7 can also only include the first metal layer 34, the first metal layer 34 of the first test pad 7 is directly electrically connected with the first transparent conductive layer 36 of the test trace 33, specifically, the first transparent conductive layer 36 of the test trace 33 extends into the non-panel area 200 and communicates with the first transparent conductive layer 36 of the first test pad 7, that is, the first transparent conductive layer 36 of the test trace 33 and the first transparent conductive layer 36 of the first test pad 7 are laminated and in contact, the first transparent conductive layer 36 of the test trace 33 covers the first metal layer 34 of the first test pad 7 entirely or partially, so as to realize the electrical connection between the test trace 33 and the first test pad 7. The first metal layer 34 of the first test pad 7 and the first metal layer 34 of the test trace 33 can be arranged in the same layer and can be prepared by the same process, so as to save the process. In other embodiments, the first metal layer 34 of the first test pad 7 can also be prepared separately, as long as it is electrically connected with the first transparent conductive layer 36 of the test trace 33.

[0083] As shown in the figure, Figure 7 in another embodiment, the first test pad 7 can also only include the first transparent conductive layer 36, the first transparent conductive layer 36 of the first test pad 7 is directly electrically connected with the first transparent conductive layer 36 of the test trace 33, specifically, the first transparent conductive layer 36 of the test trace 33 directly extends into the non-panel area 200 and communicates with the first transparent conductive layer 36 of the first test pad 7, that is, the first transparent conductive layer 36 of the test trace 33 and the first transparent conductive layer 36 of the first test pad 7 are laminated and in contact, the first transparent conductive layer 36 of the test trace 33 covers the first metal layer 34 of the first test pad 7 entirely or partially, so as to realize the electrical connection between the test trace 33 and the first test pad 7. The first metal layer 34 of the first test pad 7 and the first metal layer 34 of the test trace 33 can be arranged in the same layer and can be prepared by the same process, so as to save the process. In other embodiments, the first metal layer 34 of the first test pad 7 can also be prepared separately, as long as it is electrically connected with the first transparent conductive layer 36 of the test trace 33.

[0084] As shown in the figure, Figure 8 and Figure 9 , Figure 8 is a structural schematic diagram of an embodiment of a display panel provided by the second embodiment of the present application, Figure 9 is a structural schematic diagram of another embodiment of a display panel provided by the second embodiment of the present application.

[0085] As shown in the figure, Figure 8 and Figure 9 , the present embodiment provides a display panel 300, which can be cut from the mother board 400 of the display panel provided by the first embodiment, and the specific structure of the display panel 300 is the same as that of the display panel 300 of the panel area 100 of the mother board 400 of the display panel described above, and will not be described in detail here.

[0086] Specifically, in the embodiment, the display panel 300 is formed by cutting off the part of the display panel's mother panel 400 in the non-panel area 200, i.e., the structure reserved after cutting off the common electrode connecting wire 8, the first test pad 7 and the second test pad 9 and other test lines or signal wires in the non-panel area 200 of the display panel's mother panel 400, and then cutting the plurality of panel areas 100 into single independent display panels 300.

[0087] As shown in FIG. 1, in an embodiment, the display panel 300 still includes the display area 1 and the non-display area 2, and the structures of the display area 1 and the non-display area 2 are the same as those in the display panel's mother panel 400. Figure 8

[0088] As shown in FIG. 1, in another embodiment, the display panel 300 can also be the structure reserved after cutting off the test wire 33 in the non-display area 2 of the display panel 300, i.e., the display panel 300 can not include the test wire 33. Figure 9 The design can be made according to the needs, which is not limited in the present application.

[0089] Referring to FIG. 2, the present application further provides a display panel's mother panel 400.

[0090] Figure 10 is a flowchart of a method for manufacturing a display panel provided by the third embodiment of the present application. Figure 10 Referring to FIG. 2, the present application further provides a display panel's mother panel 400.

[0091] Figure 10 Specifically, the method for manufacturing a display panel includes:

[0092] S1: providing a display panel's mother panel 400.

[0093] Specifically, first, a display panel's mother panel 400 is provided, which has the same structure as the display panel's mother panel 400 provided in the first embodiment, and the display panel's mother panel 400 can be prepared by using the existing process.

[0094] S2: electrically connecting the detection electrodes of the detection device 500 to the first test pad 7 and the second test pad 9, respectively, to detect whether the array substrate 3 and the counter substrate 4 of the display panel 300 are conductive.

[0095] ​​​Specifically, the detection can be a multimeter, which can determine whether the first conductive ball 5 and the second conductive ball 6 are in conduction with the array substrate 3 and the corresponding counter substrate 4 by measuring the resistance value. Specifically, the multimeter is adjusted to the resistance value measuring gear, and the two detection electrodes of the multimeter are electrically connected to the first test pad 7 and the second test pad 9, respectively, to detect the resistance value. If the resistance value detected by the multimeter is very large and greater than or equal to a preset threshold, for example, the resistance value detected by the multimeter is in the order of MΩ, or the multimeter cannot display the resistance value, it indicates that the first test pad 7 and the second test pad 9 are not in conduction, that is, the first conductive ball 5 and the second conductive ball 6 are not in conduction with the array substrate 3 and the corresponding counter substrate 4, that is, the first transparent conductive layer 36 and the second transparent conductive layer 42 are not pierced, and there is a problem of poor conduction of the gold ball. If the resistance value detected by the multimeter is very small and less than the preset threshold, for example, the detected resistance value is less than 1KΩ, it indicates that the first test pad 7 and the second test pad 9 are in conduction, that is, the first conductive ball 5 and the second conductive ball 6 are in conduction with the array substrate 3 and the corresponding counter substrate 4, that is, the first transparent conductive layer 36 and the second transparent conductive layer 42 are pierced, and there is no problem of poor conduction of the gold ball.

[0096] In other embodiments, the detection device 500 can also be provided in other structures, or other parameters such as voltage can also be detected to determine whether the first conductive ball 5 and the second conductive ball 6 are in conduction with the array substrate 3 and the corresponding counter substrate 4.

[0097] S3: cutting the mother substrate 400 of the display panel to obtain a plurality of display panels 300.

[0098] Specifically, according to the result detected by the detection device 500, the mother substrate 400 of the display panel whose array substrate 3 and counter substrate 4 have been in conduction is cut to obtain a plurality of independent display panels 300.

[0099] In an embodiment, the step of cutting the mother substrate 400 of the display panel to obtain a plurality of display panels 300 in step S3 comprises:

[0100] The non-panel area 200 of the mother substrate 400 of the display panel is cut to obtain a plurality of display panels 300.

[0101] Specifically, in the present embodiment, the non-panel area 200 of the mother substrate 400 of the display panel is cut, that is, the common electrode connection trace 8, the first test pad 7 and the second test pad 9 and other test lines or signal traces and the like of the mother substrate 400 of the display panel located in the non-panel area 200 are cut, and the part located in the panel area 100 is reserved, and then the plurality of panel areas 100 are cut into single independent display panels 300 to form the structure of the display panel 300 as shown in FIG. 8. Figure 8 ​

[0102] In another embodiment, the step of cutting the mother panel 400 of display panels 300 to obtain a plurality of display panels 300 in step S3 comprises:

[0103] cutting off the non-panel area 200 and the test trace 33 of the mother panel 400 of display panels to obtain a plurality of display panels 300.

[0104] Specifically, in the present embodiment, not only the non-panel area 200 of the mother panel 400 of display panels is cut off, i.e. the common electrode connecting trace 8, the first test pad 7 and the second test pad 9 and other test lines or signal traces of the mother panel 400 of display panels located in the non-panel area 200 are cut off, but also the test trace 33 of the non-display area 2 of the panel area 100 is cut off, and then the plurality of panel areas 100 are cut into single independent display panels 300 to form a display panel 300 as shown in Figure 9 The structure of the display panel 300 described above, i.e. in the present embodiment, the display panel 300 prepared and formed does not include the test trace 33.

[0105] When the array substrate 3 and the opposite substrate 4 of the display panel 300 are not conductive by the detection device 500 in step S2, i.e. the first conductive ball 5 and the second conductive ball 6 do not pierce the first transparent conductive layer 36 and the second transparent conductive layer 42, the mother panel 400 of display panels can be marked as defective products for subsequent detection and repair, and after detection and repair, steps S2 and S3 can be performed again to prepare and form display panels 300.

[0106] The above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A mother panel of display panels, comprising a plurality of panel regions and a non-panel region, each of the panel regions having a display panel; each of the display panels comprising a display region and a non-display region; characterized in that, Each of the display panel of the non-display area part comprises: An array substrate comprising a first substrate and a common electrode trace and a test trace which are spaced apart from each other and arranged on one side of the first substrate, the common electrode trace and the test trace each comprising a first metal layer, a cover layer, a first transparent conductive layer and a first alignment film which are sequentially stacked, the cover layer covering the first metal layer and having a through hole, the first transparent conductive layer covering the cover layer and electrically connected with the first metal layer through the through hole, and the first alignment film covering the first transparent conductive layer; A counter substrate spaced apart from the array substrate and comprising a second substrate and a second transparent conductive layer and a second alignment film which are sequentially stacked on one side of the second substrate close to the array substrate; A plurality of first conductive balls arranged between the common electrode trace and the counter substrate for electrically connecting the common electrode trace and the second transparent conductive layer; A plurality of second conductive balls arranged between the test trace and the counter substrate for electrically connecting the test trace and the second transparent conductive layer; The first substrate further extends to the non-panel area; and the display panel mother board further comprises: A first test pad arranged in the non-panel area of the first substrate and electrically connected with the test trace; A common electrode connection trace arranged in the non-panel area of the first substrate and electrically connected with the common electrode trace of each of the display panel; A second test pad arranged in the non-panel area of the first substrate and spaced apart from the first test pad and electrically connected with the common electrode connection trace; The counter substrate does not cover the first test pad and the second test pad.

2. The display panel mother board of claim 1, wherein The first test pad comprises a first metal layer, a cover layer and a first transparent conductive layer which are sequentially stacked, the cover layer covering the first metal layer and having a through hole, the first transparent conductive layer covering the cover layer and electrically connected with the first metal layer through the through hole, and the first transparent conductive layer of the first test pad is directly electrically connected with the first transparent conductive layer of the test trace; or The first test pad comprises a first metal layer, and the first metal layer of the first test pad is directly electrically connected with the first metal layer of the test trace; or The first test pad comprises a first metal layer, and the first metal layer of the first test pad is directly electrically connected with the first transparent conductive layer of the test trace; or The first test pad comprises a first transparent conductive layer, and the first transparent conductive layer of the first test pad is directly electrically connected with the first transparent conductive layer of the test trace.

3. The display panel mother board of claim 1, wherein The common electrode trace is arranged around the display area, and the test trace is spaced apart from the common electrode trace on a side away from the display area.

4. The display panel mother board of claim 3, wherein The test wires correspond to the same side of the display panel and are arranged at intervals.

5. The display panel mother substrate according to claim 4, wherein The common electrode wires corresponding to the same side of the display panel have a plurality of gaps arranged at intervals on the side close to the side of the display panel, and the test wires are arranged in the gaps one by one and are insulated from the common electrode wires.

6. A display panel comprising a display area and a non-display area, characterized in that, The display panel is cut from the display panel mother substrate of claim 1, and the display panel located in the non-display area comprises: The array substrate comprises a first substrate, common electrode wires and test wires arranged on one side of the first substrate and insulated from each other, and the common electrode wires and the test wires each comprise a first metal layer, a cover layer, a first transparent conductive layer and a first alignment film arranged in sequence, the cover layer covers the first metal layer and has a through hole, the first transparent conductive layer covers the cover layer and is electrically connected with the first metal layer through the through hole, and the first alignment film covers the first transparent conductive layer; The counter substrate is arranged at intervals opposite to the array substrate and comprises a second substrate and a second transparent conductive layer and a second alignment film arranged in sequence on the side of the second substrate close to the array substrate; A plurality of first conductive balls are arranged between the common electrode wires and the counter substrate, and the first conductive balls are used to pierce the first alignment film of the common electrode wires and the second alignment film to electrically connect the first transparent conductive layer of the common electrode wires and the second transparent conductive layer; A plurality of second conductive balls are arranged between the test wires and the counter substrate, and the second conductive balls are used to pierce the first alignment film of the test wires and the second alignment film to electrically connect the first transparent conductive layer of the test wires and the second transparent conductive layer.

7. The display panel of claim 6, wherein, The common electrode wires surround the display area, and the test wires are arranged at intervals on the side of the common electrode wires away from the display area; The display panel comprises a plurality of test wires, the test wires correspond to the same side of the display panel and are arranged at intervals, and the first test pads are electrically connected with the test wires one by one; The common electrode wires corresponding to the same side of the display panel have a plurality of gaps arranged at intervals on the side close to the side of the display panel, and the test wires are arranged in the gaps one by one and are insulated from the common electrode wires.

8. A method for manufacturing a display panel, characterized by, The display panel mother substrate is provided. The display panel mother substrate is provided. The detection electrodes of the detection device are electrically connected to the first test pads and the second test pads respectively to detect whether the array substrate and the counter substrate of the display panel are conductive; The display panel mother substrate is cut to obtain a plurality of display panels. The cutting of the display panel mother substrate to obtain a plurality of display panels comprises:

9. The method of manufacturing a display panel according to claim 8, wherein, ​ cutting off the non-panel area of the mother board of the display panel to obtain a plurality of display panels; or cutting off the non-panel area and the test trace of the mother board of the display panel to obtain a plurality of display panels.

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