Package Structure, Manufacturing Method and Application of Power Semiconductor Devices

Abstract

A packaging structure, method and application of a power semiconductor device, belonging to the field of semiconductor packaging; the packaging structure of the power semiconductor device includes: a chip, a cathode electrode arranged on the first side of the chip; and an anode electrode arranged on the second side opposite to the first side of the chip; at least one of the cathode electrode and the anode electrode uses a conductive metal composite material. The present invention realizes a significant reduction in the overall thermal resistance of the device by respectively reducing the bulk thermal resistance and the contact thermal resistance, improves the current rating of the device, and reduces the complexity of the packaging process.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and particularly relates to a packaging structure of a power device, a manufacturing method thereof and an application, especially a packaging structure of a high-power semiconductor device. Background Art

[0002] As a new type of power electronic device, the gate commutated thyristor (GCT) has been widely used in the fields of industrial variable frequency speed regulation, wind power grid connection, rail transit, etc. due to its advantages of large capacity, high reliability, low loss and low cost. In recent years, the rapid development of DC power grids has made high-voltage and large-capacity power semiconductor devices the core components of key equipment for DC backbone networks. As a power electronic device, the typical operating states of the gate commutated thyristor are the blocking state, the conducting state, and the turn-on process and turn-off process during the conversion between the two states. It can withstand high voltage in the forward direction, pass large current in the forward direction, and the gate controls the turn-on and turn-off of the thyristor. In power system applications, the gate commutated thyristor mainly serves as a fully controlled switching device, and the current-carrying capacity of a single device can reach up to 6000A - 8000A.

[0003] The traditional gate commutated thyristor case adopts the protection and electrode lead-out method of copper boss + molybdenum electrode plate. As Figure 1 shown, the traditional GCT component mainly consists of a semiconductor switch chip and a packaging case. Among them, the semiconductor chip 1, the cathode buffer layer 201, the anode buffer layer 202, the case cathode electrode 301; the case anode electrode 302 together constitute a five-layer vertical stacking structure of electrode - buffer layer - chip - buffer layer - electrode. Among them, 401 is the heat transfer path on the cathode side of the semiconductor chip; 402 is the heat transfer path on the anode side of the semiconductor chip. The packaging structures disclosed in Chinese Patent Publication No. CN1937243A (right holder: Zhuzhou CRRC Times Semiconductor Co., Ltd.) and Chinese Patent Publication No. CN1292150A (right holder: ABB Switzerland Ltd.) both adopt this form.

[0004] However, the above structure has at least the following problems:

[0005] (1) The thermal resistance of the copper boss and the molybdenum electrode itself and the contact thermal resistance of their contact cross-section are both relatively high, resulting in a large temperature rise of the device at steady state, which affects the reliability of the device; taking a 4500V device as an example, a copper boss thickness of 10mm and a molybdenum electrode plate thickness of 2.5mm are required, the thermal resistance is 4.3K / kW, and the temperature rise during steady-state operation is at least 30°C.

[0006] (2) The number of packaging layers is relatively large, and the complexity of the process operation is relatively high.

[0007] (3) The multi-layer stacking structure has strict requirements for the flatness and parallelism processing of each layer, increasing the processing difficulty of the packaging accessories. Summary of the Invention

[0008] In view of this, the main object of the present invention is to provide a packaging structure, manufacturing method and application of a power device, so as to at least partially solve the above technical problems.

[0009] To achieve the above object, as the first aspect of the present invention, a packaging structure of a power semiconductor device is proposed, including:

[0010] A chip;

[0011] A cathode electrode disposed on the first side of the chip; and

[0012] An anode electrode disposed on the second side of the chip opposite to the first side;

[0013] Wherein, at least one of the cathode electrode and the anode electrode is prepared by using a conductive metal composite material.

[0014] As the second aspect of the present invention, a manufacturing method of a packaging structure of a power semiconductor device is also proposed, including the following steps:

[0015] Connect one of the cathode electrode and the anode electrode to the first side of the chip by mechanical pressure or sintering;

[0016] Connect the other electrode of the cathode electrode and the anode electrode to the second side of the chip opposite to the first side by mechanical pressure or sintering;

[0017] Wherein, at least one of the cathode electrode and the anode electrode uses a conductive metal composite material, and at least one of the cathode electrode and the anode electrode is subjected to plating treatment or deposition treatment on the surface facing the chip before crimping.

[0018] As the third aspect of the present invention, a power device using the above packaging structure is also proposed, and the power device is an IGCT, IGBT, GTO or ordinary thyristor.

[0019] As the fourth aspect of the present invention, an electronic device is also proposed, and the electronic device uses the above power device as a control element and / or a current / voltage switching element.

[0020] Based on the above technical solutions, the packaging structure, manufacturing method and application of the power device of the present invention have at least one of the following beneficial effects compared with the prior art:

[0021] (1) Through the power semiconductor packaging structure provided by the present invention, the requirements for heat dissipation of high-power semiconductor devices, especially high-power semiconductor devices, can be met.

[0022] (2) The present invention simplifies the five-layer vertical stacked structure of electrode-buffer layer-chip-buffer layer-electrode in the traditional structure into a three-layer vertical stacked structure of electrode-chip-electrode. The number of contact interfaces is reduced from four layers to two layers, significantly reducing the contact thermal resistance. At the same time, the electrode material is changed to a conductive metal composite material with high thermal conductivity and low coefficient of thermal expansion, significantly reducing the bulk thermal resistance without changing the thermal stress and electrical conductivity. Finally, a significant reduction in the overall thermal resistance of the device is achieved, further improving the current rating of the device.

[0023] (3) The present invention uses a high thermal conductivity composite material, such as an electrode made of aluminum diamond / copper diamond, to connect with the chip to realize the electrode lead-out of the anode and cathode of the chip. Taking the cathode side as an example, the two-layer structure of the cathode molybdenum electrode and the cathode copper boss of the package shell in the traditional structure is reduced to one layer, reducing the complexity of the packaging process operation.

[0024] (4) The present invention uses a high thermal conductivity composite material, such as an electrode made of aluminum diamond / copper diamond, to connect with the chip to realize the electrode lead-out of the anode and cathode of the chip. By virtue of the advantage of the thermal conductivity of the material itself, the thermal resistance of the device can be reduced to 1 / 2.

[0025] (5) The present invention uses an electrode made of a high thermal conductivity composite material to connect with the chip through welding or sintering to achieve a gapless connection between the chip and the electrode, further reducing the thermal resistance of the device. Description of the Drawings

[0026] The methods and devices of the present invention will be further described below in conjunction with the drawings and embodiments:

[0027] Figure 1 is a schematic diagram of the packaging structure of a traditional power semiconductor device;

[0028] Figure 2 is a schematic diagram of the packaging structure of a power semiconductor device according to an embodiment of the present invention;

[0029] Figure 3 is a schematic diagram of the packaging structure of a power semiconductor device according to another embodiment of the present invention;

[0030] Figure 4 is a chip structure with a gate ring at the edge according to an embodiment of the present invention;

[0031] Figure 5 is a chip structure with a gate ring in the center according to an embodiment of the present invention;

[0032] Figure 6 is a schematic diagram of the surface state of a metal electrode according to an embodiment of the present invention;

[0033] Figure 7A 、 7BThey are the relationships between the diamond volume fraction and the thermal conductivity and thermal expansion coefficient in the copper diamond material, respectively;

[0034] Figure 8 It is a schematic diagram of the heat dissipation path of a traditional IGCT device;

[0035] Figure 9 It is the thermal resistance composition of a traditional IGCT device;

[0036] Figure 10 It is a schematic diagram of the heat dissipation path of a three - layer - structure IGCT device according to an embodiment of the present invention;

[0037] Figure 11 It is a thermal resistance simulation diagram of a three - layer - structure IGCT device according to an embodiment of the present invention.

[0038] Figure 12 It is a schematic diagram of the package with a transition metal ring added according to an embodiment of the present invention;

[0039] Figure 13 It is a schematic diagram of the package with a stepped structure according to an embodiment of the present invention;

[0040] Figure 14 It is Figure 13 A partial enlarged view of the stepped structure in

[0041] Figure 15 It is a schematic diagram of the package with different thermal expansion coefficients according to an embodiment of the present invention

[0042] In the above - mentioned drawings, the meanings of the reference numerals are as follows:

[0043] 1: Semiconductor chip;

[0044] 6: Metal flange

[0045] 7: Ceramic housing

[0046] 8: Transition metal ring

[0047] 201: Cathode buffer layer;

[0048] 202: Anode buffer layer;

[0049] 301: Shell cathode electrode;

[0050] 302: Shell anode electrode;

[0051] 401: Heat transfer path on the cathode side of the semiconductor chip;

[0052] 402: Heat transfer path on the anode side of the semiconductor chip;

[0053] 503, 504: Anode electrode;

[0054] 303, 304: Cathode electrodes.

[0055] 203, 204: Composite material buffer layers.

[0056] 101: Gate ring. Detailed implementation manners

[0057] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the following further elaborates on the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0058] In the present invention, the definitions of some abbreviations and key terms are as follows:

[0059] GCT: Abbreviation for Gate-Commutated Thyristor, gate-commutated thyristor;

[0060] IGCT: Abbreviation for Integrated Gate-Commutated Thyristor, integrated gate-commutated thyristor;

[0061] IGBT: Abbreviation for Insulated Gate Bipolar Transistor, insulated gate bipolar transistor;

[0062] GTO: Abbreviation for GateTurn-Off Thyristor, gate turn-off thyristor;

[0063] P-type semiconductor: Semiconductor doped with P-type (Positive, hole-type and positively charged) ions;

[0064] N-type semiconductor: Semiconductor doped with N-type (Negative, electron-type and negatively charged) ions;

[0065] PN junction: Abbreviation for PN junction, PN interface composed of P-type semiconductor and N-type semiconductor.

[0066] As Figure 2-5 shown, on the one hand, the present invention improves the heat dissipation capacity of the device by changing the material used and replacing the traditional copper boss and / or molybdenum electrode with a composite material; on the other hand, the copper boss and molybdenum electrode structures are made into one body, reducing the contact thermal resistance at the interface and reducing the number of components, thereby reducing the complexity of the packaging process; in addition, the contact interfaces between layers can be interconnected through processes such as nano-silver sintering and low-temperature bonding to eliminate the contact interfaces, further reducing the contact interfaces, and finally achieving a significant reduction in the overall thermal resistance of the device.

[0067] To achieve the above objectives, the present invention can adopt one or a combination of the following technical solutions:

[0068] As shown Figure 2 in the figure, the present invention provides a power semiconductor device packaging structure, which includes a chip 1; a cathode electrode 304 perpendicular to the axis of the chip 1 and disposed on the first surface of the chip 1, and an anode electrode 504 disposed on the second surface of the chip 1;

[0069] As a preferred embodiment, the cathode electrode 304 and the anode electrode 504 are connected to the chip 1 by mechanical pressure to lead out the electrodes of the chip;

[0070] As a preferred embodiment, the cathode electrode 304 and the anode electrode 504 are connected to a ceramic housing 7 through a metal flange 6 to form a sealed housing, protecting the chip 1 from being isolated from the environment such as water vapor, oxygen, and dust;

[0071] As a preferred embodiment, the anode electrode 304, the cathode electrode 504, and the buffer layer are all formed of a conductive metal composite material with high thermal conductivity and low coefficient of thermal expansion. Preferably, its thermal conductivity is greater than 400 W / (m·K), and the coefficient of thermal expansion is less than 10e-6 / K. As a preferred composite material, for example, aluminum diamond / copper diamond.

[0072] As shown Figure 3 in the figure, as another possible implementation manner, the present invention provides a high-power semiconductor device packaging structure, which includes a chip; an anode electrode 503 perpendicular to the axis of the chip 1 and disposed on the first surface of the chip 1, buffer layers 203 and 204 disposed on the second surface of the chip 1, and a cathode electrode 303 on the buffer layer;

[0073] As a preferred embodiment, the cathode electrode 303 and the anode electrode 503 are connected to the chip 1 by mechanical pressure to lead out the electrodes of the chip;

[0074] As a preferred embodiment, the cathode electrode 303 and the anode electrode 503 are connected to a ceramic housing 7 through a metal flange 6 to form a sealed housing, protecting the chip 1 from being isolated from the environment such as water vapor, oxygen, and dust.

[0075] In addition, without changing the original five-layer structure, simply by using a conductive metal composite material with high thermal conductivity and low coefficient of thermal expansion to replace the original material, and / or by realizing interconnection through processes such as nano-silver sintering and low-temperature bonding at the contact interfaces between layers to eliminate the contact interfaces, the contact interfaces can also be reduced, achieving the effect of significantly reducing the overall thermal resistance of the device.

[0076] Figure 4 、 5The chip structures with the gate ring at the edge and the gate ring at the center are respectively shown, where 101 is the gate ring.

[0077] As Figure 6 shown, as a preferred embodiment, for high-power IGCT devices, the flatness of the electrode surface is required to be < 10 μm, and the surface roughness Ra = 0.3 μm - 0.7 μm; due to the relatively high hardness and low machinability of the composite material, the flatness is generally > 20 μm.

[0078] Therefore, one method is to first perform plating treatment on the surface. As the preferred plating material, the plating metal can be selected as the Ni-Ag layer, and the plating thickness > 20 μm (where the Ni layer is the transition layer and the Ag layer is the machinable layer. At the same time, in order to ensure the bonding effect, the Ni layer is as thin as possible, preferably 2 μm - 5 μm), and then the flatness is reduced to < 10 μm by grinding, and at the same time, a lower surface roughness < Ra = 0.3 μm is obtained to ensure good contact between the electrode and the wafer surface.

[0079] Another method is to deposit nano-silver particles on the surface of the copper-diamond electrode through a nano-deposition process, pre-deposit nano-materials on the copper-diamond surface, simplify the sintering process, and reduce the contact thermal resistance. For example, nano-scale microparticles can be generated by bombarding the target with a laser, and the nano-particles are deposited layer by layer on the electrode surface to form a dense silver layer.

[0080] Whether it is surface silver plating or nano-silver particle deposition, a silver layer is attached to the electrode surface, which mainly has two functions: one is to utilize the relatively soft property of the silver layer to compensate for the originally poor roughness and flatness of the electrode surface in the crimping state and reduce the contact thermal resistance; the other is to utilize the weldable / sinterable property of the silver layer to realize the welding / sintering of the electrode and the chip and reduce the contact thermal resistance.

[0081] Selection of conductive metal composite materials:

[0082] As the conductive metal composite material, materials with a thermal conductivity greater than 400 W / (m·K) and a thermal expansion coefficient less than 8e-6 / K are preferably selected. Materials meeting the above requirements can be preferably aluminum-diamond, copper-diamond, molybdenum-copper alloy, tungsten-copper alloy, copper-graphene composite material, etc. For copper-diamond or aluminum-diamond, the thermal conductivity and thermal expansion coefficient of the material are closely related to the composition of diamond, copper or aluminum. For the application of the electrode of high-power IGCT devices, materials with as high a thermal conductivity and as low a thermal expansion coefficient as possible (close to Si, 2.49×10 -6 / °C) are required. Therefore, considering the interface effect, the volume fraction of diamond in the composition range of copper-diamond or aluminum-diamond materials is preferably 40% - 70%, the thermal conductivity range is 450 - 600 W / (m·K), and the thermal expansion coefficient range is 3.5 - 5.5×10-6 / °C.

[0083] Figure 7A and 7B respectively show the relationships between the diamond volume fraction and the thermal conductivity and the coefficient of thermal expansion in the copper diamond material.

[0084] On the other hand, as a preferred embodiment, in order to improve the reliability of the package, the package structure can also be improved from the following aspects:

[0085] (1) Adjust the coefficient of thermal expansion of the original package sealing flange, and add a transition metal ring (such as kovar alloy, etc.), so that the inner ring of the package sealing flange and the electrode have more similar coefficients of thermal expansion, reduce the thermal stress, and improve the welding reliability of the package.

[0086] (2) Adjust the distribution concentration of diamond particles inside the electrode material, so that the center of the electrode has a lower coefficient of thermal expansion and the outside of the electrode has a higher coefficient of thermal expansion, showing a gradient distribution, reduce the thermal stress between the electrode and the package sealing flange, and improve the welding reliability of the package.

[0087] (3) Make full use of the steps in the existing electrode structure to increase the interconnecting area between the copper diamond electrode and the package sealing flange, improve the welding strength, and the axial dimension of the overlapping step surface should not be less than 1.5 mm.

[0088] Hereinafter, through specific embodiments, various possible embodiments of the present invention are exemplified, but these embodiments do not constitute a limitation to the technical solution of the present invention.

[0089] Embodiment 1

[0090] As Figure 2 shown. The present invention provides a high-power semiconductor package structure, which significantly improves the heat dissipation capacity of the device and reduces the junction-to-case thermal resistance of the device and the complexity of the packaging process by changing the package structure and materials. In terms of structure, the traditional five-layer vertical stacking structure of electrode-buffer layer-chip-buffer layer-electrode is simplified to a three-layer vertical stacking structure of electrode-chip-electrode, and the number of contact interfaces is reduced from four layers to two layers, significantly reducing the contact thermal resistance. In terms of material selection, the electrode material is changed from traditional oxygen-free copper to a conductive metal composite material with high thermal conductivity and low coefficient of thermal expansion, such as aluminum diamond / copper diamond, with a thermal conductivity greater than 400 W / (m·K) and a coefficient of thermal expansion less than 10e-6 / K, significantly reducing the bulk thermal resistance without affecting the thermal stress and electrical conductivity. Since the overall junction-to-case thermal resistance of the device is composed of the sum of the bulk thermal resistance and the contact thermal resistance, this embodiment significantly reduces the overall thermal resistance of the device by reducing the bulk thermal resistance and the contact thermal resistance respectively, and further improves the current rating of the device.

[0091] In addition, the cathode electrode 304 and the anode electrode 504 are connected to the chip 1 by mechanical pressure to lead out the electrodes of the chip. Further, the cathode electrode 501 and the anode electrode 502 are connected to the ceramic housing 7 through the metal flange 6 to form a sealed housing, protecting the chip 1 from being isolated from the environment such as water vapor, oxygen, and dust.

[0092] Example 2

[0093] As Figure 3 shown, for a high-power semiconductor package structure with the gate ring located inside, due to the need to lead out the gate, a slot needs to be opened on one of the electrodes and a gate lead spoke is provided. This slot will affect the lead-out of the cathode comb of the chip above it. Therefore, the buffer layer on the lower side needs to be retained. Specifically, in terms of structure, the traditional five-layer vertical stacking structure of electrode-buffer layer-chip-buffer layer-electrode is simplified to a four-layer vertical stacking structure of electrode-chip-buffer layer-electrode. The number of contact interfaces is reduced from four to three, significantly reducing the contact thermal resistance. In terms of material selection, the electrode material and the buffer layer material are respectively changed from traditional oxygen-free copper and molybdenum sheet to a conductive metal composite material with high thermal conductivity and low coefficient of thermal expansion, such as aluminum diamond / copper diamond, with a thermal conductivity greater than 400 W / (m·K) and a coefficient of thermal expansion less than 10e-6 / K. On the basis of not affecting the thermal stress and electrical conductivity, the bulk thermal resistance is significantly reduced. Since the overall junction-to-case thermal resistance of the device is composed of the superposition of the bulk thermal resistance and the contact thermal resistance, this example realizes a significant reduction in the overall thermal resistance of the device by separately reducing the bulk thermal resistance and the contact thermal resistance, further improving the current rating of the device.

[0094] In addition, the cathode electrode 303 and the anode electrode 503 are connected to the chip 1 by mechanical pressure to lead out the electrodes of the chip. Further, the cathode electrode 501 and the anode electrode 502 are connected to the ceramic housing 7 through the metal flange 6 to form a sealed housing, protecting the chip 1 from being isolated from the environment such as water vapor, oxygen, and dust.

[0095] Example 3

[0096] On the basis of the traditional five-layer vertical stacking structure of electrode-buffer layer-chip-buffer layer-electrode, without changing the device package structure, only changing the material selection, the electrode material and the buffer layer material are respectively changed from traditional oxygen-free copper and molybdenum sheet to a conductive metal composite material with high thermal conductivity and low coefficient of thermal expansion, such as aluminum diamond / copper diamond. By significantly improving the thermal conductivity, the bulk thermal resistance is reduced, and finally a significant reduction in the overall thermal resistance of the device is achieved.

[0097] Example 4

[0098] Based on the five-layer vertical stacked structure of electrode-buffer layer-chip-buffer layer-electrode in the traditional solution, without changing the device packaging structure, only changing the material selection and packaging process, the electrode material and buffer layer material are respectively changed from traditional oxygen-free copper and molybdenum sheets to a conductive metal composite material with high thermal conductivity and low coefficient of thermal expansion, such as aluminum diamond / copper diamond, to reduce the bulk thermal resistance by significantly improving the thermal conductivity. The contact interfaces between layers are interconnected through processes such as nano-silver sintering and low-temperature bonding to eliminate the contact interface, further reducing the contact interface, and ultimately achieving a significant reduction in the overall thermal resistance of the device.

[0099] Example 5

[0100] Figure 12 For another preferred packaging structure, adjust the coefficient of thermal expansion of the original shell sealing flange. For example, by adding a transition metal ring 8 (such as kovar alloy, etc.), the inner ring of the shell sealing flange 6 has a more similar coefficient of thermal expansion to the electrode, thereby further reducing the thermal stress and improving the welding reliability of the shell. For example, when the electrode selects copper diamond, the coefficient of thermal expansion of the electrode is 5 - 7e-6 / K, while the coefficient of thermal expansion of the transition metal ring 8 is 7 - 10e-6 / K. The metal flange 6 can be selected as an oxygen-free copper flange, and its coefficient of thermal expansion is 17 - 20e-6 / K.

[0101] Example 6

[0102] Figure 13 For another preferred packaging structure, set the electrode structure as a stepped structure, thereby increasing the interconnect area between the copper diamond electrode and the shell sealing flange and improving the welding strength; more preferably, as Figure 14 shown in the enlarged view, it is preferred that the axial dimension d where the stepped surfaces coincide is not less than 1.5 mm.

[0103] Example 7

[0104] As Figure 15 shown, another preferred implementation is that the distribution concentration of diamond particles inside the electrode material can be adjusted so that the electrode has different coefficients of thermal expansion along the radial direction, such as the electrode center has a lower coefficient of thermal expansion and the electrode outer part has a higher coefficient of thermal expansion, showing a gradient distribution, thereby further reducing the thermal stress between the electrode and the shell sealing flange and improving the welding reliability of the shell. A preferred method is, for example, the coefficient of thermal expansion of the central part of the electrode is 5 - 7e-6 / K, and the edge is 7 - 10e-6 / K.

[0105] Simulation effect

[0106] 1. Thermal resistance optimization effect

[0107] The schematic diagram of the heat dissipation path of the traditional IGCT device is as Figure 8As shown, the heat generated by the chip reaches the radiator through the molybdenum-silicon contact surface, molybdenum sheet, copper-molybdenum contact surface, and copper sheet, with double-sided heat dissipation. The device thermal resistance components are as Figure 9 shown, including the chip body thermal resistance, molybdenum-silicon contact surface contact thermal resistance, molybdenum sheet body thermal resistance, copper-molybdenum contact surface contact thermal resistance, and copper sheet body thermal resistance. From Figure 9 it can be seen that the device contact thermal resistance accounts for a high proportion, and the copper sheet thermal resistance is also relatively large.

[0108] Figure 10 Figure shows the heat dissipation path of the optimized three-layer structure device, which reduces the device thermal resistance and improves the device current-carrying capacity from two aspects: eliminating the contact surface and increasing the material thermal conductivity to reduce the body thermal resistance.

[0109] Figure 11 Figure shows the thermal resistance composition of the optimized three-layer structure device. Taking the thermal conductivity of the high thermal conductivity material as 600 W / (m·K) as an example, through theoretical calculation and simulation analysis, the predicted thermal resistance of the three-layer structure is reduced by 48.44%, and the effect is significantly better than the existing technology.

[0110] 2. Electrical characteristic analysis

[0111] Calculate the influence of the high thermal conductivity material replacement scheme on the electrical conductivity of the device. Taking copper diamond as an example, the resistivity takes the upper limit of the usual range, and the overall replacement package structure resistance is calculated according to the device structure. The resistance calculation formula is shown in Equation (1), where ρ is the resistivity of the material, l is the thickness of the material, and s is the cross-sectional area of the material. Substitute the electrical conductivity of the material and the thickness and cross-sectional area of each layer structure into Equations (2) and (3) to obtain the resistance of each layer of the package structure.

[0112]

[0113] R pack1 = R CuK + R MoK + R MoA + R CuA (2)

[0114] R pack2 = R CuCk + R CuCA (3)

[0115] According to Equation (2), the package structure resistance of the original scheme is calculated to be 7×10 -8 Ω, and according to Equation (3), the package structure resistance after overall replacement is calculated to be 2.02×10 -7 Ω. The conduction voltage drops at a load current of 5 kA are 0.35 mV and 1.01 mV respectively, and the change amount compared with the chip voltage drop of 3 V is less than one-thousandth, which can be ignored. It shows that replacing the high thermal conductivity material will not significantly affect the electrical conductivity of the device.

[0116] 3. Thermal Strain Analysis

[0117] Taking the overall replacement scheme on both sides as an example, calculate the influence of the replacement scheme with high - thermal - conductivity materials on the thermal strain of the device. The calculation formula of thermal strain is shown in Equation (4), where α is the thermal expansion coefficient of the material, ΔT is the change in material temperature, and ε is the thermal strain of the material. Substitute the thermal expansion coefficients of molybdenum and copper - diamond into Equation (5) respectively, and calculate the thermal strain at a temperature difference of 100 °C according to the device structure. The calculation results show that the thermal strain between copper - diamond and the chip after overall replacement is 4.6×10 -4 , and the thermal strain between molybdenum and silicon under the same working conditions is 2.3×10 -4 . The thermal strain before and after replacement is of the same order of magnitude and is very small.

[0118] ε = αΔT (4)

[0119] ε Si-Mo / CuC =(α Si - α Mo / CuC )ΔT (5)

[0120] The present invention also discloses a power device adopting a packaging structure, and the power device is, for example, an IGCT, an IGBT, a GTO, or a Thyristor (ordinary thyristor).

[0121] The present invention also discloses a power semiconductor device adopting the above - mentioned packaging structure. The power semiconductor device is, for example, a device using an IGBT, an IGCT, etc. as a control element and / or a switching element, such as a commutation valve.

[0122] The above - described specific embodiments have further elaborated on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above - mentioned are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A power semiconductor device packaging structure, characterized in that Comprising: A chip; A cathode electrode disposed on the first side of the chip; And An anode electrode disposed on the second side of the chip opposite to the first side; Wherein, at least one of the cathode electrode and the anode electrode is prepared using a conductive metal composite material; wherein, the conductive metal composite material is copper diamond or aluminum diamond, and in the copper diamond or aluminum diamond, the volume fraction of diamond is 40%-70%; the thermal conductivity of the conductive metal composite material is greater than 400 W / m·K, and the coefficient of thermal expansion is less than 10e-6 / K; the flatness of the surface of the cathode electrode and the anode electrode facing the chip side is less than or equal to 10 μm, and the surface roughness Ra is less than or equal to 0.7 μm; the cathode electrode and / or anode electrode prepared from the conductive metal composite material has a diamond concentration distribution with a radial gradient, such that the cathode electrode and / or anode electrode has different coefficients of thermal expansion in the radial direction, and the closer to the center of the electrode, the higher the coefficient of thermal expansion.

2. The power semiconductor device packaging structure according to claim 1, characterized in that, One of the cathode electrode and the anode electrode is directly connected to the chip, and the other is connected to the chip through a buffer layer; or Both the cathode electrode and the anode electrode are directly connected to the chip.

3. The power semiconductor device package structure according to claim 1, wherein A Ni-Ag coating or a nano-silver particle deposition layer is formed on the surface of the cathode electrode and the anode electrode facing the chip side, or A Ni-Ag coating or a nano-silver particle deposition layer is formed only on the surface of one of the cathode electrode and the anode electrode facing the chip side; The surface flatness less than or equal to 10 μm and the surface roughness Ra less than or equal to 0.7 μm are achieved through the Ni-Ag coating or the nano-silver particle deposition layer.

4. The power semiconductor device packaging structure according to claim 1 or 2, characterized in that, It further includes a transition metal ring, the transition metal ring is connected between the electrode and the metal flange, and the coefficient of thermal expansion of the transition metal ring is greater than that of the electrode and less than that of the metal flange.

5. The power semiconductor device package structure according to claim 1 or 2, characterized in that, The electrode has a stepped structure on its radial cross-section.

6. A manufacturing method of a power semiconductor device packaging structure according to any one of claims 1-5, characterized in that, Including the following steps: Connect one of the cathode electrode and the anode electrode to the chip on the first side by mechanical pressure or sintering; Connect the other electrode of the cathode electrode and the anode electrode to the chip on the second side opposite to the first side by mechanical pressure or sintering; Wherein: At least one of the cathode electrode and the anode electrode uses a conductive metal composite material; at least one of the cathode electrode and the anode electrode has its surface facing the chip treated with a Ni-Ag coating or nano-silver particle deposition before crimping.

7. A power device using the packaging structure according to any one of claims 1-5, the power device being an IGCT, IGBT, GTO.

8. A power device using the packaging structure according to any one of claims 1-5, the power device being a conventional thyristor.

9. An electronic device, the electronic device using the power device according to claim 7 or 8 as a control element and / or a current / voltage switching element.

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