Power charging and discharging management circuit, power management chip, and electronic device

Abstract

The present invention discloses a power charging and discharging management circuit, a power management chip and an electronic device. The power charging and discharging management circuit includes a first power management module, a charging and discharging module, a second power management module, a third power management module and a monostable delay module. The first power management module is used to step down the voltage output by the power supply and provide it to the charging and discharging module; the charging and discharging module is used to store electrical energy; the second power management module is used to boost the electrical energy stored in the charging and discharging module to a target voltage; and, is used to boost the voltage output by the third power management module to the target voltage; the monostable delay module is used to stop the second power management module from supplying power to the host computer after a first preset duration when receiving an instruction sent by the host computer to turn off the power supply of the second power management module to the host computer.

Description

Technical Field

[0001] The present application relates to the technical field of power management, and particularly to a power charge and discharge management circuit, a power management chip, and an electronic device. Background Art

[0002] In modern electronic systems, the power charge and discharge management circuit is a core component to ensure the performance and reliability of devices. With the trend of electronic devices towards high performance and miniaturization, the requirements for power charge and discharge management circuits are also increasing day by day.

[0003] In the prior art, as Figure 1 shown, the power charge and discharge management circuit usually uses a combination of an optocoupler and an electromagnetic relay to control the switching of the power supply. However, the existing power charge and discharge management circuits mainly have the following problems in use: First, the combination of the optocoupler and the relay usually occupies a large space, making the power charge and discharge management circuit inapplicable to miniaturized application scenarios. In modern electronic designs, devices are increasingly inclined towards miniaturization. Therefore, the large-sized power management components limit the design flexibility and innovation. Second, the cost of manufacturing and assembling the optocoupler and the electromagnetic relay is relatively high, which burdens the competitiveness of cost-sensitive products. Third, the relay relies on physical contact to switch the circuit, and after long-term repeated use of the physical contacts of the relay, the contact resistance increases, which may lead to poor contact, reducing the efficiency of the power system, and under harsh usage conditions, it will significantly affect the reliability and lifespan of the power charge and discharge management circuit. Fourth, the existing power charge and discharge management circuits also have the risk of system startup failure. When the relay receives the power-off command from the host computer, if the host computer is already in a powered-off state, but the system then resumes power supply, it may cause the host computer to fail to shut down. This not only makes the device unable to restart, but may also cause the system to freeze, resulting in serious reliability problems.

[0004] Therefore, there is a need for a new type of power charge and discharge management circuit nowadays to overcome the deficiencies in the prior art. Summary of the Invention

[0005] Based on this, in view of the above technical problems, a power charge and discharge management circuit, a power management chip, and an electronic device are provided, which can solve the problems of large volume, high cost, poor reliability, and high system startup failure rate of the power charge and discharge management circuit in the prior art.

[0006] In a first aspect, a power charge and discharge management circuit, the circuit includes a first power management module, a charge and discharge module, a second power management module, a third power management module, and a monostable delay module;

[0007] The input end of the first power management module is connected to a power supply, the output end of the first power management module is connected to the input end of the charge and discharge module, the output end of the charge and discharge module is connected to the first input end of the second power management module, and the output end of the second power management module is respectively connected to a host computer and the input end of the third power management module; the output end of the third power management module is connected to the input end of the monostable delay module, and the output end of the monostable delay module is connected to the second input end of the second power management module; the monostable delay module is also connected to the host computer;

[0008] Wherein, the first power management module is used to step down the voltage output by the power supply and supply it to the charge and discharge module; the charge and discharge module is used to store electric energy; the second power management module is used to boost the electric energy stored by the charge and discharge module to a target voltage; and, to boost the voltage output by the third power management module to the target voltage; the monostable delay module is used to stop the second power management module from supplying power to the host computer after a first preset duration when receiving an instruction sent by the host computer to turn off the power supply of the second power management module to the host computer.

[0009] In the above solution, optionally, the monostable delay module is further used to control the power charge and discharge management circuit to automatically turn off after stopping the second power management module from supplying power to the host computer, so that the control system is turned off.

[0010] In the above solution, further optionally, the host computer is further used to control the second power management module to supply power to the host computer again through the monostable delay module after a second preset duration after stopping the second power management module from supplying power to the host computer.

[0011] In the above solution, further optionally, the charge and discharge module includes at least one super capacitor, and the super capacitor is used to supply power to the host computer when the control system loses power or is interfered.

[0012] In the above solution, further optionally, the first preset duration is 5 seconds.

[0013] In the above solution, further optionally, both the first power management module and the third power management module include BUCK chips.

[0014] In the above solution, further optionally, the second power management module includes a BOOST chip.

[0015] In the above solution, further optionally, the circuit further includes a control module, and the first power management module, the charge and discharge module, the second power management module, the third power management module, and the monostable delay module are respectively connected to the control module;

[0016] Wherein, the control module is used to monitor the power supplies of the first power management module, the charge and discharge module, the second power management module, the third power management module, and the monostable delay module.

[0017] In a second aspect, a power management chip includes the power charge and discharge management circuit according to any one of the first aspects above.

[0018] In a third aspect, an electronic device includes the power management chip according to the second aspect above.

[0019] The present invention has at least the following beneficial effects:

[0020] Based on further analysis and research of the problems in the prior art, it is recognized that the existing power supply has problems such as a relatively large volume, high cost, poor reliability of the charge and discharge management circuit, and a relatively high system startup failure rate. In this application, a charge and discharge management circuit is composed of a first power management module, a charge and discharge module, a second power management module, a third power management module, and a monostable delay module. Among them, the first power management module is used to step down the voltage output by the power supply and provide it to the charge and discharge module; the charge and discharge module is used to store electrical energy; the second power management module is used to boost the electrical energy stored in the charge and discharge module to a target voltage; and, to boost the voltage output by the third power management module to the target voltage; the monostable delay module is used to stop the second power management module from supplying power to the host computer after a first preset duration when receiving an instruction from the host computer to turn off the power supply of the second power management module to the host computer. The charge and discharge management circuit provided in this application is a chip-level power management circuit, which is small in volume and low in cost, and can be used in a miniaturized manner; at the same time, it also avoids the mechanical relay contacts and does not need to consider the problems of life and switch reliability. In addition, the charge and discharge management circuit provided in this application cleverly handles the problem of the host computer crashing caused by the system being powered on again during the power-off process of the host computer, and has high reliability. Description of the Drawings

[0021] Figure 1 It is a circuit principle block diagram of a power charge and discharge management circuit in the prior art;

[0022] Figure 2 It is a circuit principle block diagram of a power charge and discharge management circuit provided by an embodiment of the present invention;

[0023] Figure 3 The circuit principle block diagram of the power charging and discharging management circuit provided by another embodiment of the present invention;

[0024] Figure 4 The power-on timing diagram of the monostable delay module provided by an embodiment of the present invention;

[0025] Figure 5 The circuit schematic diagram of the power charging and discharging management circuit provided by an embodiment of the present invention. Detailed implementation manners

[0026] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0027] As Figure 2 shown, the present application provides a power charging and discharging management circuit, which is characterized in that the circuit includes a first power management module, a charging and discharging module, a second power management module, a third power management module and a monostable delay module;

[0028] The input end of the first power management module is connected to a power supply, the output end of the first power management module is connected to the input end of the charging and discharging module, the output end of the charging and discharging module is connected to the first input end of the second power management module, and the output end of the second power management module is respectively connected to a host computer and the input end of the third power management module; the output end of the third power management module is connected to the input end of the monostable delay module, and the output end of the monostable delay module is connected to the second input end of the second power management module; the monostable delay module is also connected to the host computer;

[0029] Wherein, the first power management module is used for step-down processing of the voltage output by the power supply and providing it to the charging and discharging module; the charging and discharging module is used for storing electric energy; the second power management module is used for boosting the electric energy stored by the charging and discharging module to a target voltage; and, for boosting the voltage output by the third power management module to the target voltage; the monostable delay module is used for stopping the power supply of the second power management module to the host computer after a first preset duration when receiving an instruction sent by the host computer to turn off the power supply of the second power management module to the host computer.

[0030] It should be noted that the power charging and discharging management circuit provided by the present application has low cost, high efficiency and high reliability, and can solve the defects of the power charging and discharging management circuit in the prior art.

[0031] In this embodiment, the power supply charge and discharge management circuit provided by the present application can shield power supply interference and fluctuations within 5 seconds; and the host computer can automatically power off, reset, and restart. That is, after the host computer shuts off its own power supply, after a certain delay time, the power supply of the host computer can be restored again. In addition, after the power supply of the control system is cut off, the host computer can be continuously powered for 5 seconds. After the host computer completes data saving, it starts a self-shutdown program to ensure reliable shutdown of the system.

[0032] In the embodiment of the present application, the charge and discharge management circuit is composed of a first power management module, a charge and discharge module, a second power management module, a third power management module, and a monostable delay module. Among them, the first power management module is used to step down the voltage output by the power supply and provide it to the charge and discharge module; the charge and discharge module is used to store electrical energy; the second power management module is used to boost the electrical energy stored in the charge and discharge module to the target voltage; and, to boost the voltage output by the third power management module to the target voltage; the monostable delay module is used to stop the second power management module from supplying power to the host computer after a first preset duration when receiving an instruction from the host computer to turn off the power supply to the host computer by the second power management module. The charge and discharge management circuit provided by the present application is a chip-level power management circuit, which is small in size and low in cost, and can be used in a miniaturized manner; at the same time, it also avoids mechanical relay contacts and does not need to consider issues such as lifespan and switch reliability. In addition, the charge and discharge management circuit provided by the present application cleverly handles the problem of the host computer crashing caused by the system powering on again during the power-off process of the host computer, and has high reliability.

[0033] In the embodiment of the present application, the charge and discharge management circuit uses chip-level modules to achieve miniaturized application; it can reliably turn off the power supply of the host computer, avoid the phenomenon of the host computer crashing during power-on and power-off, and has high reliability. At the same time, by using a super capacitor, when the system loses power or is interfered, it can continue to effectively support the host computer to work uninterruptedly for several seconds, and the reliability is very high.

[0034] In the embodiment of the present application, a monostable delay module is adopted, which has multiple functions of adjustable delay and monitoring the power supply of the host computer, realizes reliable cutting off of the power supply of the host computer, and effectively avoids the phenomenon of the host computer restarting failure. Based on the characteristics of the boost module, a circuit is designed so that the monostable delay module can still work normally after the boost is powered off. In addition, the charge and discharge management circuit of the present application can also automatically filter out interference and fluctuations of the input power supply within 5 seconds, improving the safety and reliability of power supply.

[0035] Such as Figure 3As shown, in the embodiments of the present application, the power supply is the overall input power supply of the invention circuit; the power supply is the output power supply of the host computer, and at the same time, it supplies power to the monostable delay module; the BUCK power supply module: reduces the power supply to a suitable power range for supplying power to the charge and discharge module; the charge and discharge module: stores electrical energy; the BOOST power supply module: boosts the BUCK power supply or the stored electrical energy to the potential required by the host computer; the monostable delay module: realizes the soft start of the system and receives the instruction from the host computer to cut off its power supply.

[0036] As Figure 4 shown, Figure 4 is the power-on timing sequence of the monostable delay module. Through this power-on timing sequence, the working process of the power charge and discharge management circuit can be clearly explained.

[0037] As Figure 5 shown, when the control system is powered on, 5.3V charges the super capacitor, and at the same time powers on the boost power supply module, and 12V2 is powered. Q14 conducts, Q18 is cut off, Q24 switch conducts, the host computer power supply 12V3 is powered on, Q15 conducts, and the circuit realizes reliable self-locking, that is: when the power supply is disconnected, 5.3V has no power, Q14 is disconnected, and the circuit can continue to be powered by the super capacitor boost power supply module for a period of time.

[0038] When the host computer completes data storage and needs to cut off its own power supply, or needs to cut off power and reset and restart itself, Q17 will receive a falling-edge trigger signal. At this time, the C (clock) pin of U14 obtains a rising-edge trigger signal, the Q of U14 outputs a high level, Q18 conducts, Q14 and Q15 are cut off, and the Q24 switch is cut off, and the host computer is powered off. By adjusting the parameters of R118 and C77, the conduction time of Q18 can be set to ensure that Q24 is reliably cut off. The high level of Q of U14 will charge C77 through R118. When the charging is completed, the R pin of U14 becomes high level, causing the Q of U14 to jump to low level, Q18 is cut off, completing the automatic unlocking of the circuit and preparing for the re-conduction of Q24.

[0039] When Q17 receives the falling-edge trigger signal, that is, the host computer shutdown signal, and Q18 conducts, it will ensure that Q14 and Q15 are reliably cut off, so that the host computer can be reliably shut down and will not be affected by the system powering on again at this moment. That is, regardless of whether the system powers on again, the host computer will complete a reliable shutdown before responding to the system power-on.

[0040] In one embodiment, the first preset duration is 5 seconds.

[0041] In this embodiment, it should be noted that the value of the first preset duration can be adjusted.

[0042] In one embodiment, both the first power management module and the third power management module include BUCK chips.

[0043] In one embodiment, the second power management module includes a BOOST chip.

[0044] In one embodiment, the monostable delay module is further configured to control the power charge and discharge management circuit to automatically turn off after stopping the second power management module from supplying power to the host computer, so as to turn off the control system.

[0045] Among them, the control system refers to the entire electronic device or electronic system. The control system relies on the power charge and discharge management circuit to control and manage its power supply. Generally, the control system may include electronic components such as a processor, memory, sensors, actuators, etc. The processor, memory, sensors, actuators and other electronic components cooperate together to complete specific functions. The host computer refers to the main computing device or logical control unit that controls this control system. The host computer may be a microcontroller, a processor or a more complex computing platform.

[0046] Among them, soft starting the control system refers to a software-controlled startup process. The power management circuit allows the control system to start slowly or in a predetermined step according to a certain program and conditions, which is more gradual and controlled than directly switching on the hardware power supply. Soft starting the control system helps to prevent voltage surges caused by sudden power-on, thereby protecting electronic components and ensuring that the control system can start normally in a safe state.

[0047] In this embodiment, after receiving the power-off instruction from the host computer, the monostable delay module may ensure that the power supply is cut off in a controllable manner, and the control system can also be started in a safe and predetermined manner when the power supply is restored. The above is the way for the monostable delay module to achieve soft starting of the control system, which provides a protection measure to prevent startup failures or hardware damages caused by power supply problems.

[0048] In one embodiment, the host computer is further configured to control the second power management module to supply power to the host computer again through the monostable delay module after a second preset duration after stopping the second power management module from supplying power to the host computer.

[0049] In one embodiment, the charge and discharge module includes at least one super capacitor, and the super capacitor is used to supply power to the host computer when the control system loses power or is interfered.

[0050] In one embodiment, the circuit further includes a control module, and the first power management module, the charge and discharge module, the second power management module, the third power management module, and the monostable delay module are respectively connected to the control module;

[0051] Wherein, the control module is configured to monitor the power supplies of the first power management module, the charge and discharge module, the second power management module, the third power management module, and the monostable delay module.

[0052] In the embodiments of the present application, by only setting a monostable trigger core with an adjustable delay time, a low-power control module can also be adopted to monitor the power supplies of the first power management module, the charge and discharge module, the second power management module, the third power management module, and the monostable delay module, so as to better complete the power management function of the host computer.

[0053] The present application also provides a power management chip, which includes the power charge and discharge management circuit described in the above embodiments.

[0054] The present application also provides an electronic device, which includes the power management chip described in the above embodiments.

[0055] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A power charging and discharging management circuit, characterized in that, The circuit includes a first power management module, a charge and discharge module, a second power management module, a third power management module, and a monostable delay module; The input end of the first power management module is connected to a power supply, the output end of the first power management module is connected to the input end of the charge and discharge module, the output end of the charge and discharge module is connected to the first input end of the second power management module, and the output end of the second power management module is respectively connected to a host computer and the input end of the third power management module; the output end of the third power management module is connected to the input end of the monostable delay module, and the output end of the monostable delay module is connected to the second input end of the second power management module; the monostable delay module is also connected to the host computer; Among them, the first power management module is used to step down the voltage output by the power supply and supply it to the charge and discharge module; the charge and discharge module is used to store electrical energy; the second power management module is used to boost the electrical energy stored by the charge and discharge module to a target voltage; the third power management module is used to step down the target voltage output by the second power management module to a first voltage, and the first voltage is the power supply voltage of the monostable delay module; the monostable delay module is used to stop the second power management module from supplying power to the host computer after a first preset duration when receiving an instruction from the host computer to turn off the power supply of the second power management module to the host computer; The monostable delay module is also used to control the automatic shutdown of the power charge and discharge management circuit after stopping the second power management module from supplying power to the host computer, so that the control system shuts down; The host computer is also used to control the second power management module to supply power to the host computer again through the monostable delay module after a second preset duration after stopping the second power management module from supplying power to the host computer; The charge and discharge module includes at least one super capacitor, and the super capacitor is used to supply power to the host computer when the control system loses power or is interfered; Among them, when the monostable delay module receives a falling-edge trigger signal sent by the host computer, the monostable delay module outputs a high-level signal to the second power management module, so that the second power management module stops supplying power to the host computer and the host computer loses power; When the charge and discharge module is fully charged, the monostable delay module outputs a low-level signal to the second power management module to unlock the second power management module.

2. The circuit according to claim 1, wherein, The first preset duration is 5 seconds.

3. The circuit according to claim 1, wherein Both the first power management module and the third power management module include BUCK chips.

4. The circuit according to claim 1, wherein The second power management module includes a BOOST chip.

5. The circuit according to claim 1, wherein The circuit further includes a control module, and the first power management module, the charge and discharge module, the second power management module, the third power management module, and the monostable delay module are respectively connected to the control module; Wherein, the control module is used to monitor the power supplies of the first power management module, the charge and discharge module, the second power management module, the third power management module and the monostable delay module.

6. A power management chip, characterized in that, Comprising the power charge and discharge management circuit according to any one of claims 1 to 5.

7. An electronic device, characterized in that, Comprising the power management chip according to claim 6.

Images