amplifier circuit

Abstract

An amplifier circuit of the present application has: a first transistor through which a first input current flows between a drain and a source; a second transistor through which a second input current flows between a drain and a source; a first-1 current source that supplies a specific current to a gate of the first transistor; a first-2 current source that supplies a specific current to a gate of the second transistor; a pair of adjustment resistors connected in series between the gate of the first transistor and the gate of the second transistor; a connection path that connects a connection point of the pair of adjustment resistors to the drain of the first transistor; and a second current source that supplies a current to the drain of the second transistor; and the current from the first-1 current source is supplied to the drain of the first transistor via one of the pair of adjustment resistors, and the current from the first-2 current source is supplied to the drain of the first transistor via the other adjustment resistor, and by relatively adjusting the resistance values of the first adjustment resistor and the second adjustment resistor, the gate voltage offset of the first transistor and the second transistor can be adjusted.

Description

TECHNICAL FIELD

[0001] The present application relates to an offset adjustment of an amplifier circuit using a pair of transistors whose gates are commonly connected. BACKGROUND

[0002] In the past, in an operational amplifier using a pair of transistors, offset compensation of the pair of transistors was required. For example, in the case of an operational amplifier in which the gates of a pair of transistors are connected to each other and there is a pair of current input terminals from the sources, a pair of resistors is arranged at the sources of the transistors, and offset compensation is performed by adjusting these resistors.

[0003] In a circuit in which the voltage drop on an adjustment resistor is feedback-adjusted using an operational amplifier, an additional current source is required. In addition, if the additional circuit is provided, there is a problem of operation delay due to stray capacitance and the like. SUMMARY

[0004] The amplifier circuit of the present application has:

[0005] a first transistor M2 through which a first input current flows between the drain and the source;

[0006] a second transistor M4 through which a second input current flows between the drain and the source;

[0007] a first-1 current source ibla that supplies a specific current to the gate of the first transistor M2;

[0008] a first-2 current source iblb that supplies a specific current to the gate of the second transistor M4;

[0009] a pair of adjustment resistors Rt1 and Rt2 connected in series between the gate of the first transistor and the gate of the second transistor;

[0010] a connection path that connects the connection point of the adjustment resistors Rt1 and Rt2 to the drain of the first transistor; and

[0011] a second current source ib2 that supplies a current to the drain of the second transistor; and

[0012] the current from the first-1 current source ibla is supplied to the drain of the first transistor M2 via the first adjustment resistor Rt1, and the current from the first-2 current source iblb is supplied to the drain of the first transistor M2 via the second adjustment resistor Rt2;

[0013] By relatively adjusting the resistance values of the first adjustment resistor and the second adjustment resistor, the gate voltage offsets of the first transistor and the second transistor can be adjusted.

[0014] According to the amplifier circuit of the present application, offset adjustment can be performed by trimming a pair of resistors disposed in a path to the gate of a transistor, without the need for an additional operational amplifier or the like. In addition, an increase in stray capacitance can be suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a circuit diagram showing the configuration of an amplifier circuit of an embodiment.

[0016] Figure 2 is a circuit diagram showing the configuration of an amplifier circuit of another embodiment.

[0017] Figure 3 is a circuit diagram showing the configuration of an amplifier circuit of a further embodiment.

[0018] Figure 4 is a circuit diagram showing the configuration of an amplifier circuit of a further embodiment. DETAILED DESCRIPTION

[0019] Embodiments of the present application will be described below with reference to the accompanying drawings. Note that the following embodiments do not limit the present application, and configurations selectively combined from a plurality of examples are also included in the present application.

[0020] "Circuit Configuration"

[0021] Figure 1 is a circuit diagram showing the configuration of an amplifier circuit of an embodiment. In this circuit, as a transistor, an N-type MOSFET (metal-oxide-semiconductor field-effect transistor) is used. A P-type MOSFET can be used to configure the circuit. In this case, the polarity of the current direction and the like of the circuit must be appropriately reversed.

[0022] The amplifier circuit has four transistors Mn1 to Mn4, and the gates of the transistors Mn2 and Mn4 are commonly connected. The transistors Mn2 and Mn4 are connected in cascade with the transistors Mn1 and Mn3. The transistor Mn2 is referred to as a first transistor, and the transistor Mn4 is referred to as a second transistor. In addition, the transistors Mn1 and Mn3 are referred to as cascade transistors.

[0023] The drain of the transistor Mn2 is connected to the source of the transistor Mn1, and a first current input terminal inp is led out from the source of the transistor Mn2.

[0024] The gate of the transistor Mn1 is connected to a first-1 current source ibla. The gate of the transistor Mn1 is also connected to the gate of the transistor Mn2 via a resistor Rla.

[0025] The gate of the transistor Mn2 is also connected to the drain of the transistor Mn 1 via the resistor Rt 1.

[0026] Further, the drain of the transistor Mn4 is connected to the source of the transistor Mn3, and the second current input terminal inn is drawn from the source of the transistor Mn4.

[0027] The gate of the transistor Mn3 is connected to the first-2 current source iblb. The gate of the transistor Mn3 is also connected to the gate of the transistor Mn4 via the resistor Rlb. Here, as long as the gate voltages of the transistors Mn2 and Mn4 can be set appropriately by the first-1 current source ibla and the first-2 current source iblb, the resistors Rla and Rlb can be omitted.

[0028] The gate of the transistor Mn4 is also connected to the resistor Rt 1 via the resistor Rt2. That is, the gate of the transistor Mn 1 and the gate of the transistor Mn4 are connected by a pair of adjustment resistors, namely, the resistors Rt 1 and Rt2. The connection point of the resistors Rt 1 and Rt2 is connected to the drain of the transistor Mn 1. The resistor Rt 1 is referred to as a first adjustment resistor, and the resistor Rt2 is referred to as a second adjustment resistor.

[0029] The drain of the transistor Mn3 is connected to the second current source ib2 and to the output terminal vout.

[0030] Therefore, the current from the first-1 current source ibla is supplied to the drain of the transistor Mn 1 via the resistor Rla and the resistor Rt 1, and the current from the first-2 current source iblb is supplied to the drain of the transistor Mn 1 via the resistor Rlb and the resistor Rt2, and then flows in the transistors Mn 1 and Mn2 and flows out as the first current inp.

[0031] Further, the current from the second current source ib2 flows in the transistors Mn3 and Mn4 and flows out as the second current inn. Also, the drain voltage of the transistor Mn3 is output as the voltage vout from the output terminal vout.

[0032] Here, when the gate voltage of the transistor Mn 1 is set as vc 1, the gate voltage of the transistor Mn2 is set as vg 1, the voltage at the connection point of the resistor Rt 1 and the resistor Rt2 (the drain of the transistor Mn 1) is set as vb, the gate voltage of the transistor Mn3 is set as vc2, and the gate voltage of the transistor Mn4 is set as vg2,

[0033] vc 1 - vg 1 = ibla * Rla

[0034] and

[0035] vc2 - vg2 = iblb * Rlb,

[0036] Therefore, the gate voltage difference between the transistor Mn1 and the transistor Mn2 connected in cascade and the gate voltage difference between the transistor Mn3 and the transistor Mn4 connected in cascade are independent of and not affected by the values of the resistance Rt1 or the resistance Rt2.

[0037] In addition, at the time of design, the transistor sizes and resistance values are set in such a manner that ib2 = ibla + iblb. Therefore, the current synthesized at the connection point of the resistance Rt1 and the resistance Rt2 is ibla + iblb, and the current flowing in the transistor Mn1 and the transistor Mn2 is ib2 (= ibla + iblb).

[0038] Furthermore, it is also possible to set the transistor Mn1 and the transistor Mn3 to have the same size, and the transistor Mn2 and the transistor Mn4 to have the same size.

[0039] In order to make the drain-source voltage Vds of the transistor Mn2 and the transistor Mn4 the same, the voltage drop across the resistance Rla and the voltage drop across the resistance Rlb are the same.

[0040] Therefore,

[0041] Rla = Rlb.

[0042] Under such conditions, by setting the resistance values of the resistance Rt1 and the resistance Rt2, it is possible to adjust the offset voltage at the input terminal of the amplifier circuit.

[0043] That is, the offset voltage vos of the input terminal inp and the input terminal inn is

[0044] vinp - vinn,

[0045] This is given by the following equation:

[0046] vg1 - vg2.

[0047] Here,

[0048] vg1 - vb = ibla * Rt1

[0049] vg2 - vb = iblb * Rt2.

[0050] By subtracting the two equations, the offset voltage vos is expressed by the following equation:

[0051] vos = vg1 - vg2 = ibla * Rt1 - iblb * Rt2.

[0052] Here,

[0053] ib2 / 2 = ibla = iblb.

[0054] When the adjustment amount of the resistance Rt1 and the resistance Rt2 is set to t,

[0055] Rt1 = Rt * (1 + t),

[0056] Therefore,

[0057] Rt2 = Rt * (1 - t)

[0058] vos = ibla * Rt1 - iblb * Rt2 = ib2 / 2 * (Rt1 - Rt2)

[0059] = ib2 / 2 * Rt * 2t = ib2 * Rt * t (-1 < t < 1).

[0060] Thus, in the amplifier circuit of Figure 1 , the total resistance value of the resistances Rt1 and Rt2 can be maintained, and at the same time, the offset voltage can be adjusted by increasing the adjustment value t in one of them and decreasing the adjustment value t in the other (trimming).

[0061] Thus, in the present embodiment, the offset voltage of the pair of input terminals can be compensated by the current flowing in the pair of resistances Rt1 and Rt2 connected to the gates of the transistors Mn2 and Mn4. Therefore, an extra offset adjustment circuit or the like is not needed. Since the offset voltage can be compensated by the bias current of the series connection of the diode-connected transistor Mn1 and the transistor Mn2, a dedicated current source for offset compensation is not needed.

[0062] In addition, in the present embodiment, a cascade connection is used, and therefore, the voltage between the drain and the source of the transistor Mn2 and the transistor Mn4 can be maintained to be the same, and high-precision current control can be performed.

[0063] "Other Configuration 1"

[0064] Figure 2 is a circuit diagram showing the configuration of another embodiment. In this example, the first-1 current source ibla and the first-2 current source iblb in the example are integrated into one first current source ibl. Furthermore, the current from the one first current source ibl is divided into two halves and supplied to the resistance Rla and the resistance Rlb. This configuration also enables the same operation as in the case. Figure 1

[0065] is a circuit diagram showing the configuration of further another embodiment. In this example, in addition to the first-1 current source ibla and the first-2 current source iblb in the example, a first-3 current source iblc is provided. Figure 3 Figure 1

[0066] ​​The first-third current source ib1c adds current ib1c to the current flowing from the connection point of resistors Rt1 and Rt2 toward transistor Mn1.

[0067] therefore,

[0068] ib1 = ib2 = ib1a + ib1b + ib1c

[0069] By making the currents ib1a and ib1b relatively small, actions corresponding to the input currents inp and inn can be achieved.

[0070] also, Figure 3 In this configuration, when the adjustment amounts of resistors Rt1 and Rt2 are relatively small, the current flowing through resistors Rt1 and Rt2 is small, equivalent to current ib1c. Therefore, the combined resistance of resistors Rt1 and Rt2 can be made relatively large. Regarding resistors on ICs, the thin-layer resistors are fixed. Depending on the manufacturing process, sometimes a larger layout area is required to produce resistors with smaller resistance values. Figure 3 Examples can eliminate this drawback.

[0071] Figure 4 This is a circuit diagram illustrating the configuration of further embodiments. In this example, with... Figure 2 Similarly, the first current source ib1a and the first current source ib1b are combined into a single first current source ib1, while the cascaded transistors Mn1 and Mn3 are omitted. Therefore, the first current source ib1 is connected to the gate of transistor Mn2 via resistor R1a and to the gate of transistor Mn4 via resistor R1b. With this configuration, the current accuracy of transistors Mn2 and Mn4 is reduced, but offset compensation can still be achieved using resistors Rt1 and Rt2.

Claims

1. An amplifier circuit, comprising: The first transistor carries the first input current between its drain and source. The second transistor allows the second input current to flow between its drain and source. The first-1 current source supplies bias current to the gate of the first transistor; The first and second current sources supply bias current to the gate of the second transistor; A pair of adjusting resistors are connected in series between the gate of the first transistor and the gate of the second transistor; A connection circuit is formed by connecting the connection point of the pair of adjusting resistors to the drain of the first transistor; as well as The second current source supplies current to the drain of the second transistor; and The current from the first-1 current source is supplied to the drain of the first transistor via one of the pair of adjustment resistors, and the current from the first-2 current source is supplied to the drain of the first transistor via the second adjustment resistor; The gate voltage offset of the first transistor and the second transistor can be adjusted by relatively adjusting the resistance values ​​of the first adjustment resistor and the second adjustment resistor.

2. The amplifier circuit according to claim 1, further comprising: The first resistor is disposed on the connection path between the first-1 current source and the gate of the second transistor; and The second resistor is configured on the connection path between the first and second current sources and the gate of the second transistor.

3. The amplifier circuit according to claim 1, wherein... Cascaded transistors are added to the drain side of the first transistor and the second transistor, respectively.

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