A SiC MOSFET active gate drive circuit based on controllable gate current

Abstract

The present invention relates to a SiC MOSFET active gate drive circuit based on a controllable gate current. For the SiC MOSFET U1 to be tested included in the double-pulse test circuit (8), a drive current is provided to the current push-pull amplification circuit (3) based on the drive voltage provided by the drive voltage supply circuit (1) and the current conversion circuit (2) in sequence. The controllable current overshoot suppression circuit (4) is combined to detect and generate a controllable current overshoot suppression current, and the voltage overshoot suppression circuit (5) is used to detect and generate a voltage overshoot suppression current. The drive current is amplified by the current push-pull amplification circuit (3) to drive the SiC MOSFET U1 to be tested. The design scheme realizes controllable gate current control, so that during the switching process of the SiC MOSFET U1 to be tested, it can be turned on and off orderly, and the current and voltage overshoot phenomena can be more effectively suppressed.

Description

Technical Field

[0001] The present invention relates to a SiC MOSFET active gate drive circuit based on controllable gate current, belonging to the technical field of drive circuits. Background Art

[0002] As a wide-bandgap semiconductor material, SiC has the advantages of high breakdown electric field strength, high electron saturation drift velocity, high thermal conductivity, etc. Therefore, SiC MOSFET has the characteristics of high breakdown voltage, fast switching speed, low loss, etc., and is widely used in the field of high-frequency power electronics.

[0003] Compared with traditional Si MOSFET, SiC MOSFET has excellent characteristics such as high breakdown voltage, high current density, high switching frequency, and high operating temperature. Nowadays, DC-DC converters developed with SiC MOSFET have been used in the power supplies of some fields, such as energy, medical, transportation, etc., and their application scope is becoming increasingly wide. SiC MOSFET has become one of the most concerned in the research of power semiconductor devices. Therefore, in related specific application circuits, it is also very necessary to study the optimization and improvement of using SiC MOSFET to replace traditional silicon Si MOSFET. Due to the characteristics of high temperature resistance, small volume, high power, high efficiency, etc., the research on SiC MOSFET drive circuits is becoming more and more extensive and the application is becoming more and more popular.

[0004] However, in practical applications, parasitic parameters in devices and circuits are inevitable. When the SiC MOSFET device operates under high-frequency conditions, due to the existence of stray inductance and parasitic capacitance in the circuit, overshoot and oscillation phenomena will occur in the voltage and current passing through the SiC MOSFET. When the voltage or current overshoot exceeds the breakdown voltage of the SiC MOSFET or the maximum recovery current of the anti-parallel diode of the SiC MOSFET, the SiC MOSFET device will be damaged.

[0005] The conventional gate driver (CGD) adjusts the switching speed of the power device by changing the gate drive voltage, drive resistance, gate input capacitance, etc. These methods adjust the speed of the entire turn-on or turn-off process of the power device, but cannot flexibly adjust the switching speed of the power device in some stages of turn-on or turn-off.

[0006] The literature "Shuang Zhao, Xingchen Zhao, Audrey Dearien, Yuheng Wu, Yue Zhao and H. Alan Mantooth, 'An Intelligent Versatile Model-Based Trajectory-Optimized Active Gate Driver for Silicon Carbide Devices,' [J] IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 8, no. 1, pp. 429-441, Mar. 2020" proposes a scheme for realizing active driving by switching voltages during the switching process. An active gate drive is achieved during the switching process of the SiC MOSFET through three control signals S1, S2, and S3. If the goal is to reduce the current overshoot during the turn-on process, slow turn-on control is selected; if the goal is to accelerate the switching speed and reduce the switching loss, fast turn-on control is selected. The control strategy proposed in this literature is theoretically feasible, but it requires the use of multiple switching tubes and multiple control signals. When switching different levels of the driving power supply, it will have a greater impact on the gate circuit, which may cause current oscillation, and this scheme does not adopt closed-loop control, so its versatility is poor. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a SiC MOSFET active gate drive circuit based on a controllable gate current. A controllable current overshoot suppression circuit and a voltage overshoot suppression circuit are designed and added during the turn-on and turn-off processes to cut in and extract the gate current to slow down the voltage and current overshoot phenomena during the switching process.

[0008] The present invention adopts the following technical solutions to solve the above technical problems: The present invention designs a SiC MOSFET active gate drive circuit based on a controllable gate current, which is used to drive the SiC MOSFET U1 to be tested included in the double-pulse test circuit, and includes a driving voltage providing circuit, a current conversion circuit, a current push-pull amplification circuit, a controllable current overshoot suppression circuit, a voltage overshoot suppression circuit, and an RC differential sampling circuit;

[0009] Among them, the input end of the controllable current overshoot suppression circuit is connected to the source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit, and the output end of the controllable current overshoot suppression circuit is connected and converged with the output end of the current push-pull amplification circuit. The controllable current overshoot suppression circuit detects the voltage Vss of the source electrode of the SiC MOSFET U1 to be tested and generates a controllable current overshoot suppression current to converge with the output of the current push-pull amplification circuit;

[0010] The input end of the RC differential sampling circuit is connected to the drain of the SiC MOSFET U1 to be tested in the double-pulse test circuit. The output end of the RC differential sampling circuit is connected to the input end of the voltage overshoot suppression circuit. The output end of the voltage overshoot suppression circuit is connected and converged with the output end of the current push-pull amplification circuit. The voltage overshoot suppression circuit receives the sampling signal Vf output from the RC differential sampling circuit and generates a voltage overshoot suppression current to converge with the output of the current push-pull amplification circuit.

[0011] The input end of the current conversion circuit is connected to the output end of the driving voltage providing circuit. The current conversion circuit converts the driving voltage output by the driving voltage providing circuit into a driving current for output. The output end of the current conversion circuit is connected to the input end of the push-pull current amplification circuit. The push-pull current amplification circuit amplifies the driving current output by the current conversion circuit and improves its load capacity. The output end of the push-pull current amplification circuit is connected to the gate of the SiC MOSFET U1 to be tested in the double-pulse test circuit.

[0012] As a preferred technical solution of the present invention: it further includes an overvoltage protection circuit. The output end of the push-pull current amplification circuit is connected to the input end of the overvoltage protection circuit. The first control end of the overvoltage protection circuit is connected to the gate of the SiC MOSFET U1 to be tested in the double-pulse test circuit. The second control end of the overvoltage protection circuit is connected to the source of the SiC MOSFET U1 to be tested in the double-pulse test circuit.

[0013] As a preferred technical solution of the present invention: the overvoltage protection circuit includes transient voltage suppression diodes D3 and D4. Among them, the negative electrode of the transient voltage suppression diode D3 simultaneously constitutes the input end and the first control end of the overvoltage protection circuit. The positive electrode of the transient voltage suppression diode D3 is connected to the positive electrode of the transient voltage suppression diode D4. The negative electrode of the transient voltage suppression diode D4 constitutes the second control end of the overvoltage protection circuit.

[0014] As a preferred technical solution of the present invention: the controllable current overshoot suppression circuit includes an operational amplifier U4, an NPN transistor Q9, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a sliding rheostat Rc, a controllable voltage source Vc, a voltage source V11, and a diode D1. Among them, the positive pole of the controllable voltage source Vc is connected to one end of the resistor R7, the negative pole of the controllable voltage source Vc is grounded, one end of the resistor R8 forms the input end of the controllable current overshoot suppression circuit, the other end of the resistor R8, the other end of the resistor R7, and the positive input end of the operational amplifier U4 are connected together. The positive power supply terminal of the operational amplifier U4 is connected to the positive pole of the voltage source V11, the negative pole of the voltage source V11 is grounded, and the negative power supply terminal of the operational amplifier U4 is grounded; the output end of the operational amplifier U4 is connected to the base of the NPN transistor Q9 through the resistor R9, the negative input end of the operational amplifier U4 is connected to one end of the resistor R10, and the other end of the resistor R10, the emitter of the NPN transistor Q9, and one end of the sliding rheostat Rc are connected together. The other end of the sliding rheostat Rc is grounded; the collector of the NPN transistor Q9 is connected to the negative pole of the diode D1, and the positive pole of the diode D1 forms the output end of the controllable current overshoot suppression circuit.

[0015] As a preferred technical solution of the present invention: the voltage overshoot suppression circuit includes an NPN transistor Q10, a PNP transistor Q11, a PNP transistor Q12, a PNP transistor Q13, a PNP transistor Q14, a bypass control terminal power supply V8, a diode D2, a resistor R11, and a resistor R12. Among them, the negative pole of the bypass control terminal power supply V8 is grounded, the positive pole of the bypass control terminal power supply V8, the emitter of the PNP transistor Q12, and the emitter of the PNP transistor Q11 are connected together. The base of the PNP transistor Q11, the base of the PNP transistor Q12, the collector of the PNP transistor Q12, and the emitter of the PNP transistor Q13 are connected together. The base of the PNP transistor Q13, the base of the PNP transistor Q14, the collector of the PNP transistor Q14, and one end of the resistor R12 are connected together. The emitter of the PNP transistor Q14 is connected to the collector of the PNP transistor Q11. The collector of the PNP transistor Q13 is connected to the positive pole of the diode D2, and the negative pole of the diode D2 forms the output end of the voltage overshoot suppression circuit. The other end of the resistor R12 is connected to the collector of the NPN transistor Q10. The emitter of the NPN transistor Q10 is grounded, and the base of the NPN transistor Q10 is connected to one end of the resistor R11. The other end of the resistor R11 forms the input end of the voltage overshoot suppression circuit.

[0016] As a preferred technical solution of the present invention: The current push-pull amplification circuit includes an NPN transistor Q7, a PNP transistor Q8, a high-level control terminal voltage source V6, a low-level control terminal voltage source V7, a resistor R4, a resistor R5, and a resistor R6. Among them, the base of the NPN transistor Q7, the base of the PNP transistor Q8, and one end of the resistor R6 are connected together, and the connected end forms the input terminal of the current push-pull amplification circuit. The collector of the NPN transistor Q7 is connected to the positive pole of the high-level control terminal voltage source V6, the negative pole of the high-level control terminal voltage source V6 is grounded, the emitter of the NPN transistor Q7 is connected to one end of the resistor R4, the collector of the PNP transistor Q8 is connected to the positive pole of the low-level control terminal voltage source V7, the negative pole of the low-level control terminal voltage source V7 is grounded, the emitter of the PNP transistor Q8 is connected to one end of the resistor R5, and the other ends of the resistor R4, the other end of the resistor R5, and the other end of the resistor R6 are connected together to form the output terminal of the current push-pull amplification circuit.

[0017] As a preferred technical solution of the present invention: The current conversion circuit includes an NPN transistor Q1, an NPN transistor Q5, an NPN transistor Q6, a PNP transistor Q2, a PNP transistor Q3, a PNP transistor Q4, a resistor R3, a high-level control terminal voltage source V4, and a low-level control terminal voltage source V5. Among them, the emitter of the NPN transistor Q5, the emitter of the NPN transistor Q6, and the positive pole of the low-level control terminal voltage source V5 are connected together, the negative pole of the low-level control terminal voltage source V5 is grounded, and the base of the NPN transistor Q5, the base of the NPN transistor Q6, the collector of the NPN transistor Q5, and the emitter of the PNP transistor Q2 are connected together; the negative pole of the high-level control terminal voltage source V4 is grounded, the positive pole of the high-level control terminal voltage source V4, the emitter of the PNP transistor Q3, and the emitter of the PNP transistor Q4 are connected together, and the base of the PNP transistor Q3, the base of the PNP transistor Q4, the collector of the PNP transistor Q3, and the collector of the NPN transistor Q1 are connected together. The emitter of the NPN transistor Q1, the emitter of the PNP transistor Q2, and one end of the resistor R3 are connected together, the other end of the resistor R3 is grounded, the collector of the PNP transistor Q4 is connected to the collector of the NPN transistor Q6, and the connected end forms the output terminal of the current conversion circuit. The base of the NPN transistor Q1 is connected to the base of the PNP transistor Q2, and the connected end forms the input terminal of the current conversion circuit.

[0018] As a preferred technical solution of the present invention: the driving voltage providing circuit includes a driving chip U3, a control terminal voltage source V1, a high-level output control terminal voltage source V2, a low-level output control terminal voltage source V3, a resistor R1, a resistor R2, capacitors C1, C2, C3, C4, C5, and C6. Among them, one end of capacitor C1, the positive electrode of control terminal voltage source V1, and the Vdd1 terminal of driving chip U3 are connected to each other. The other end of capacitor C1, the negative electrode of control terminal voltage source V1, and the GND1 terminal of driving chip U3 are connected to each other and grounded. The negative electrode of high-level output control terminal voltage source V2 is grounded. The positive electrode of high-level output control terminal voltage source V2, one end of capacitor C2, one end of capacitor C3, and the Vdd2 terminal of driving chip U3 are connected to each other. The other end of capacitor C2 is connected to the other end of capacitor C3 and grounded. The negative electrode of low-level output control terminal voltage source V3 is grounded. The positive electrode of low-level output control terminal voltage source V3, one end of capacitor C4, one end of capacitor C5, and the GND2 terminal of driving chip U3 are connected to each other. The other end of capacitor C4 is connected to the other end of capacitor C5 and grounded. One end of resistor R1 is connected to the Vout terminal of driving chip U3. One end of resistor R2 is connected to the Vout_SRC terminal of driving chip U3. The other end of resistor R1, the other end of resistor R2, and one end of capacitor C6 are connected to each other, and the connection end constitutes the output end of the driving voltage providing circuit. The other end of capacitor C6 is grounded. The SRC terminal of driving chip U3 is grounded. The Vin terminal of driving chip U3 is externally connected to a control signal.

[0019] As a preferred technical solution of the present invention: the RC differential sampling circuit includes a capacitor C6 and a resistor R16. Among them, one end of capacitor C6 constitutes the input end of the RC differential sampling circuit. The other end of capacitor C6 is connected to one end of resistor R16, and the connection end constitutes the output end of the RC differential sampling circuit. The other end of resistor R16 is grounded.

[0020] As a preferred technical solution of the present invention: the double-pulse test circuit further includes a SiC MOSFET U2, a power supply V9, a power supply V10, a resistor R15, an inductor L1, a capacitor C7, and a temperature control power supply V12. Among them, the positive pole of the power supply V9 is connected to the gate of the SiC MOSFET U2 through the resistor R15. The negative pole of the power supply V9, the drain of the SiC MOSFET U1 to be tested, the source of the SiC MOSFET U2, and one end of the inductor L1 are connected together. The drain of the SiC MOSFET U2, the other end of the inductor L1, one end of the capacitor C7, and the positive pole of the power supply V10 are connected together. The source of the SiC MOSFET U1 to be tested, the other end of the capacitor C7, and the negative pole of the power supply V10 are connected together and grounded. The temperature control terminal of the SiC MOSFET U1 to be tested, the temperature control terminal of the SiC MOSFET U2, and the positive pole of the temperature control power supply V12 are connected together, and the negative pole of the temperature control power supply V12 is grounded.

[0021] For the SiC MOSFET active gate drive circuit based on controllable gate current of the present invention, compared with the prior art by adopting the above technical solutions, it has the following technical effects:

[0022] (1) The SiC MOSFET active gate drive circuit based on controllable gate current designed by the present invention provides a drive voltage for the SiC MOSFET U1 to be tested included in the double-pulse test circuit based on the drive voltage supply circuit. The drive voltage is converted into a drive current by the current conversion circuit and sent to the current push-pull amplification circuit. Then, based on the controllable current overshoot suppression circuit, according to the source voltage Vss of the SiC MOSFET U1 to be tested, a controllable current overshoot suppression current is generated, and the voltage overshoot suppression circuit generates a voltage overshoot suppression current according to the voltage Vf obtained by sampling the change rate of Vds by the RC differential sampling circuit. The drive current is amplified by the current push-pull amplification circuit to drive the SiC MOSFET U1 to be tested; the design realizes controllable gate current control, so that during the switching process of the SiC MOSFET U1 to be tested, it can be turned on and off orderly, and the current and voltage overshoot phenomena can be more effectively suppressed. Description of the Drawings

[0023] Figure 1 is a schematic diagram of the SiC MOSFET active gate drive circuit designed based on controllable gate current of the present invention;

[0024] Figure 2 is a schematic diagram of the comparison of the drain current (i _d ) waveforms of the CGC-AGD and CGD designed by the present invention during the turn-on stage;

[0025] Figure 3 is a schematic diagram comparing the waveforms of the drain-source voltages (V _ds ) of the designed CGC-AGD and CGD of the present invention during the turn-on stage;

[0026] Figure 4 is a partial schematic diagram comparing the waveforms of the drain-source voltages (V _ds ) of the designed CGC-AGD and CGD of the present invention during the turn-on stage;

[0027] Figure 5 is a schematic diagram comparing the waveforms of the drain currents (i_ d ) of the designed CGC-AGD and AGD of the present invention during the turn-on stage;

[0028] Figure 6 is a schematic diagram comparing the waveforms of the drain-source voltages (V_ ds ) of the designed CGC-AGD and AGD of the present invention during the turn-on stage;

[0029] Figure 7 is a partial schematic diagram comparing the waveforms of the drain-source voltages (V_ ds ) of the designed CGC-AGD and AGD of the present invention during the turn-on stage.

[0030] Among them, 1. driving voltage supply circuit, 2. current conversion circuit, 3. current push-pull amplification circuit, 4. current overshoot suppression circuit, 5. voltage overshoot suppression circuit, 6. RC differential sampling circuit, 7. overvoltage protection circuit, 8. double-pulse test circuit. Specific Embodiments

[0031] The following further elaborates on the specific embodiments of the present invention with reference to the accompanying drawings of the specification.

[0032] The present invention designs a SiC MOSFET active gate drive circuit (CGC-AGD) based on controllable gate current for driving the SiC MOSFET U1 to be tested included in the double-pulse test circuit 8, as Figure 1 shown, which includes a driving voltage supply circuit 1, a current conversion circuit 2, a current push-pull amplification circuit 3, a controllable current overshoot suppression circuit 4, a voltage overshoot suppression circuit 5, an RC differential sampling circuit 6, and an overvoltage protection circuit 7.

[0033] As Figure 1As shown, the input end of the controllable current overshoot suppression circuit 4 is connected to the source electrode of the to-be-tested SiCMOSFET U1 in the double-pulse test circuit 8. The output end of the controllable current overshoot suppression circuit 4 is connected and converged with the output end of the current push-pull amplification circuit 3. The controllable current overshoot suppression circuit 4 detects the voltage Vss of the source electrode of the to-be-tested SiC MOSFET U1 and generates a controllable current overshoot suppression current to converge with the output of the current push-pull amplification circuit 3.

[0034] As Figure 1 shown, the input end of the RC differential sampling circuit 6 is connected to the drain electrode of the to-be-tested SiC MOSFET U1 in the double-pulse test circuit 8. The output end of the RC differential sampling circuit 6 is connected to the input end of the voltage overshoot suppression circuit 5. The output end of the voltage overshoot suppression circuit 5 is connected and converged with the output end of the current push-pull amplification circuit 3. The control voltage overshoot suppression circuit 5 receives the sampling signal Vf output from the RC differential sampling circuit 6 and generates a voltage overshoot suppression current to converge with the output of the current push-pull amplification circuit 3.

[0035] As Figure 1 shown, the input end of the current conversion circuit 2 is connected to the output end of the driving voltage providing circuit 1. The current conversion circuit 2 converts the driving voltage output by the driving voltage providing circuit 1 into a driving current for output. The output end of the current conversion circuit 2 is connected to the input end of the push-pull current amplification circuit 3. The push-pull current amplification circuit 3 amplifies the driving current output by the current conversion circuit 2 and improves its load capacity. The output end of the push-pull current amplification circuit 3 is connected to the input end of the overvoltage protection circuit 7. The first control end of the overvoltage protection circuit 7 is connected to the gate electrode of the to-be-tested SiC MOSFET U1 in the double-pulse test circuit 8, and the second control end of the overvoltage protection circuit 7 is connected to the source electrode of the to-be-tested SiC MOSFET U1 in the double-pulse test circuit 8.

[0036] Regarding the practical application of the above design scheme, regarding the double-pulse test circuit 8, as Figure 1As shown in the figure, the specific design includes the SiC MOSFET U1 to be tested, SiC MOSFET U2, power supply V9, power supply V10, resistor R15, inductor L1, capacitor C7, and temperature control power supply V12. Among them, the positive pole of power supply V9 is connected to the gate of SiC MOSFET U2 through resistor R15. The negative pole of power supply V9, the drain of the SiC MOSFET U1 to be tested, the source of SiC MOSFET U2, and one end of inductor L1 are connected together. The drain of SiC MOSFET U2, the other end of inductor L1, one end of capacitor C7, and the positive pole of power supply V10 are connected together. The source of the SiC MOSFET U1 to be tested, the other end of capacitor C7, and the negative pole of power supply V10 are connected together and grounded. The temperature control terminals of the SiC MOSFET U1 to be tested, the temperature control terminal of SiC MOSFET U2, and the positive pole of the temperature control power supply V12 are connected together, and the negative pole of the temperature control power supply V12 is grounded.

[0037] Regarding the above double-pulse test circuit 8, as Figure 1 shown in the figure, for the above application circuit designed according to the present invention, a specific application design is carried out. Among them, the designed driving voltage supply circuit 1 includes a driving chip U3, a control terminal voltage source V1, a high-level output control terminal voltage source V2, a low-level output control terminal voltage source V3, resistors R1, R2, capacitors C1, C2, C3, C4, C5, C6. Among them, the driving chip U3 is specifically selected as ADuM4122 in actual application. One end of capacitor C1, the positive pole of control terminal voltage source V1, and the Vdd1 terminal of driving chip U3 are connected together. The other end of capacitor C1, the negative pole of control terminal voltage source V1, and the GND1 terminal of driving chip U3 are connected together and grounded. The negative pole of the high-level output control terminal voltage source V2 is grounded. The positive pole of the high-level output control terminal voltage source V2, one end of capacitor C2, one end of capacitor C3, and the Vdd2 terminal of driving chip U3 are connected together. The other end of capacitor C2 is connected to the other end of capacitor C3 and grounded. The negative pole of the low-level output control terminal voltage source V3 is grounded. The positive pole of the low-level output control terminal voltage source V3, one end of capacitor C4, one end of capacitor C5, and the GND2 terminal of driving chip U3 are connected together. The other end of capacitor C4 is connected to the other end of capacitor C5 and grounded. One end of resistor R1 is connected to the Vout terminal of driving chip U3. One end of resistor R2 is connected to the Vout_SRC terminal of driving chip U3. The other end of resistor R1, the other end of resistor R2, and one end of capacitor C6 are connected together, and this connected end constitutes the output terminal of the driving voltage supply circuit 1. The other end of capacitor C6 is grounded. The SRC terminal of driving chip U3 is grounded. The Vin terminal of driving chip U3 is externally connected to a control signal.

[0038] In the application of the driving voltage supply circuit 1, the driving chip U3 raises the driving signal Vin to the gate-source voltage of -5V to 20V that can drive the tube U1 to be tested, and adopts negative voltage shutdown to further avoid the mis-turn-on of the tube U1 to be tested caused by the fluctuation of the gate-source voltage (Vgs) during the turn-on and turn-off processes. Moreover, the capacitors C1, C2, C3, C4, and C5 are used as input filter capacitors to suppress the interference generated by the power supply module, and the capacitor C6 is used as an output filter capacitor to reduce the output ripple and noise caused by the internal power switch action. The driving chip U3 uses the ADuM4122 of ADI Company, which is an isolated, single-device, dual-output driver. The ADuM4122 provides true current isolation between the input and output regions. The ADuM4122 has two built-in output pins, which helps to control the slew rate of the two output driving strengths. The slew rate control can achieve electromagnetic interference (EMI) suppression and voltage overshoot control. If the internal temperature of the ADuM4122 exceeds the thermal shutdown temperature, the internal thermal shutdown will set the output to a low level.

[0039] The specific design of the current conversion circuit 2 is as Figure 1 shown, and it includes an NPN transistor Q1, an NPN transistor Q5, an NPN transistor Q6, a PNP transistor Q2, a PNP transistor Q3, a PNP transistor Q4, a resistor R3, a high-level control terminal voltage source V4, and a low-level control terminal voltage source V5. Among them, the emitter of the NPN transistor Q5, the emitter of the NPN transistor Q6, and the positive pole of the low-level control terminal voltage source V5 are connected together, the negative pole of the low-level control terminal voltage source V5 is grounded, and the base of the NPN transistor Q5, the base of the NPN transistor Q6, the collector of the NPN transistor Q5, and the emitter of the PNP transistor Q2 are connected together; the negative pole of the high-level control terminal voltage source V4 is grounded, and the positive pole of the high-level control terminal voltage source V4, the emitter of the PNP transistor Q3, and the emitter of the PNP transistor Q4 are connected together, and the base of the PNP transistor Q3, the base of the PNP transistor Q4, the collector of the PNP transistor Q3, and the collector of the NPN transistor Q1 are connected together. The emitter of the NPN transistor Q1, the emitter of the PNP transistor Q2, and one end of the resistor R3 are connected together, and the other end of the resistor R3 is grounded. The collector of the PNP transistor Q4 is connected to the collector of the NPN transistor Q6, and this connection end constitutes the output end of the current conversion circuit 2. The base of the NPN transistor Q1 is connected to the base of the PNP transistor Q2, and this connection end constitutes the input end of the current conversion circuit 2.

[0040] In the application of the current conversion circuit 2, the drive voltage at the output end of the drive voltage supply circuit 1 is converted into a drive current with high impedance. The conversion from the drive voltage to the drive current is achieved through a push-pull circuit composed of an NPN transistor Q1 and a PNP transistor Q2. The drive voltage generates a voltage drop Vbe across the NPN transistor Q1 and the PNP transistor Q2, and then it is converted into a current signal across the resistor R3. Moreover, the current signal is copied by two current mirrors composed of transistors above and below, and finally, a drive current with high impedance is provided at the output end of the current conversion circuit 2.

[0041] Regarding the controllable current overshoot suppression circuit 4, as Figure 1 shown, the specific design includes an operational amplifier U4, an NPN transistor Q9, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a potentiometer Rc, a controllable voltage source Vc, a voltage source V11, and a diode D1. Among them, in the specific application, the operational amplifier U4 uses AD8030. The positive pole of the controllable voltage source Vc is connected to one end of the resistor R7, the negative pole of the controllable voltage source Vc is grounded. One end of the resistor R8 forms the input end of the controllable current overshoot suppression circuit 4, and the other end of the resistor R8, the other end of the resistor R7, and the positive input terminal of the operational amplifier U4 are connected together. The positive power supply terminal of the operational amplifier U4 is connected to the positive pole of the voltage source V11, the negative pole of the voltage source V11 is grounded, and the negative power supply terminal of the operational amplifier U4 is grounded; the output terminal of the operational amplifier U4 is connected to the base of the NPN transistor Q9 through the resistor R9, the negative input terminal of the operational amplifier U4 is connected to one end of the resistor R10, and the other end of the resistor R10, the emitter of the NPN transistor Q9, and one end of the potentiometer Rc are connected together, and the other end of the potentiometer Rc is grounded; the collector of the NPN transistor Q9 is connected to the negative pole of the diode D1, and the positive pole of the diode D1 forms the output end of the controllable current overshoot suppression circuit 4.

[0042] The design of the controllable current overshoot suppression circuit 4, as Figure 1As shown in the figure, it is composed of an operational amplifier U4 (AD8030), an NPN transistor Q9, a sliding rheostat Rc, and other auxiliary components. The voltage input signal Vss received by the non-inverting input terminal of the operational amplifier U4 is compared with the controllable voltage source Vc. After being amplified by the operational amplifier U4 and then amplified by the NPN transistor Q9, the emitter current Ie of the NPN transistor Q9 acts on the sliding rheostat Rc. According to the properties of the operational amplifier, Ic = (Vss + Vc) / Rc. The output current is proportional to the voltage input signal Vss received by the non-inverting input terminal of the NPN transistor Q9 and the controllable voltage source Vc, and is independent of the size of the load resistance. Therefore, when the drain current overshoot of the SiC MOSFET U1 to be tested occurs, Vss increases, and the current at the output terminal of the controllable current overshoot suppression circuit 4 also increases accordingly, thus better suppressing the current overshoot phenomenon, indicating the good constant current performance of the circuit. And when the effect is still not ideal, the size of the controllable voltage source Vc can be adjusted manually, so as to increase the current at the output terminal of the controllable current overshoot suppression circuit 4, and the versatility is better. In addition, in order to obtain a good linear correspondence between input and output, special attention is paid to the selection of components, such as the resistor R7, the resistor R8, and the sliding rheostat Rc. Precision resistors or precision sliding rheostats with low temperature drift are selected to minimize the non-linear distortion of the conversion circuit to the greatest extent.

[0043] Regarding the application of the voltage overshoot suppression circuit 5, such as Figure 1 As shown in the figure, first, the RC differential sampling circuit 6 is specifically designed, including a capacitor C6 and a resistor R16. One end of the capacitor C6 constitutes the input terminal of the RC differential sampling circuit 6, the other end of the capacitor C6 is connected to one end of the resistor R16, and the connected end constitutes the output terminal of the RC differential sampling circuit 6, and the other end of the resistor R16 is grounded.

[0044] In the application, during the turn-off process of the SiC MOSFET U1 to be tested, its drain voltage Vds increases rapidly. The RC differential sampling circuit 6 samples the change rate of Vds, and there is

[0045] V f =R 16 C6(dv ds / dt)

[0046] Therefore, the voltage overshoot suppression circuit 5 controls the orderly turn-on and turn-off of the voltage overshoot suppression circuit 5 during the turn-on and turn-off stages of the SiC MOSFET U1 to be tested by detecting the change rate of the drain voltage Vds of the SiC MOSFET U1 to be tested on the RC differential sampling circuit 6, so as to reduce the overshoot of the drain voltage Vds during the turn-off process.

[0047] Then regarding the voltage overshoot suppression circuit 5, such as Figure 1As shown, the specific design includes NPN transistor Q10, PNP transistors Q11, Q12, Q13, Q14, bypass control terminal power supply V8, diode D2, resistor R11, and resistor R12. Among them, the negative pole of the bypass control terminal power supply V8 is grounded, and the positive pole of the bypass control terminal power supply V8, the emitter of PNP transistor Q12, and the emitter of PNP transistor Q11 are connected together. The base of PNP transistor Q11, the base of PNP transistor Q12, the collector of PNP transistor Q12, and the emitter of PNP transistor Q13 are connected together. The base of PNP transistor Q13, the base of PNP transistor Q14, the collector of PNP transistor Q14, and one end of resistor R12 are connected together. The emitter of PNP transistor Q14 is connected to the collector of PNP transistor Q11. The collector of PNP transistor Q13 is connected to the positive pole of diode D2, and the negative pole of diode D2 constitutes the output terminal of the voltage overshoot suppression circuit 5. The other end of resistor R12 is connected to the collector of NPN transistor Q10. The emitter of NPN transistor Q10 is grounded, the base of NPN transistor Q10 is connected to one end of resistor R11, and the other end of resistor R11 constitutes the input terminal of the voltage overshoot suppression circuit 5.

[0048] For the design of the voltage overshoot suppression circuit 5, the structure of a Wilson current mirror is adopted. An improved version of the Wilson current mirror composed of 4 PNP transistors is more suitable for high-current circuits and can significantly eliminate the problem of base current mismatch, making the output current and input current nearly the same, better regulating the bypass current, and accurately eliminating the overshoot phenomenon of the drain voltage of the SiC MOSFET U1 to be tested. And an overvoltage protection circuit 6 is introduced to limit the gate voltage of the SiC MOSFET U1 to be tested within the range of the threshold voltage to prevent the gate positive and negative surge voltages from damaging the SiC MOSFET U1 to be tested and ensure the actual driving test effect.

[0049] Furthermore, for the current push-pull amplifier circuit 3, as Figure 1As shown, the specific design includes an NPN transistor Q7, a PNP transistor Q8, a high-level control terminal voltage source V6, a low-level control terminal voltage source V7, a resistor R4, a resistor R5, and a resistor R6. Among them, the base of the NPN transistor Q7, the base of the PNP transistor Q8, and one end of the resistor R6 are connected together, and the connected end forms the input terminal of the current push-pull amplifier circuit 3. The collector of the NPN transistor Q7 is connected to the positive pole of the high-level control terminal voltage source V6, the negative pole of the high-level control terminal voltage source V6 is grounded, the emitter of the NPN transistor Q7 is connected to one end of the resistor R4, the collector of the PNP transistor Q8 is connected to the positive pole of the low-level control terminal voltage source V7, the negative pole of the low-level control terminal voltage source V7 is grounded, the emitter of the PNP transistor Q8 is connected to one end of the resistor R5, and the other ends of the resistor R4, the other end of the resistor R5, and the other end of the resistor R6 are connected together to form the output terminal of the current push-pull amplifier circuit 3.

[0050] In the application of the current push-pull amplifier circuit 3, a controllable current amplification structure is formed by a pair of push-pull complementary transistors and the resistor R6. Assuming that the voltage drop between the base and the emitter of the transistor is 0 and the base currents of the NPN transistor Q7 and the PNP transistor Q8 are 0, it can be obtained that the voltage drop across the resistor R6 is forced to pass through the on-resistance R4 and the off-resistance R5. The voltage drop across the resistor R6 is distributed by the ratio of the resistor values, and finally the gate current Ig = i6 + 2i6R6 / (R4 + R5) can be obtained, where i6 is the current flowing through the resistor R6 and ig is the current at the output terminal of the current push-pull amplifier circuit 3. By selecting appropriate values of the resistor R6, the resistor R4, and the resistor R5, the gain required by the current amplifier can be obtained.

[0051] For the overvoltage protection circuit 7, as Figure 1 shown, the specific design includes a transient voltage suppression diode D3 and a transient voltage suppression diode D4. Among them, the negative pole of the transient voltage suppression diode D3 simultaneously forms the input terminal and the first control terminal of the overvoltage protection circuit 7. The positive pole of the transient voltage suppression diode D3 is connected to the positive pole of the transient voltage suppression diode D4, and the negative pole of the transient voltage suppression diode D4 forms the second control terminal of the overvoltage protection circuit 7. Two transient voltage suppression diodes (TVS) connected in reverse series are added between the gate and the source of the SiC MOSFET U1 to be tested. Among them, the diode D3 limits the amplitude of the positive voltage, and the lower diode D4 limits the amplitude of the negative voltage, thereby limiting the gate voltage within the range of the threshold voltage and preventing the oscillation of the gate voltage from damaging the device. The overvoltage protection circuit 7 is used to limit the gate voltage of the SiC MOSFET U1 to be tested within the range of the threshold voltage to prevent the gate positive and negative surge voltages from damaging the SiC MOSFET U1 to be tested and ensure the actual driving test effect.

[0052] In the actual application of the above design solution, during the switching process of the SiC MOSFET U1 to be tested, the rate of change of the voltage drop Vss on the parasitic inductor LSS on its source electrode is proportional to the drain current id of the SiC MOSFET U1. Therefore, it is equivalent to sampling the di / dt of the drain current id as the judgment condition. The differential quantity di / dt can reflect the entry and exit of the SiC MOSFET into the current rising region and the current falling region faster than the physical quantity id.

[0053]

[0054] Therefore, the controllable current overshoot suppression circuit 4 controls the turning on and off of the controllable current overshoot suppression circuit 4 by detecting the voltage drop Vss on the source inductor LSS of the SiC MOSFET U1 to be tested. Thus, when the drain current overshoot of the SiC MOSFET U1 to be tested occurs, Vss increases, and the current at the output end of the controllable current overshoot suppression circuit 4 also increases accordingly, thereby better suppressing the current overshoot phenomenon, indicating the good constant current performance of the circuit. And when the effect is still not ideal, the magnitudes of the controllable voltage source Vc and the sliding rheostat Rc can be adjusted manually to increase the current magnitude at the output end of the controllable current overshoot suppression circuit 4, with better versatility.

[0055] During the actual application process, as Figure 2 shown, compared with the ordinary gate drive circuit (CGD), the design solution of the present invention enables a lower current overshoot of the drain current Id of the SiC MOSFET U1 to be tested during the turn-on stage. The drain current overshoot changes from 27.43 A to 8.34 A, and the current overshoot is reduced by approximately 70%; as Figure 3 、 Figure 4 shown, compared with the ordinary gate drive circuit (CGD), the design solution of the present invention enables a lower voltage overshoot of the drain-source voltage Vds of the SiC MOSFET U1 to be tested during the turn-off stage. The drain-source voltage overshoot changes from 62.34 V to 48.53 V, and the voltage overshoot is reduced by approximately 22%; as Figure 5 shown, compared with the active gate drive circuit (AGD), the design solution of the present invention enables a lower current overshoot of the drain current Id of the SiC MOSFET U1 to be tested during the turn-on stage. The drain current overshoot changes from 15 A to 8.34 A, and the current overshoot is reduced by approximately 44%; as Figure 6 、 Figure 7As shown, compared with the active gate drive circuit (CGD), the design solution of the present invention results in a lower voltage overshoot of the drain-source voltage Vds of the SiC MOSFET U1 under test during the turn-off phase. The voltage overshoot of the drain-source voltage decreases from 59.79V to 48.53V, a reduction of approximately 19%. That is, by controlling the change of the gate current through the controllable current overshoot suppression circuit 4 and the voltage overshoot suppression circuit 5, the gate current is cut in and extracted during the turn-on and turn-off processes to slow down the voltage and current overshoot phenomena during the switching process. Moreover, the compensation current provided by the controllable current overshoot suppression circuit 4 can not only be controlled by artificially adjusting the values of the controllable voltage source Vc and the sliding rheostat Rc, but also adaptively change the current magnitude with the change of Vss, making it more versatile. The voltage overshoot suppression circuit 5 uses a modified Wilson current mirror composed of 4 PNP transistors, which significantly eliminates the problem of base current mismatch, making the output current and the input current nearly the same, better regulating the bypass current, and precisely eliminating the overshoot phenomenon of the drain voltage of the SiC MOSFET U1 under test.

[0056] The present invention is directed to the SiC MOSFET U1 under test included in the double-pulse test circuit 8. Based on the driving voltage provided by the driving voltage supply circuit 1, the driving voltage is converted into a driving current by the current conversion circuit 2 and sent to the current push-pull amplification circuit 3. Then, based on the source voltage Vss of the SiC MOSFET U1 under test, the controllable current overshoot suppression circuit 4 generates a controllable current overshoot suppression current, and the voltage overshoot suppression circuit 5 generates a voltage overshoot suppression current based on the voltage Vf obtained by sampling the change rate of Vds by the RC differential sampling circuit 6. The driving current is amplified by the current push-pull amplification circuit 3 to drive the SiC MOSFET U1 under test. The design solution realizes controllable gate current control, so that during the switching process of the SiC MOSFET U1 under test, it can be turned on and off orderly, and more effectively suppress the current and voltage overshoot phenomena.

[0057] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those of ordinary skill in the art, various changes can be made without departing from the gist of the present invention.

Claims

1. A SiC MOSFET active gate drive circuit based on controllable gate current, used for driving a SiC MOSFET U1 to be tested included in a double pulse test circuit (8), characterized in that: It comprises a driving voltage supply circuit (1), a current conversion circuit (2), a current push-pull amplifier circuit (3), a controllable current overshoot suppression circuit (4), a voltage overshoot suppression circuit (5), and an RC differential sampling circuit (6); The input end of the controllable current overshoot suppression circuit (4) is connected to the source of the SiC MOSFET U1 to be tested in the double pulse test circuit (8), and the output end of the controllable current overshoot suppression circuit (4) is connected to the output end of the current push-pull amplifier circuit (3) for convergence. The controllable current overshoot suppression circuit (4) detects the voltage Vss of the source of the SiC MOSFET U1 to be tested, and generates a controllable current overshoot suppression current for convergence with the output of the current push-pull amplifier circuit (3); The input end of the RC differential sampling circuit (6) is connected to the drain of the SiC MOSFET U1 to be tested in the double pulse test circuit (8), the output end of the RC differential sampling circuit (6) is connected to the input end of the voltage overshoot suppression circuit (5), the output end of the voltage overshoot suppression circuit (5) is connected to the output end of the current push-pull amplifier circuit (3), and the voltage overshoot suppression circuit (5) is controlled to receive the sampling signal Vf output from the RC differential sampling circuit (6), and generate a voltage overshoot suppression current to be converged with the output of the current push-pull amplifier circuit (3); The input end of the current conversion circuit (2) is connected to the output end of the driving voltage providing circuit (1), and the current conversion circuit (2) converts the driving voltage output by the driving voltage providing circuit (1) into a driving current for output; the output end of the current conversion circuit (2) is connected to the input end of the push-pull current amplifier circuit (3), and the push-pull current amplifier circuit (3) amplifies the driving current output by the current conversion circuit (2) and improves its load capacity; the output end of the push-pull current amplifier circuit (3) is connected to the gate of the SiC MOSFET U1 to be tested in the double pulse test circuit (8).

2. The SiC MOSFET active gate drive circuit based on controllable gate current according to claim 1, characterized in that: It also includes an overvoltage protection circuit (7), wherein the output end of the push-pull current amplifier circuit (3) is connected to the input end of the overvoltage protection circuit (7), the first control end of the overvoltage protection circuit (7) is connected to the gate of the SiCMOSFET U1 to be tested in the double pulse test circuit (8), and the second control end of the overvoltage protection circuit (7) is connected to the source of the SiCMOSFET U1 to be tested in the double pulse test circuit (8).

3. The SiC MOSFET active gate drive circuit based on controllable gate current according to claim 2, characterized in that: The overvoltage protection circuit (7) comprises a transient voltage suppression diode D3 and a transient voltage suppression diode D4, wherein the cathode of the transient voltage suppression diode D3 simultaneously constitutes the input terminal and the first control terminal of the overvoltage protection circuit (7), the anode of the transient voltage suppression diode D3 is connected to the anode of the transient voltage suppression diode D4, and the cathode of the transient voltage suppression diode D4 constitutes the second control terminal of the overvoltage protection circuit (7).

4. The SiC MOSFET active gate drive circuit based on controllable gate current according to claim 1, characterized in that: The controllable current overshoot suppression circuit (4) comprises an operational amplifier U4, an NPN transistor Q9, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a sliding rheostat Rc, a controllable voltage source Vc, a voltage source V11, and a diode D1, wherein the positive electrode of the controllable voltage source Vc is connected to one end of the resistor R7, the negative electrode of the controllable voltage source Vc is grounded, one end of the resistor R8 constitutes the input end of the controllable current overshoot suppression circuit (4), the other end of the resistor R8, the other end of the resistor R7, and the positive input end of the operational amplifier U4 are connected, and the positive power supply end of the operational amplifier U4 is connected to the positive power supply end of the operational amplifier U4. The positive electrode of the voltage source V11 is connected, the negative electrode of the voltage source V11 is grounded, and the negative power supply terminal of the operational amplifier U4 is grounded; the output end of the operational amplifier U4 is connected to the base of the NPN transistor Q9 through the resistor R9, the negative input end of the operational amplifier U4 is connected to one end of the resistor R10, the other end of the resistor R10, the emitter of the NPN transistor Q9, and one end of the sliding resistor Rc are connected, and the other end of the sliding resistor Rc is grounded; the collector of the NPN transistor Q9 is connected to the negative electrode of the diode D1, and the positive electrode of the diode D1 constitutes the output end of the controllable current overshoot suppression circuit (4).

5. The SiC MOSFET active gate drive circuit based on controllable gate current according to claim 1, characterized in that: The voltage overshoot suppression circuit (5) comprises an NPN transistor Q10, a PNP transistor Q11, a PNP transistor Q12, a PNP transistor Q13, a PNP transistor Q14, a bypass control end power supply V8, a diode D2, a resistor R11, and a resistor R12, wherein the negative electrode of the bypass control end power supply V8 is grounded, the positive electrode of the bypass control end power supply V8, the emitter of the PNP transistor Q12, and the emitter of the PNP transistor Q11 are connected, the base of the PNP transistor Q11, the base of the PNP transistor Q12, the collector of the PNP transistor Q12, and the emitter of the PNP transistor Q13 are connected, and the PNP transistor The base of Q13, the base of the PNP transistor Q14, the collector of the PNP transistor Q14, and one end of the resistor R12 are connected, the emitter of the PNP transistor Q14 is connected to the collector of the PNP transistor Q11, the collector of the PNP transistor Q13 is connected to the anode of the diode D2, the cathode of the diode D2 constitutes the output end of the voltage overshoot suppression circuit (5), the other end of the resistor R12 is connected to the collector of the NPN transistor Q10, the emitter of the NPN transistor Q10 is grounded, the base of the NPN transistor Q10 is connected to one end of the resistor R11, and the other end of the resistor R11 constitutes the input end of the voltage overshoot suppression circuit (5).

6. The SiC MOSFET active gate drive circuit based on controllable gate current according to claim 1, characterized in that: The current push-pull amplifier circuit (3) comprises an NPN transistor Q7, a PNP transistor Q8, a high-level control terminal voltage source V6, a low-level control terminal voltage source V7, a resistor R4, a resistor R5, and a resistor R6, wherein the base of the NPN transistor Q7, the base of the PNP transistor Q8, and one end of the resistor R6 are connected, and the connected end constitutes the input end of the current push-pull amplifier circuit (3), and the collector of the NPN transistor Q7 is connected to the positive electrode of the high-level control terminal voltage source V6. The negative electrode of the high-level control terminal voltage source V6 is grounded, the emitter of the NPN transistor Q7 is connected to one end of the resistor R4, the collector of the PNP transistor Q8 is connected to the positive electrode of the low-level control terminal voltage source V7, the negative electrode of the low-level control terminal voltage source V7 is grounded, the emitter of the PNP transistor Q8 is connected to one end of the resistor R5, and the other end of the resistor R4, the other end of the resistor R5, and the other end of the resistor R6 are connected to form the output end of the current push-pull amplifier circuit (3).

7. The SiC MOSFET active gate drive circuit based on controllable gate current according to claim 1, characterized in that: The current conversion circuit (2) comprises an NPN transistor Q1, an NPN transistor Q5, an NPN transistor Q6, a PNP transistor Q2, a PNP transistor Q3, a PNP transistor Q4, a resistor R3, a high-level control terminal voltage source V4, and a low-level control terminal voltage source V5, wherein the emitter of the NPN transistor Q5, the emitter of the NPN transistor Q6, and the positive electrode of the low-level control terminal voltage source V5 are connected, the negative electrode of the low-level control terminal voltage source V5 is grounded, the base of the NPN transistor Q5, the base of the NPN transistor Q6, the collector of the NPN transistor Q5, and the emitter of the PNP transistor Q2 are connected; the negative electrode of the high-level control terminal voltage source V4 is grounded, and the high-level control terminal voltage source V5 is grounded. The positive electrode of V4, the emitter of the PNP transistor Q3, and the emitter of the PNP transistor Q4 are connected; the base of the PNP transistor Q3, the base of the PNP transistor Q4, the collector of the PNP transistor Q3, and the collector of the NPN transistor Q1 are connected; the emitter of the NPN transistor Q1, the emitter of the PNP transistor Q2, and one end of the resistor R3 are connected; the other end of the resistor R3 is grounded; the collector of the PNP transistor Q4 is connected to the collector of the NPN transistor Q6, and the connected ends constitute the output end of the current conversion circuit (2); the base of the NPN transistor Q1 is connected to the base of the PNP transistor Q2, and the connected ends constitute the input end of the current conversion circuit (2).

8. The SiC MOSFET active gate drive circuit based on controllable gate current according to claim 1, characterized in that: The driving voltage providing circuit (1) comprises a driving chip U3, a control end voltage source V1, a high level output control end voltage source V2, a low level output control end voltage source V3, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, and a capacitor C6, wherein one end of the capacitor C1, a positive electrode of the control end voltage source V1, and a Vdd1 end of the driving chip U3 are connected, the other end of the capacitor C1, a negative electrode of the control end voltage source V1, and a GND1 end of the driving chip U3 are connected and grounded, the negative electrode of the high level output control end voltage source V2 is grounded, the positive electrode of the high level output control end voltage source V2, one end of the capacitor C2, one end of the capacitor C3, and a Vdd2 end of the driving chip U3 are connected, and the other end of the capacitor C2 is connected to the The other end of the capacitor C3 is connected and grounded, the negative electrode of the low-level output control terminal voltage source V3 is grounded, the positive electrode of the low-level output control terminal voltage source V3, one end of the capacitor C4, one end of the capacitor C5, and the GND2 terminal of the driving chip U3 are connected, the other end of the capacitor C4 is connected to the other end of the capacitor C5 and grounded, one end of the resistor R1 is connected to the Vout terminal of the driving chip U3, one end of the resistor R2 is connected to the Vout_SRC terminal of the driving chip U3, the other end of the resistor R1, the other end of the resistor R2, and one end of the capacitor C6 are connected, and the connected ends constitute the output end of the driving voltage providing circuit (1), the other end of the capacitor C6 is grounded, the SRC terminal of the driving chip U3 is grounded, and the Vin terminal of the driving chip U3 is externally connected to the control signal.

9. The SiC MOSFET active gate drive circuit based on controllable gate current according to claim 1, characterized in that: The RC differential sampling circuit (6) comprises a capacitor C6 and a resistor R16, wherein one end of the capacitor C6 constitutes an input end of the RC differential sampling circuit (6), the other end of the capacitor C6 is connected to one end of the resistor R16, and the connected ends constitute an output end of the RC differential sampling circuit (6), and the other end of the resistor R16 is grounded.

10. The SiC MOSFET active gate drive circuit based on controllable gate current according to claim 1, characterized in that: The double pulse test circuit (8) further comprises a SiC MOSFET U2, a power supply V9, a power supply V10, a resistor R15, an inductor L1, a capacitor C7, and a temperature control power supply V12, wherein the positive electrode of the power supply V9 ​​is connected to the gate of the SiC MOSFET U2 via the resistor R15, the negative electrode of the power supply V9, the drain of the SiC MOSFET U1 to be tested, the source of the SiC MOSFET U2, and one end of the inductor L1 are connected, the drain of the SiC MOSFET U2, the other end of the inductor L1, one end of the capacitor C7, and the positive electrode of the power supply V10 are connected, the source of the SiC MOSFET U1 to be tested, the other end of the capacitor C7, and the negative electrode of the power supply V10 are connected and grounded, the temperature control end of the SiC MOSFET U1 to be tested, the temperature control end of the SiC MOSFET U2, and the positive electrode of the temperature control power supply V12 are connected, and the negative electrode of the temperature control power supply V12 is grounded.

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