PCIe link status detection method for server and server

Abstract

Compared with the prior art, the present application provides a method and server for detecting the PCIe link status of a server, by recording the fault information of the faulty device in the power-on self-test phase; and in the operation phase of the server, a link monitoring tree of the PCIe link is established, and the link information of the link monitoring tree is obtained using multiple data channels. Based on the above link information, the link status of the link monitoring tree is judged, and the faulty device in the operation phase of the server's operating system is determined. According to the device identification of the faulty device in the power-on self-test phase and the operation phase of the server's operating system, an alarm message is sent to the processor, and a self-healing instruction is sent to the faulty device. Complex monitoring alarms and recovery strategies are implemented, and the stability of the system is avoided. At the same time, the high-performance interface provided by the support module is avoided, and the multi-level detection of the PCIe link will not generate missed alarms, which can help customers detect the PCIe link of the server more accurately and precisely.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to a PCIe link status detection method for a server and a server. Background Art

[0002] In order to meet the growing demand for computing resources and storage space, servers often need to be configured with more PCIe devices and multiple PCIe device levels. During the power-on self-test phase, the server will initialize each PCIe device and establish a PCIe link based on the above PCIe devices. In order to promptly discover and resolve potential failures of the above PCIe links, the server's BMC needs to be able to monitor the operating status of the PCIe link in real time.

[0003] The existing PCIe link detection method usually sets a register to monitor the speed status of the PCIe device, and continuously monitors the registers corresponding to all PCIe devices during the system operation phase through the BIOS (Basic Input / Output System). If the value of the register changes, it will be reported to the BMC (Baseboard Management Controller) according to the pre-saved related PCIe information. The BMC obtains the alarm log based on the reported PCIe information for the client to query.

[0004] Due to the limited resources and insufficient compatibility within the BIOS, it is impossible to monitor the increasingly complex PCIe link hierarchy and high-performance modules in the server. At the same time, the BIOS can only detect the PCIe link through the registers provided by each PCIe device. Therefore, the above PCIe link detection method cannot ensure timely discovery and resolution of potential PCIe link failures. Summary of the invention

[0005] In view of the problem that the correctness and accuracy of PCIe link detection in the prior art are insufficient, an embodiment of the present invention provides a method for detecting the PCIe link status of a server and a server.

[0006] In a first aspect, an embodiment of the present application provides a PCIe link status detection and alarm method for a server.

[0007] The method is characterized in that the server includes a processor, a PCIe link connected to the processor, and a first baseboard controller, the PCIe link includes multiple PCIe devices, the processor is connected to the first baseboard controller, and the method is used for the first baseboard controller, including: the server includes a processor, a PCIe link connected to the processor, and a first baseboard controller, the PCIe link includes multiple PCIe devices, the processor is connected to the first baseboard controller, and the method is used for the first baseboard controller, including: obtaining device information of multiple PCIe devices, determining a link monitoring tree of the PCIe link according to the device information; determining multiple monitoring nodes in the link monitoring tree, obtaining link information of multiple monitoring nodes; each monitoring node in the multiple monitoring nodes corresponds to a PCIe device; determining a faulty device in the PCIe link according to the link information of the multiple monitoring nodes. In this way, the PCIe link detection method can realize complex monitoring alarms and recovery strategies, and avoid affecting the stability of the system. At the same time, it supports the high-performance interface provided by the module, and does not generate missed alarms through multi-level detection of the PCIe link, which can help customers detect the PCIe link of the server more accurately and precisely.

[0008] In some embodiments, determining multiple monitoring nodes in the link monitoring tree also includes: monitoring the PCIe link during the BIOS power-on self-test phase to obtain fault information of the PCIe link; determining multiple monitoring nodes in the link monitoring tree includes: determining multiple monitoring nodes in the link monitoring tree based on the fault information. In this way, based on the above multiple monitoring nodes, the first baseboard management controller can monitor the faulty devices in the PCIe link establishment process and the training process through out-of-band management, and no missed alarms will be generated.

[0009] In some embodiments, according to the link information of multiple monitoring nodes, the faulty device in the PCIe link is determined, and then the following is included: outputting alarm information for the faulty device and sending a self-healing instruction to the faulty device. In this way, by providing monitoring alarm information to the client, the client can be helped to detect the PCIe link of the server. At the same time, the self-healing instruction can be sent to the faulty device to provide the client with a recovery strategy for the PCIe link of the server.

[0010] In some embodiments, the first baseboard management controller is connected to the processor via the first bus, and obtaining the device information of the multiple PCIe devices includes obtaining the device information of the multiple PCIe devices from the processor via the first bus. In this way, the first baseboard controller does not need to configure additional resources, and can obtain the device information of multiple node devices from the processor to generate a link monitoring tree through out-of-band management, without affecting the in-band service of the server.

[0011] In some embodiments, obtaining link information of multiple monitoring nodes includes: obtaining link information of multiple monitoring nodes from a processor via a first bus. In this way, the first baseboard controller does not need to configure additional resources, and can obtain link information of multiple monitoring nodes from the processor via out-of-band management, and actively initiate detection of PCIe links without affecting in-band services of the server.

[0012] In some embodiments, the server further includes a management chip, the management chip is connected to the processor, and the first baseboard management controller is connected to the management chip via a second bus, wherein obtaining device information of multiple PCIe devices includes obtaining device information of multiple PCIe devices from the management chip via the second bus. In this way, the first baseboard controller does not need to configure additional resources, and can obtain device information of multiple node devices from the management chip to generate a link monitoring tree through out-of-band management, and actively initiate detection of PCIe links without affecting the in-band services of the server.

[0013] In some embodiments, obtaining link information of multiple monitoring nodes further includes: obtaining link information of multiple monitoring nodes from a management chip through a second bus. In this way, the first baseboard controller does not need to configure additional resources, and can obtain link information of multiple monitoring nodes from the management chip through out-of-band management, and actively initiate detection of PCIe links without affecting the in-band services of the server.

[0014] In some embodiments, the server also includes a first board, a PCIe device and a second baseboard controller are arranged on the first board, the PCIe device is connected to the second baseboard controller, and the second baseboard controller is connected to the interface of the first baseboard controller through a first interface. The method for obtaining link information also includes: obtaining link information of the PCIe device from the second baseboard controller through the first interface. In this way, the link information of all monitoring nodes on the first board is directly obtained through the first interface provided by the second baseboard controller, so as to more accurately detect the link status of multiple node devices of the first board. When the PCIe link includes multiple boards, the first baseboard controller can establish communication with the baseboard management controller on each board through the respective high-performance interfaces provided by the multiple boards, and obtain the link information of all root nodes and leaf nodes on any board.

[0015] In some embodiments, the link information includes the expected value and current value of the device rate of multiple PCIe devices. According to the link information of multiple monitoring nodes, the faulty device in the PCIe link is determined, including: judging the link status of the first PCIe device according to the link information of the device rate of the first PCIe device; the first PCIe device includes the PCIe device on any node except the root node among the multiple monitoring nodes; if the expected value of the device rate of the first PCIe device is less than the current value, then the first PCIe device is determined to be the faulty device in the PCIe link. In this way, it can help customers detect the PCIe link more accurately.

[0016] In some embodiments, determining the faulty device in the PCIe link based on the link information of multiple monitoring nodes also includes: if the device rate of the first PCIe device is consistent with the expected value, judging the link status of the first PCIe device based on the current value of the device rate of the second PCIe device; the second PCIe device is any bridge device upstream of the first PCIe device; if the current value of the device rate of the second PCIe device is less than the current value of the device rate of the first PCIe device, then determining the first PCIe device as the faulty device in the PCIe link. In this way, the link status of the terminal PCIe device in the multi-level PCIe link scenario can be accurately judged based on the generated PCIe link monitoring tree, avoiding missed alarms in PCIe link detection.

[0017] On the other hand, an embodiment of the present application provides a server, including a memory and a processor, wherein the memory stores a computer program that can be executed on the processor, and is characterized in that the above-mentioned PCIe link detection method is implemented when the processor executes the computer program.

[0018] Compared with the prior art, the PCIe link detection method provided by the present application records the fault information of the faulty device in the power-on self-test phase; and in the server operation phase, establishes a link monitoring tree of the PCIe link, and uses multiple data channels to obtain the link information of the link monitoring tree. Based on the above link information, the link status of the link monitoring tree is judged, the faulty device in the operating system operation phase of the server is determined, and according to the device identification of the faulty device in the power-on self-test phase and the operating system operation phase of the server, an alarm message is sent to the processor, and a self-healing instruction is sent to the faulty device. Complex monitoring alarms and recovery strategies are implemented, and the stability of the system is avoided. At the same time, the high-performance interface provided by the support module is avoided, and the multi-level detection of the PCIe link will not generate missed alarms, which can help customers detect the PCIe link of the server more accurately and precisely. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1It is a connection diagram of a PCIe link of a server provided in an embodiment of the present application;

[0020] Figure 2 is a module diagram of a first baseboard management controller firmware program;

[0021] Figure 3 is a schematic diagram of obtaining device information of multiple PCIe devices in a PCIe link through a processor;

[0022] Figure 4a is a schematic diagram of obtaining link information of a first bridge device in a PCIe link through a processor;

[0023] Figure 4b A schematic diagram of obtaining link information of a PCIe device on a first board through a first interface;

[0024] Figure 5 It is a flow chart of a PCIe link detection method of a server provided in an embodiment of the present application;

[0025] Figure 6 It is a schematic diagram of a link monitoring tree established based on device information of multiple PCIe devices in a PCIe link;

[0026] Figure 7 It is a schematic diagram of obtaining link information of a monitoring node of a link monitoring tree;

[0027] Figure 8 It is a schematic diagram for judging the link status of the link monitoring tree;

[0028] Fig. 9 It is a schematic diagram of the structure of the server provided in the embodiment of the present application. DETAILED DESCRIPTION

[0029] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0030] In order to facilitate understanding of the technical solution of the present application, the relevant terms involved in this article are explained below.

[0031] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard that is designed to replace the old PCI, PCI-x and AGP bus standards. It is a universal motherboard interface for personal computer graphics cards, sound cards, hard drives, host adapters, solid-state drives, Wi-Fi and Ethernet hardware connections. In an embodiment of the present application, a bus based on the above-mentioned PCIe protocol is used to connect a processor and multiple PCIe devices at multiple levels. The PCIe device includes a PCIe bridge device and a PCIe terminal device. The PCIe bridge device is typically a PCIe expansion chip, an NVMe expansion chip, and a SATA expansion chip, etc.; the PCIe terminal device is typically a graphics card, a network adapter, a sound card, a storage controller card, a USB expansion card, a parallel port card, a video capture card, a TV tuner card encryption card, a GPU, and a DPU, etc.

[0032] In order to meet the growing demand for computing resources and storage space, servers often need to be configured with more PCIe devices and multiple PCIe device levels. During the power-on self-test phase, the server will initialize each PCIe device and establish a PCIe link based on the above PCIe devices. In order to promptly discover and resolve potential failures of the above PCIe links, the server's BMC needs to be able to monitor the operating status of the PCIe link in real time.

[0033] In some implementations, a register for monitoring its own speed status is usually set in the PCIe device. The BIOS (Basic Input / Output System) continuously monitors the registers corresponding to all PCIe devices during the system operation phase. If the value of the register changes, it is reported to the BMC based on the pre-saved related PCIe information. The BMC obtains the alarm log based on the reported PCIe configuration information for the client to query.

[0034] If BIOS uses background tasks to detect the PCIe link of the above registers, it will occupy additional resources. The size of the BIOS program is strictly limited. The size limit of the traditional BIOS program (commonly called Legacy BIOS) is between 16KB and 2MB. Due to limited resources, the BIOS monitoring function is relatively elementary and simple, and it is difficult to handle the complex PCIe link layer.

[0035] The server is also equipped with an independent high-performance module. The high-performance module usually includes an internal circuit and a BMC. The internal circuit is used to monitor the status of the PCIe device of the module itself, and the BMC is used to provide a high-performance interface. The server can query the status of the PCIe device on the high-performance module through the high-performance interface. Due to the limitations of the BIOS functions and extended functions, the high-performance interface cannot be supported.

[0036] For the above-mentioned usage scenarios with high computing resource requirements and storage space, the server usually has a multi-level PCIe topology structure. Detecting the link status of a single PCIe device in the PCIe link through BIOS cannot fully represent the actual link status of the PCIe device.

[0037] In some implementations, an upstream PCIe bridge device (PCIe Switch) mounts a GPU card in a high-performance module, wherein the expected values ​​of the PCIe bridge device and the GPU card are both x16, 32gt / s.

[0038] If a PCIe bridge device fails and the actual link rate and bandwidth detected are x8, 16gt / s, which are lower than the expected values, the link rate and bandwidth that the PCIe bridge device can provide to the downstream GPU card can only be x8, 16gt / s. In this case, the actual link rate and bandwidth of the GPU card will inevitably be lower than the expected values ​​and will also be in a faulty state.

[0039] At this time, when the GPU card is tested alone, if the link rate obtained is x16, 32gt / s, which meets the expected value, the BIOS will still determine that the GPU card is in a normal state. Therefore, the existing PCIe link detection may miss detection.

[0040] Real-time monitoring of the PCIe link of a server cannot ensure timely discovery and resolution of potential PCIe link failures. An embodiment of the present application provides a method for detecting the PCIe link status of a server and a server.

[0041] In order to facilitate understanding of the technical solution of the present application, the application scenario of the PCIe link status detection method is first introduced below.

[0042] For example, Figure 1 FIG. 1 shows a schematic diagram of a PCIe link connection of a server provided in an embodiment of the present application. Figure 1 As shown, the server 100 includes a processor 11, a management chip (Management Engine) 12, a first baseboard management controller 13, and a PCIe link connected to the processor.

[0043] The processor 11 is connected to the first baseboard controller 13 via a PECI bus (first bus). The processor 11 is used to obtain device identifications of multiple PCIe devices in the PCIe link and link information of the multiple PCIe devices, and send the device information and link information of the multiple PCIe devices to the first baseboard management controller 13.

[0044] PECI (Platform Environment Control Interface) is an interface standard for managing and monitoring processors and their surrounding environment. PECI is usually used for the system's baseboard management controller or other devices to communicate with the processor to obtain information about the processor's working environment, such as temperature, voltage, power consumption and other data. In the embodiment of the present application, the PECI bus based on the above protocol is used to build the communication between the baseboard management controller and the processor of the server.

[0045] In some implementations, the device information includes the vendor identification (Vendor ID), device identification, secondary bus (SECBUS, Secondary Bus), subbus (SUBBUS) and header type identification (HeaderType) of each PCIe device. The above device information is usually stored in the configuration space of the PCIe device.

[0046] Configuration space, an address space with a specific record structure or model in the register of a PCIe device, which records the vendor identification (Vendor ID), device identification (SBDF, Segment, Bus, Device, Function, logical segment number, bus number, device number, function number), secondary bus, sub-bus, header type identification of the PCIe device, and the actual link rate and bandwidth when the PCIe device is running. Through the configuration space, the configuration of the PCIe device can be understood, and then the device can be controlled.

[0047] The vendor identification mark (Vendor ID) is used to indicate the manufacturer of the PCIe device and can be used for the in-place detection of the PCIe device. When this field is not "FFFF", it indicates that the PCIe device is in-place.

[0048] Secondary Bus (SECBUS) The minimum PCIe bus number to which the downstream PCIe device is connected, usually stored independently at an address specified in the configuration space of the PCIe bridge device.

[0049] Subbus (SUBBUS), the maximum PCIe bus number connected downstream of the PCIe bridge device, is usually stored independently at an address specified in the configuration space of the PCIe bridge device.

[0050] The header type identifier (Header Type) is used to indicate the layout type of the second part of the configuration space header area and whether the specified device contains multiple functions. Among them, bit 6 is used to identify the bridge device. When bit 6 is 0, it indicates that the PCIe device is a PCIe terminal device, and when bit 6 is 1, it indicates that the PCIe device is a PCIe bridge device; bit 7 is used to identify the multi-function device. When bit 7 is 0, it indicates that the PCIe device is a single-function device, and when bit 7 is 1, it indicates that the PCIe device is a PCIe multi-function device. The header type field is usually stored independently at a specified address in the configuration space of the PCIe device.

[0051] The management chip 12 is connected to the first baseboard controller 13 through the SMLink bus (second bus), and is electrically connected to the processor 11. The management chip is used to provide another data channel, obtain the device identifications of multiple PCIe devices in the PCIe link and the link information of the multiple PCIe devices through the processor 11, and send the device identifications and link information of the multiple PCIe devices to the first baseboard management controller 13.

[0052] SMLink (System Management Link) is a dedicated communication connection or protocol used to manage, monitor or configure a computer system, network device or server. SMLink is typically used to remotely manage systems for diagnosis, performance monitoring, device configuration or other management tasks. In an embodiment of the present application, the SMLink bus based on the above protocol is used to build communication between the baseboard management controller and the management chip of the server.

[0053] By way of example and not limitation, the PCIe link status detection method provided in the embodiment of the present application may use a BMC that can be a CPU (central processing unit) of an ARM architecture, or a processor implemented in any of a DPU (Data Processing Unit) and a FPGA (Field-Programmable Gate Array).

[0054] By way of example and not limitation, the management chip 12 used in the PCIe link status detection method provided in the embodiment of the present application can also be replaced by a CPLD (Complex Programmable Logic Device), or a programmable component implemented by any of FPGA and MCU (Micro Control Unit).

[0055] Please continue reading Figure 1 The PCIe link includes multiple PCIe devices distributed in the 1st to N+1th device levels, the PCIe devices include bridge devices and PCIe terminal devices, the bridge devices include PCIe extension chips and NVMe extension chips, and the PCIe terminal devices include PCIe cards and terminal devices.

[0056] The upstream port 1 of the first-level PCIe expansion chip 20 in the PCIe link is used to connect to the root port 1 of the processor 11, its downstream port 2 is used to connect to the next-level PCIe expansion chip, and its downstream port 3 is used to connect to the upstream port 1 of the first PCIe card 21.

[0057] The upstream port 1 of the Nth level PCIe expansion chip 30 in the PCIe link is used to connect to the downstream port of the previous level PCIe expansion chip, its downstream port 2 and downstream port 3 are used to connect to the PCIe device on the first board 41, and its downstream port 4 is used to connect to the upstream port 1 of the second PCIe card 42.

[0058] The first board 41 is provided with an NVMe expansion chip 411, a terminal device 412, a second baseboard controller 413 and a first interface 414.

[0059] The upstream port 1 of the NVMe expansion chip 411 is used to connect to the downstream port 2 of the N-th level PCIe expansion chip 30, its downstream port 2 is used to connect to NVMe1, and its downstream port 3 is used to connect to NVMe2.

[0060] The uplink port 2 of the terminal device 412 is used to connect to the uplink port 3 of the Nth level PCIe expansion chip 30 .

[0061] The second baseboard controller 413 is connected to the NVMe extension chip 411 and to the terminal device 412. The interface 1 (first interface) of the second baseboard controller 413 is connected to the interface 1 of the first baseboard controller 13, and is used to send the acquired link information of the NVMe extension chip 411 and the terminal device 412 to the first baseboard controller 13 through the first interface 414.

[0062] By way of example and not limitation, the first board 41 in the embodiment of the present application may be the aforementioned high-performance module, such as an AI module and a DPU module, or may be any board including a PCIe expansion board. It is understandable that the terminal device mounted on the first board may be any PCIe component such as a GPU and an NV Switch, and the first interface is any interface of a USB, an IIC and an out-of-band communication protocol such as Redfish and IPMI provided by the second baseboard controller. In other words, the embodiment of the present application does not limit the first board, the terminal device and the terminal bridge device on the first board, and the specific type of the first interface provided by the first board.

[0063] By way of example and not limitation, the PCIe link status detection method provided in the embodiment of the present application may use a first baseboard management controller and a second baseboard management controller that are replaced by a CPLD (Complex Programmable Logic Device), or a programmable component implemented by using either an FPGA or an MCU (Micro Control Unit).

[0064] For example, Figure 2 FIG. 4 shows a schematic diagram of a software module of a first baseboard management controller. Figure 2 As shown, the software modules of the first baseboard management control 13 include a link anomaly detection module 131 , a link monitoring tree initialization module 132 , a link information monitoring module 133 , a link status judgment module 134 and a link anomaly processing module 135 .

[0065] The link anomaly detection module 131 is used to monitor the PCIe link during the power on self-test (POST) on the server to obtain fault information of faulty devices during the PCIe link establishment process and training process.

[0066] When the operating system of the server is running, the link monitoring tree initialization module 132 is used to obtain device information of multiple PCIe devices in the PCIe link and establish a link monitoring tree of the PCIe link based on the above device information.

[0067] In some implementations, the first baseboard controller 13 may obtain device information of a plurality of PCIe devices in the PCIe link at the processor 11 through the first bus.

[0068] For example, Figure 3 FIG. 4 is a schematic diagram showing a method of obtaining device information of multiple PCIe devices in a PCIe link through a processor. Figure 3As shown, in the configuration space of each PCIe device, an independent register address is specified for the device information of the PCIe device. To facilitate understanding of the solution, the Nth level PCIe expansion chip 30 is at the second PCIe device level in the PCIe link.

[0069] Please continue reading Figure 3 Address 1 in the register of each PCIe device records the device identifier of the PCIe device, address 2 records the secondary bus identifier of the PCIe device, address 3 records the sub-bus identifier of the PCIe device, and address 4 records the header type identifier of the PCIe device.

[0070] The first baseboard controller 13 sends a first query instruction to the processor 11. In response to the first query instruction, the processor 11 scans multiple PCIe devices in the PCIe link.

[0071] More specifically, the PCIe bus number of the root port 1 of the processor 11 is "0", and the processor 11 scans the PCIe device with the PCIe bus number "1" in sequence. It is worth noting that when the processor 11 scans the above-mentioned multiple PCIe devices, it will first obtain the vendor identification identifier of each PCIe device, and perform in-situ detection of each PCIe device based on the above-mentioned vendor identification identifier, which will not be repeated below.

[0072] First, the processor 11 obtains the secondary bus identifier and sub-bus identifier of the first-level PCIe expansion chip 20 whose PCIe bus number is "1", and determines that the bus number range of multiple PCIe devices mounted under the first-level PCIe expansion chip 20 is 2-11 based on the secondary bus identifier "2" and the sub-bus identifier "11".

[0073] Secondly, the processor 11 obtains the header type identifier of the first-level PCIe expansion chip 20, and determines the device type of the first-level PCIe expansion chip 20 according to the header type identifier [6:1].[7:0]. Bit 6 is 1, indicating that the PCIe device is a bridge device, and bit 7 is 0, indicating that the PCIe device is a single-function device.

[0074] Again, the processor 11 sequentially scans the PCIe devices with PCIe bus numbers “3-11” mounted under the first-level PCIe expansion chip 20 .

[0075] It is worth noting that when the PCIe device scanned by the processor 11 is a bridge device, the processor 11 will continue to scan the PCIe devices mounted under the bridge device until the traversal of all PCIe devices mounted under the bridge device is completed.

[0076] For example, when scanning the Nth level PCIe expansion chip 30 with PCIe bus number "3", the processor 11 obtains the secondary bus identifier "5" and the sub-bus identifier "10" of the Nth level PCIe expansion chip 30, and determines that the bus number range of the multiple PCIe devices mounted under the Nth level PCIe expansion chip 30 is 5-10. The processor 11 obtains the header type identifier of the first level PCIe expansion chip 20, and determines that the Nth level PCIe expansion chip 30 also belongs to the bridge device according to the header type identifier [6:1].[7:0].

[0077] Next, the processor 11 first scans the PCIe devices with bus numbers ranging from 5 to 10.

[0078] When the NVMe expansion chip 411 with the PCIe bus number "5" is scanned, bit 6 in the header type identifier of the NVMe expansion chip 411 is 0, indicating that the device is a PCIe terminal device, and bit 7 is 0, indicating that the device is a multi-function device. At this time, it is also necessary to continue to traverse the terminal devices mounted under the NVMe expansion chip 411 according to the function number of the NVMe expansion chip 411.

[0079] When a terminal device 412 with a PCIe bus number of "9" is scanned, bit 6 in the header type identifier of the terminal device 412 is 0, indicating that the device is a PCIe terminal device, and bit 7 is 0, indicating that the device is a single-function device.

[0080] When the second PCIe card 42 with PCIe bus number "10" is scanned, bit 6 in the header type identifier of the second PCIe card 42 is 0, indicating that the device is a PCIe terminal device, and bit 7 is 0, indicating that the device is a single-function device.

[0081] So far, the processor 11 has completed the traversal of all PCIe devices with bus numbers ranging from 5 to 10 mounted under the N-th level PCIe expansion chip 30 .

[0082] At the very least, the processor 11 will first scan the first PCIe card with bus number "11". If bit 6 in the header type identifier of the first PCIe card 20 is 0, it means that the device is a PCIe terminal device, and if bit 7 is 0, it means that the device is a single-function device.

[0083] The processor 11 traverses multiple PCIe devices in the above manner, obtains the device identification, secondary bus, sub-bus, and header type identification of each PCIe device from the register addresses of the multiple PCIe devices, and sends the above device information to the link monitoring tree initialization module 132 of the first baseboard controller 13 through the first bus.

[0084] Finally, the link monitoring tree initialization module 132 determines the link monitoring tree of the PCIe link based on the above device information.

[0085] In some implementations, the first baseboard controller 13 may obtain device information of multiple PCIe devices in the PCIe link through a management chip.

[0086] First, the first baseboard controller 13 sends a second query instruction to the management chip 12. In response to the second query instruction, the management chip 12 uses the processor 11 to obtain device information of multiple PCIe devices in the PCIe link in the same manner.

[0087] Then, the management chip 12 sends the device information obtained by the processor 11 to the link monitoring tree initialization module 132 of the first baseboard controller 13 through the second bus.

[0088] Please continue reading Figure 2 When the operating system of the server is running, the link information monitoring module 133 is used to obtain link information of multiple PCIe devices in the PCIe link according to a preset time.

[0089] In some implementations, the first baseboard controller 13 may obtain link information of multiple PCIe devices in the PCIe link from the processor 11 via the first bus.

[0090] Taking the first bridge device 20 as an example, Figure 4a FIG. 4 is a schematic diagram showing how to obtain link information of a first bridge device in a PCIe link through a processor. Figure 4a As shown, the first baseboard controller 13 sends a first query instruction to the processor 11. In response to the first query instruction, the processor 11 obtains the link information of the first bridge device 13 from the configuration space of the first bridge device 13.

[0091] It is worth noting that the PCIe link information is stored dynamically in the configuration space and does not specify a fixed register address.

[0092] First, processor 11 needs to read the value in the register at address 5. If the value is not "0x10", it needs to continue reading the value in the register based on address 5, stepping by 1 byte as the offset until it reads address 6 with a value of "0x10".

[0093] Then, based on address 6, CPU 11 uses "0Ch" as an offset to read the value of the register with the address "address 6+0Ch", where the value in the register is the link information of the first bridge device 20, wherein the link information includes the link rate and bandwidth of the PCIe device.

[0094] The processor 11 obtains the link information of the second bridge device 30, the third bridge device 411, the terminal device 412, the first PCIe card 21 and the second PCIe card 42 in the same manner.

[0095] In some implementations, the first baseboard controller 13 may obtain link information of multiple PCIe devices in the PCIe link from the management chip 12 via the second bus.

[0096] First, the first baseboard controller 13 sends a fourth query instruction to the management chip 12. In response to the fourth query instruction, the management chip 12 uses the processor 11 to obtain link information of multiple PCIe devices in the PCIe link in the same manner.

[0097] Then, the management chip 12 sends the link information obtained by the processor 11 to the link information monitoring module 133 of the first baseboard controller 13 through the second bus.

[0098] In some implementations, the first baseboard controller 13 may obtain link information of multiple PCIe devices in the PCIe link from the second baseboard controller 413 through the first interface.

[0099] For example, Figure 4b FIG. 4 is a schematic diagram showing how to obtain link information of a PCIe device on a first board through a first interface. Figure 4b As shown, a monitoring circuit 415 is provided on the first board 41, and the monitoring circuit 415 can detect the link information of the NVMe extension chip 411 and the terminal device 412 on the first board 41 in real time for query by the second baseboard management controller 413. The first baseboard controller 13 can obtain the link information of the NVMe extension chip 411 and the terminal device 412 from the second baseboard management controller 413 through the first interface 414 at a preset time.

[0100] In an embodiment of the present application, when the PCIe link includes multiple boards, the first baseboard controller 131 can establish communication with the baseboard management controller on each board through the high-performance interfaces provided by each of the multiple boards to obtain link information of all PCIe devices on any board.

[0101] Please continue reading Figure 2 When the operating system of the server is running, the link status judgment module 134 is used to obtain the expected values ​​of multiple PCIe devices in the PCIe link. The link status of the above devices is judged according to the link information obtained by the link information monitoring module 133 and the expected values, and the faulty device among the above devices is determined.

[0102] The expected value, the expected link rate and expected bandwidth of the PCIe device, are determined by the product performance of the PCIe. When the actual link rate and bandwidth of the PCIe device are less than the expected link rate and expected bandwidth of the device, it can be determined that the PCIe device has a fault.

[0103] See also Figure 2 When the operating system of the server is running, the link abnormality processing module 135 determines the faulty device during the power-on self-test according to the fault information of the PCIe link received by the link abnormality detection module 131.

[0104] The link anomaly detection module 135 sends an alarm message to the client 200 based on the device identifier in the fault information during the BIOS power-on self-test and the device identifier of the faulty device when the operating system of the server is running, and at the same time sends a self-healing instruction to the faulty device 50.

[0105] By way of example and not limitation, the first PCIe card 21 is any PCIe device among the multiple PCIe devices mounted under the first bridge device 20, and the second PCIe card 42 is any PCIe device among the multiple PCIe devices mounted under the second bridge device 30. In other words, the number of PCIe devices in the 1st to N+1th device levels is not limited in the embodiments of the present application.

[0106] Figure 2 The embodiments shown are merely illustrative. For example, the division of modules in the firmware program is only a logical function division, and there may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. The various functional modules in the various embodiments of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0107] Next, based on the content described above, the PCIe link detection method of the server provided by the embodiment of the present application is introduced. It can be understood that the method is proposed based on the content described above, and part or all of the content of the method can refer to the description above.

[0108] See also Figure 5 , Figure 5 FIG. 1 is a flow chart of a PCIe link detection method for a server provided in an embodiment of the present application. Figure 5 As shown, PCIe link detection of the server can be implemented through S310 to S350.

[0109] S510: Determine information of abnormal devices in the power self-check phase.

[0110] During the power-on self-test phase of the server, the first baseboard controller 131 uses the abnormality detection module 131 to monitor the PCIe link, obtains the fault information of the PCIe device during the PCIe link establishment process and the training process, and sends the fault information of the PCIe device to the link abnormality processing module 135.

[0111] In some embodiments, the expected value of the first PCIe card 21 is x8 16gt / s. During the power-on self-test phase, the BIOS of the server monitors that the current value of the first PCIe card 21 is x8 8gt / s, which does not meet the expected value. Therefore, the first PCIe card 21 is determined to be a faulty device, and the fault information of the first PCIe card 21 is sent to the first baseboard controller 131.

[0112] In this way, the first baseboard management controller 13 can monitor the faulty devices in the PCIe link establishment process and the training process by means of out-of-band management, without affecting the in-band service of the server.

[0113] S520: Determine a link monitoring tree of the PCIe link.

[0114] During the operation phase of the server operating system, the first baseboard controller 13 can use the monitoring tree initialization module 132 to obtain device information of multiple PCIe devices in the PCIe link from the processor 11 or the management chip 12 through the first bus or the second bus, and determine the link monitoring tree of the PCIe link according to the above device information.

[0115] It is worth noting that a unique device identifier is independently allocated to each port of a bridge device in the PCIe link, and an independent bus number is also allocated between the upstream port and the downstream port of each bridge device.

[0116] For example, Figure 6 FIG. 4 is a schematic diagram of a link monitoring tree established based on device information of multiple PCIe devices in a PCIe link. Figure 6 As shown, the link monitoring tree takes the root port 1 of the processor 11 as the root node, and the first baseboard controller 13 divides the link monitoring tree into four levels according to the device information of multiple PCIe devices in the PCIe link.

[0117] In the first level, the first-level PCIe expansion chip 20 is connected to the root port 1 of the processor 11 via the PCIe bus 1, and the bus number connecting the upstream port and the downstream port thereof is the PCIe bus 2.

[0118] The first-level PCIe expansion chip 20 is a first bridge device, and the bus number range of the PCIe devices mounted thereon is PCIe bus 3 to PCIe bus 11.

[0119] The device identifier of the upstream port 1 of the first bridge device is 1.0.0, the device identifier of the downstream port 2 is 2.0.0, and the device identifier of the downstream port 3 is 2.1.0.

[0120] The second level includes an N-th level PCIe expansion chip 30 and a first PCIe card 21 .

[0121] The second-level PCIe expansion chip 3 is connected to the downstream port 2 of the first bridge device via the PCIe bus 3 , and the bus number connecting the upstream port and the downstream port thereof is the PCIe bus 4 .

[0122] The second-level PCIe expansion chip 20 is a second bridge device, and the bus number range of the PCIe devices mounted thereunder is PCIe bus 5 to PCIe bus 10.

[0123] The device identifier of the upstream port 1 of the second bridge device is 3.0.0, the device identifier of the downstream port 2 is 4.0.0, and the device identifier of the downstream port 3 is 4.1.0.

[0124] The first PCIe card 21 is a leaf node of the first bridge device, connected to the downstream port 3 of the first bridge device via the PCIe bus 11, and its device identifier is 11.0.0.

[0125] In the third level, there are an NVMe expansion chip 411, a terminal device 412 and a second PCIe card 42.

[0126] The NVMe expansion chip 411 is connected to the downstream port 2 of the second bridge device via the PCIe bus 5, and the bus number connecting the upstream port and the downstream port is the PCIe bus 6.

[0127] The NVMe expansion chip is a multifunctional PCIe device, and as a third bridge device, the bus number range of the NVMe mounted thereon is PCIe bus 7 to PCIe bus 8.

[0128] Since the link status of the NVMe mounted under the NVMe expansion chip 411 can be judged, the first baseboard controller 13 can only record the device identifier 5.0.0 of the upstream port of the NVMe expansion chip 4.

[0129] The terminal device 412 is a leaf node of the second bridge device, connected to the downstream port 3 of the second bridge device via the PCIe bus 9, and its device identifier is 9.0.0.

[0130] The second PCIe card 42 is a leaf node of the second bridge device, connected to the downlink port 4 of the second bridge device via the PCIe bus 10, and its device identifier is 10.0.0.

[0131] The first baseboard controller 13 can detect the PCIe link by actively detecting and generating a link monitoring tree through out-of-band management without additional resource configuration, without affecting the in-band service of the server 100. In this way, the staff can accurately determine the link status of the terminal PCIe device in the multi-level PCIe link scenario, avoiding missed alarms in PCIe link detection.

[0132] S530: Obtain link information of the link monitoring tree.

[0133] During the detection of the PCLe link, the first baseboard controller 13 may be used to set a monitoring node in the link monitoring tree determined in step S520 according to monitoring requirements.

[0134] In order to prevent the PCIe terminal device from being missed during the link detection process, the staff uses the first baseboard controller 13 to set the port of the bridge device to which the PCIe terminal device is connected as a monitoring node of the link monitoring tree.

[0135] It is worth noting that, during the PCIe link detection process, the first baseboard controller 13 can be used to set a monitoring node in the link monitoring tree based on the PCIe link fault information obtained during the BIOS power-on self-test phase.

[0136] Exemplarily, during the operating system running stage of the server, the first baseboard management controller 13 receives fault information of the first PCIe card 21 during the power-on self-test stage, and therefore sets the first PCIe card 21 and port 3 of the first bridge device as monitoring nodes of the link monitoring tree.

[0137] For example, Figure 7 FIG. 4 is a schematic diagram showing a method for obtaining link information of a monitoring node of a link monitoring tree. Figure 7 As shown, the monitoring nodes in the first level of the link monitoring tree include port 2 and port 3 of the first bridge device; the monitoring nodes in the second level of the link monitoring tree include port 2, port 3 and port 4 of the second bridge device, and the first PCIe card 21; the monitoring nodes in the third level of the link monitoring tree include port 1 of the third bridge device, the terminal device 412, and the second PCIe card 412.

[0138] The first baseboard controller 13 uses the link information monitoring module 133 to receive the link information of each monitoring node in the link monitoring tree through the first bus or the second bus at a preset time. The link information is obtained by the processor 11 through a loop traversal, including the current value and expected value of the device rate of each PCIe device, specifically including the following contents.

[0139] The expected value of port 2 of the first bridge device is x16 32gt / s, and its current value is x8 32gt / s; the expected value of port 3 of the first bridge device is x8 16t / s, and its current value is x8 16gt / s.

[0140] The expected value of port 2 of the second bridge device is x8 16gt / s, and its current value is x8 16gt / s; the expected value of port 3 of the second bridge device is x8 8t / s, and its current value is x8 8gt / s; the expected value of port 4 of the second bridge device is x16 32t / s, and its current value is x8 16gt / s; the expected value of the first PCIe card 21 is x8 16t / s, and its current value is x8 16gt / s.

[0141] The expected value of port 1 of the third bridge device is x8 16gt / s, and its current value is x8 16gt / s; the expected value of terminal device 412 is x8 8t / s, and its current value is x8 8gt / s; the expected value of the second PCIe card 42 is x16 32t / s, and its current value is x16 32t / s.

[0142] As mentioned above, the first baseboard controller 131 can set each monitoring node in the link monitoring tree and reduce the number of monitoring nodes as required to improve the detection efficiency of the PCIe link detection method.

[0143] In some implementations, the first baseboard controller 131 may also receive link information of the third bridge device 411 and the terminal device 412 on the first board 41 through the first interface provided by the second baseboard management controller 413 .

[0144] In the embodiment of the present application, the first baseboard controller 13 forms a monitoring network of multiple node devices in the PCIe link of the server through the channel established by the first interface and the second baseboard controller 413, as well as multiple transmission channels such as the first bus connected to the processor 11 and the second bus connected to the management chip 12. In this way, the link information of each monitoring node in the link monitoring tree is more accurate, which is convenient for the staff to monitor the PCIe link.

[0145] S540: Determine the link status of the link monitoring tree.

[0146] During the operation phase of the server operating system, the first baseboard controller 131 uses the link status judgment module 134 to judge the link status of all monitoring nodes in the link monitoring tree from top to bottom based on the link information obtained in step S530.

[0147] The judgment rules of the link status of the PCIe device specifically include the following contents.

[0148] The first baseboard controller 131 determines the link status of the PCIe device based on the link information of the PCIe device itself. For example, if the current value of the device rate of any PCIe device (the first PCIe device) among the first bridge device 20, the second bridge device 30, the third bridge device 411, the terminal device 412, the first PCIe card 21, and the second PCIe card 42 is less than the expected value, it is determined that the above-mentioned PCIe device has a fault.

[0149] If the current value of the device rate of the above-mentioned first PCIe device meets the expected value, the first baseboard controller 131 is also required to determine the link status of the device according to the current value of the device rate of the bridge device (second PCIe device) upstream of the first PCIe device.

[0150] Taking the second PCIe card 42 as an example, if the current value of the device rate of the second PCIe card 42 is greater than the current value of the device rate of the second bridge device 30 , the first baseboard controller 131 determines that the second PCIe card 42 has a fault.

[0151] If the current value of the device rate of the second PCIe card 42 is equal to the current value of the device rate of the second bridge device 30, the first baseboard controller 131 is also required to determine the link state of the second PCIe card 42 according to the current value of the device rate of the first bridge device 20 upstream of the second PCIe card 42. This is done until the first baseboard controller 131 completes the comparison of the current values ​​of the device rates of the second PCIe card 42 and all the bridge devices upstream thereof.

[0152] If the current value of the device rate of the second PCIe card 42 is equal to the current value of the device rate of the first bridge device 20 , the first baseboard controller 131 may determine that the link status of the second PCIe card 42 is normal.

[0153] Specifically, first, the first baseboard controller 131 uses the link status judgment module 134 to judge the link status of port 2 of the first bridge device 20. The expected value is x16 32gt / s, and the current value is x8 32gt / s. The current value does not meet the expected value, and it is determined that the device status is abnormal.

[0154] Secondly, the first baseboard controller 131 uses the link status judgment module 134 to judge the monitoring node downstream of the port 2 of the first bridge device 20 , that is, the port 2 of the second bridge device 30 .

[0155] The expected value of the port 2 of the second bridge device 30 is x8 16gt / s, and the current value is x8 16gt / s. If the current value meets the expected value, the monitoring node downstream of the port 2 of the second bridge device 30 continues to be judged.

[0156] The first baseboard controller 131 uses the link status judgment module 134 to judge port 1 of the third bridge device 411. Its expected value is x8 16gt / s, and the current value is x8 16gt / s. The current value is consistent with the expected value. Since the third bridge device 411 is a multi-function device, it is determined that the link status of NVMe1 and NVMe2 mounted thereon are both normal.

[0157] Again, the first baseboard controller 131 uses the link status judgment module 134 to judge the port 3 of the second bridge device 30, and its expected value is x8 8gt / s, and the current value is x8 8gt / s. The current value meets the expected value, and then continues to judge the monitoring node terminal device 412 downstream of the port 3 of the second bridge device 30.

[0158] The expected value of the terminal device 412 is x8 8gt / s, and the current value is x8 8gt / s, so it is determined that the link status of the terminal device 412 is normal.

[0159] At last, the first baseboard controller 131 uses the link status judgment module 134 to judge the port 4 of the second bridge device 30, and its expected value is x16 32gt / s, and the current value is x8 16gt / s. The current value does not meet the expected value, and then continues to judge the second PCIe card 42 of the monitoring node downstream of the port 4 of the second bridge device.

[0160] The expected value of the second PCIe card 42 is x16 32gt / s, and the current value is x16 32gt / s, which meets the expected value. However, since the current value of the second PCIe card 42 is greater than the current value of the port 4 of the second bridge device 30, the first baseboard controller 131 determines that the link state of the second PCIe card is abnormal. At the same time, the first baseboard controller 131 sends the device identification of the second PCIe card 42 to the link abnormality processing module 135.

[0161] Finally, the first baseboard controller 131 uses the link status judgment module 134 to judge the link status of port 3 of the first bridge device 20. The expected value is x8 16gt / s, and the current value is x8 16gt / s. The current value meets the expected value, and then continues to judge the link status of the first PCIe card 21, a monitoring node downstream of port 3 of the first bridge device.

[0162] The expected value of the first PCIe card 21 is x8 16gt / s, and the current value is x8 16gt / s. If the current value meets the expected value, the first baseboard controller 131 determines that the link status of the first PCIe card 21 is normal, and clears the fault information of the first PCIe card 21 and cancels the alarm.

[0163] In some implementations, the first baseboard controller 131 may use the link status determination module 134 to determine the link status of a designated monitoring node, so that the PCIe link may be detected more accurately.

[0164] S550: Send an alarm message to the client and send a self-healing instruction to the faulty device.

[0165] During the operating system running stage of the server, first, the first baseboard controller 131 receives the fault information sent by the BIOS during the power-on self-test stage, and uses the link exception handling module 135 to obtain the device identification of the faulty device recorded in the fault information, and / or the device identification of the faulty device during the operating system running stage of the server.

[0166] Then, the first baseboard controller 131 determines the alarm information of the PCIe link based on the device identifier, and sends the alarm information to the client 200 .

[0167] By way of example and not limitation, the self-healing instruction may be an instruction to initialize a PCIe device, or may be other self-healing instructions to reset a PCIe device or interrupt data transmission of a PCIe device. In other words, the embodiment of the present application does not limit the type of self-healing instruction.

[0168] Finally, the first baseboard controller 131 sends a self-healing instruction to the first PCIe card 21 and the first node device 42 using the link abnormality processing module 135 .

[0169] For example, Figure 8 FIG. 4 is a schematic diagram showing a method of sending a self-healing instruction to a faulty device. Figure 8As shown, in some embodiments, the first baseboard controller 13 can adopt an out-of-band management method to send a self-healing instruction to the faulty device through the IIC (Inter-Integrated Circuit, integrated circuit bus), NCSI (Network Controller Sideband Interface, network controller sideband interface protocol) bus and MCTP (Management Component Transport Protocol, management component transport protocol) bus.

[0170] In some implementations, the first baseboard controller 13 may also send a self-healing instruction to the faulty device through the MCTP bus and the PCIe bus in an in-band management manner.

[0171] Compared with the prior art, the present application provides a PCIe link detection method for a server, which records the fault information of the faulty device in the power-on self-test phase; and in the server operation phase, establishes a link monitoring tree for the PCIe link, and uses multiple data channels to obtain the link information of the link monitoring tree. Based on the above link information, the link status of the link monitoring tree is judged, and the faulty device in the operating system operation phase of the server is determined. According to the device identification of the faulty device in the power-on self-test phase and the operating system operation phase of the server, an alarm message is sent to the processor, and a self-healing instruction is sent to the faulty device. Complex monitoring alarms and recovery strategies are implemented, and the stability of the system is avoided. At the same time, the method supports the high-performance interface provided by the module, and no missed alarms are generated through the multi-level detection of the PCIe link, which can help customers detect the PCIe link of the server more accurately and precisely.

[0172] The above is the introduction to the PCIe link detection method of a server provided in the embodiment of the present application. Next, a server provided in the embodiment of the present application is introduced.

[0173] Fig. 9 The structure diagram of the server provided in the embodiment of the present application is shown. Fig. 9 As shown, an embodiment of the present application provides a server 90, including a first baseboard controller 91 and a memory 92, wherein the memory 92 stores a computer program that can be run on the first baseboard controller 91, and is characterized in that the first baseboard controller 91 implements the above-mentioned PCIe link detection method when executing the computer program.

[0174] The types of servers disclosed in the embodiments of the present application are not limited here for the purpose of illustration and not limitation. Specifically, they may be cabinet servers, tower servers, rack servers, and blade servers. In other words, the embodiments of the present application do not specifically limit the specific types of servers. Further, it can be understood that Figure 1 The structure of the server shown does not constitute a limitation on the structure of the server. The server may include more or less components than shown in the figure, or combine some components, or arrange the components differently.

[0175] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0176] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for detecting PCIe link status of a server, characterized in that: The server includes a processor, a PCIe link connected to the processor, and a first baseboard controller, the PCIe link includes a plurality of PCIe devices, the processor is connected to the first baseboard controller, and the method is used for the first baseboard controller, including: Acquire device information of the multiple PCIe devices, and determine a link monitoring tree of the PCIe link according to the device information; the link monitoring tree reflects the connection relationship between the multiple PCIe devices; Determine multiple monitoring nodes in the link monitoring tree, and obtain link information of the multiple monitoring nodes; each of the multiple monitoring nodes corresponds to a PCIe device; the link information includes expected values ​​and current values ​​of device rates of the multiple PCIe devices; If the expected value of the device rate of the first PCIe device meets the current value, determining the link state of the first PCIe device according to the current value of the device rate of at least one bridge device upstream of the first PCIe device; the first PCIe device includes a PCIe device on any node except the root node; If the current value of the device rate of the at least one bridge device is smaller than the current value of the device rate of the first PCIe device, it is determined that the first PCIe device is a faulty device in the PCIe link.

2. The method according to claim 1, characterized in that: The determining of a plurality of monitoring nodes in the link monitoring tree further includes: During the BIOS power-on self-test phase, the PCIe link is monitored to obtain fault information of the PCIe link; The determining of a plurality of monitoring nodes in the link monitoring tree comprises: A plurality of monitoring nodes in the link monitoring tree are determined based on the fault information.

3. The method according to any one of claims 1 to 2, characterized in that: After determining that the first PCIe device is a faulty device in the PCIe link, the method further comprises: Output alarm information for the faulty device, and send a self-healing instruction to the faulty device, including initializing the faulty device, resetting the faulty device, and interrupting data transmission of the faulty device.

4. The method according to claim 1, characterized in that: The first baseboard controller is connected to the processor via a first bus, and acquiring the device information of the multiple PCIe devices includes acquiring the device information of the multiple PCIe devices from the processor via the first bus.

5. The method according to claim 4, characterized in that The obtaining link information of the plurality of monitoring nodes comprises: The link information of multiple monitoring nodes is obtained from the processor through the first bus.

6. The method according to claim 3, wherein the server further comprises a management chip, the management chip is connected to the processor, and the first baseboard controller is connected to the management chip via a second bus, wherein: The acquiring device information of the plurality of PCIe devices includes acquiring the device information of the plurality of PCIe devices from the management chip through the second bus.

7. The method according to claim 6, characterized in that The obtaining of link information of the plurality of monitoring nodes further includes: The link information of multiple monitoring nodes is obtained from the management chip through the second bus.

8. The method according to claim 1, characterized in that: The server further includes a first board, a PCIe device and a second baseboard controller are arranged on the first board, the PCIe device is connected to the second baseboard controller, and the second baseboard controller is connected to an interface of the first baseboard controller via a first interface. The method for obtaining link information further includes: The link information of the PCIe device is obtained from the second baseboard controller through the first interface.

9. A server, comprising a memory and a first substrate controller, wherein the memory stores a computer program that can be run on the first substrate controller, characterized in that: When the first substrate controller executes the computer program, the method according to any one of claims 1 to 7 is implemented.

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