A vertical cavity surface emitting laser and a method for manufacturing the same

Abstract

The present invention relates to the field of semiconductor laser technology, and specifically to a vertical cavity surface emitting laser and a preparation method thereof, wherein the laser comprises a substrate, an epitaxial layer is arranged on the substrate, and is characterized in that a first electrode, a second electrode, a first etched area and a second etched area are arranged on the epitaxial layer, the first etched area and the second etched area are arranged in the epitaxial layer, and the first etched area surrounds to form a truncated cone waveguide, and the first electrode is arranged on the top of the truncated cone waveguide; the two etched areas are connected to the first etched area, and an organic polymer is arranged inside the first etched area and the second etched area to form an organic polymer layer, and the second electrode is drawn out from the first electrode and extends above the second etched area. The present invention can reduce the equivalent dielectric constant of the epitaxial layer between the electrodes, reduce the parasitic capacitance of the chip, and improve the modulation bandwidth and transmission rate of the vertical cavity surface emitting laser.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor lasers, and in particular to a vertical cavity surface emitting laser and a preparation method thereof. Background Art

[0002] Compared with edge-emitting lasers, vertical cavity surface emitting lasers (VCSELs) have the characteristics of low threshold, low power consumption, single longitudinal mode, high modulation bandwidth, and easy two-dimensional array integration, so they are used as the core light source for short-distance optical communications. With the development of optical communication technology, the demand for high-speed VCSEL chips for short-distance transmission has increased dramatically, and the transmission rate requirements for a single chip have transitioned from 10Gbit / s NRZ to 25Gbit / s NRZ and 50Gbit / s PAM4.

[0003] The parasitic capacitance of the VCSEL chip is a key factor restricting the chip transmission rate, especially the contribution of the electrode capacitance. According to the capacitance theory between planar electrodes, ways to reduce the electrode capacitance of the VCSEL chip include reducing the electrode area, increasing the electrode spacing, and reducing the dielectric constant of the medium between electrodes. High-speed VCSEL chips often use a coplanar electrode structure, and due to subsequent testing and packaging requirements, the electrode area cannot be reduced indefinitely. Therefore, due to structural limitations, the main method currently used to reduce the parasitic capacitance of the chip is to insert a certain thickness of low dielectric constant material between the positive electrode and the epitaxial layer, but this method greatly reduces the chip reliability due to stress mismatch between materials and overly obvious height differences. Summary of the invention

[0004] In order to improve the deficiencies of the prior art, the present invention provides a vertical cavity surface emitting laser and a method for preparing the same, which can improve the modulation bandwidth and transmission rate of the chip by reducing the parasitic capacitance of the chip and ensure the reliability of the chip.

[0005] To achieve the above object, the technical solution of the present invention is:

[0006] In a first aspect, the present invention provides a vertical cavity surface emitting laser, comprising a substrate, an epitaxial layer is arranged on the substrate, a first electrode, a second electrode, a first etched region and a second etched region are arranged on the epitaxial layer, the first etched region and the second etched region are arranged in the epitaxial layer, and the first etched region is surrounded to form a truncated cone waveguide, and the first electrode is arranged on the top of the truncated cone waveguide; the two etched regions are connected to the first etched region, and organic polymers are arranged inside the first etched region and the second etched region to form an organic polymer layer, and the second electrode is led out from the first electrode and extends to above the second etched region.

[0007] According to an embodiment of the present invention, the projection area of ​​the second electrode on the substrate covers the projection area of ​​the first etched region on the substrate to increase the heat dissipation characteristics of the laser chip, that is, the second electrode is not only connected to the first electrode, but also surrounds the first etched region outside the first electrode.

[0008] According to an embodiment of the present invention, a third etching region is further provided on the epitaxial layer, the epitaxial layer exposes the N-type ohmic contact layer through the third etching region, the third etching region is provided with a third electrode, and the third electrode is provided on the top of the N-type ohmic contact layer.

[0009] According to an embodiment of the present invention, the dielectric constant of the organic polymer layer is less than or equal to 3, preferably the dielectric constant of the organic polymer layer is less than or equal to 2, and further preferably the dielectric constant of the organic polymer layer is less than or equal to 1.5.

[0010] According to an embodiment of the present invention, the organic polymer is selected from one or more of BCB, PI, PR, and PS, for example, BCB.

[0011] According to an embodiment of the present invention, the thickness of the organic polymer layer is equivalent to the depth of the first etching zone and the second etching zone. Preferably, the depths of the first etching zone and the second etching zone are the same, and the thickness of the organic polymer layer is ±1um of the depth of the first etching zone and the second etching zone.

[0012] According to an embodiment of the present invention, the thickness of the organic polymer layer is 2-4 um, and exemplarily is 3 um.

[0013] According to an embodiment of the present invention, both the first electrode and the first etching region are circular ring structures. Preferably, the first electrode and the first etching region are concentrically arranged.

[0014] According to an embodiment of the present invention, the epitaxial layer includes an N-type ohmic contact layer, an N-DBR layer, an active region, an oxidation restriction layer, a P-DBR layer and a P-type ohmic contact layer arranged in sequence from bottom to top.

[0015] According to an embodiment of the present invention, the first etching area is formed by an ICP etching process, and the etching starts from the P-type ohmic contact layer, passes through the P-type DBR layer and the resonant cavity, and stops after entering the N-type DBR layer. The etching depth is 3.8-4.2um, and 4.0um is exemplified.

[0016] According to an embodiment of the present invention, the inner diameter of the bottom of the first etching area is 20-30um, exemplarily 25um, and preferably the bottom width of the groove of the first etching area is 4-8um, exemplarily 6um.

[0017] According to an embodiment of the present invention, the second etching region includes a main groove and a connecting groove, the main groove is connected with the first etching region through the connecting groove, and the main groove is a circular groove.

[0018] According to an embodiment of the present invention, the second etching area is formed by an ICP etching process, and the etching starts from the P-type ohmic contact layer, passes through the P-type DBR layer and the resonant cavity, and stops after entering the N-type DBR layer. The etching depth is 3-5um, and 3.2um is exemplified.

[0019] According to an embodiment of the present invention, the bottom diameter of the main groove of the second etched area is 70-75um, and exemplarily is 75um.

[0020] According to an embodiment of the present invention, the first electrode is a ring structure with an inner diameter of 10-12 um, exemplarily 10 um, and an outer diameter of 16-20 μm, exemplarily 18 um.

[0021] According to an embodiment of the present invention, the material of the first electrode is Ti / Pt / Au, and the thickness is 2500-3000A, and 3000A is exemplary.

[0022] According to an embodiment of the present invention, the second electrode is connected to the first electrode and is led out to above the organic polymer layer in the second etched region.

[0023] According to an embodiment of the present invention, the second electrode includes a connecting portion and a main structure, the main structure is circular in shape, and preferably the center of the main structure coincides with the center of the second etching area.

[0024] According to an embodiment of the present invention, the main structure diameter of the second electrode is 60-65 um, and exemplarily is 63 um.

[0025] According to an embodiment of the present invention, the material of the second electrode is TiW / Au or Ti / Au, and the thickness is 10000-30000A, and 25000A is exemplary.

[0026] According to the embodiment of the present invention, the third etching area exposes the N-type ohmic contact layer of the epitaxial layer to form a main epitaxial structure.

[0027] According to an embodiment of the present invention, the etching depth of the third etching area is 9-11 um, exemplarily 9 um.

[0028] According to an embodiment of the present invention, the third electrode is disposed above the N-type ohmic contact layer and adjacent to the main epitaxial structure.

[0029] According to an embodiment of the present invention, the third electrode material is Ni / Ge / Au / Ni / Au or Pd / Ge / Ti / Pt / Au, and the thickness is 3000-4000A, and 3500A is exemplary.

[0030] According to an embodiment of the present invention, the material of the N-type ohmic contact layer is N-type doped GaAs, and the material of the P-type ohmic contact layer is P-type doped GaAs.

[0031] According to an embodiment of the present invention, the N-DBR layer is N-type doped Alx1Ga1-x1 As and Aly1Ga1-y1 As alternately grown, and the P-DBR layer is P-type doped Alx2 Ga1-x2 As and Aly2 Ga1-y2 As alternately grown, wherein: x1 and x2 are independently selected from (0.1-0.15), exemplarily 0.12; y1 and y2 are independently selected from (0.85-0.9), exemplarily 0.88.

[0032] According to an embodiment of the present invention, the material of the oxidation restriction layer is Alz Ga1-z As, where z=0.96-1.0, exemplarily 0.96, 0.98, and 1.0.

[0033] According to an embodiment of the present invention, the thickness of the oxidation restriction layer is 10-20 nm, exemplified by 10 nm, 12 nm, 15 nm, and 20 nm; preferably, the number of layers of the oxidation restriction layer is 1-3 layers, exemplified by 2 layers.

[0034] According to an embodiment of the present invention, the active region includes quantum wells (MQWs) and a resonant cavity, and the sum of the optical thicknesses of the quantum wells and the resonant cavity is an integer multiple of half the wavelength of the laser lasing wavelength.

[0035] According to an embodiment of the present invention, the quantum well is grown alternately by Inx3 Ga1-x3 As and Aly3 Ga1-y3 As, wherein x3=0.1-0.2, y3=0.2-0.4, and the cycle of the alternating growth of Inx3 Ga1-x3 As and Aly3 Ga1-y3 As is 3-5 times.

[0036] According to an embodiment of the present invention, the material of the resonant cavity is GaAs.

[0037] In a second aspect, the present invention further provides a method for preparing the above-mentioned laser, comprising the following steps:

[0038] S1: growing an epitaxial layer on a substrate;

[0039] S2: Disposing a first electrode on the surface of the epitaxial layer;

[0040] S3: etching around the first electrode to form a first etching area;

[0041] S4: etching next to the first etching region to form a second etching region;

[0042] S5: filling the first etching area and the second etching area with an organic polymer;

[0043] S6: Dispose a second electrode on the top of the second etched region.

[0044] According to an embodiment of the present invention, step S1 includes the following steps: an N-type ohmic contact layer, an N-DBR layer, an active area, an oxidation restriction layer, a P-DBR layer and a P-type ohmic contact layer are sequentially grown on the substrate to form an epitaxial layer.

[0045] According to an embodiment of the present invention, step S1 includes the following steps: using MOCVD method to sequentially grow an N-type ohmic contact layer, an N-DBR layer, an active area, an oxidation restriction layer, a P-DBR layer and a P-type ohmic contact layer on the substrate to form an epitaxial layer.

[0046] According to an embodiment of the present invention, step S2 includes the steps of depositing a first electrode on the surface of the epitaxial layer and annealing to form an ohmic contact.

[0047] According to an embodiment of the present invention, the following step is included between step S3 and step S4: wet oxidation is performed on the epitaxial layer to form oxidation limiting holes.

[0048] According to an embodiment of the present invention, the following step is further included before step S5: depositing a passivation layer on the epitaxial layer to protect the oxidation limiting holes.

[0049] According to an embodiment of the present invention, step S6 includes the following steps: preparing a second electrode by magnetron sputtering and electroplating process, connecting the second electrode to the first electrode and leading out to the top of the organic polymer in the second etched area.

[0050] According to an embodiment of the present invention, after step S6, step S7 is further included: performing ICP etching on the epitaxial layer to form a third etching area to expose the N-type ohmic contact layer and form a main epitaxial structure;

[0051] According to an embodiment of the present invention, step S6 further includes step S8: depositing a third electrode on the surface of the N-type ohmic contact layer and annealing to form an ohmic contact.

[0052] According to an embodiment of the present invention, step S8 further includes step S9: depositing a passivation layer on the structure after the third electrode is set and etching windows at the second electrode and the third electrode to form a wafer.

[0053] According to the embodiment of the present invention, step S9 further includes the following steps: thinning the wafer to 100-150 μm, performing on-chip performance testing, and then performing chip cleavage and packaging.

[0054] According to an embodiment of the present invention, in the etching, the etching gas is a Cl2 / Ar2 / N2 mixed gas or a BCl3 / Cl2 mixed gas, and the etching mask is a photoresist mask.

[0055] According to an embodiment of the present invention, the passivation layer is SiNx, SiO2, SiONx or a multilayer combination of the above three dielectric films.

[0056] Beneficial Effects

[0057] The present invention sets a first etching area under the first electrode, sets a second etching area under the second electrode, and sets an organic polymer layer in the first etching area and the second etching area, and uses a low dielectric constant organic polymer material to replace a high dielectric constant semiconductor material, thereby reducing the equivalent dielectric constant of the epitaxial layer between the electrodes, reducing the parasitic capacitance of the chip, and improving the modulation bandwidth and transmission rate of the vertical cavity surface emitting laser; the present invention forms an etching area filling polymer method instead of directly inserting the polymer between the electrode and the epitaxial layer, thereby reducing the parasitic capacitance and reducing the chip stress mismatch at the same time, and there will be no large height difference on the chip surface, so that the reliability and solderability of the chip can be guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 is a longitudinal cross-sectional schematic diagram of a vertical cavity surface emitting laser in Example 1 of the present invention;

[0059] Figure 2 for Figure 1 A top view of

[0060] Figure 3 for Figure 1 A top view position relationship diagram of the first electrode, the second electrode, the first etching area and the second etching area;

[0061] Figure 4 is a flow chart of a method for preparing a vertical cavity surface emitting laser in Example 2 of the present invention;

[0062] Figure 5 This is the 25.7825 Gbit / s eye diagram test result of the vertical cavity surface emitting laser prepared in Example 2 of the present invention.

[0063] In the figure: 1-substrate; 2-epitaxial layer; 3-first electrode; 4-second electrode; 5-third electrode; 6-first etching region; 7-second etching region; 8-third etching region; 9-organic polymer layer. DETAILED DESCRIPTION

[0064] The structure and application of the present invention will be further described in detail below in conjunction with specific embodiments. It should be understood that the following embodiments are only exemplary descriptions and explanations of the present invention and should not be construed as limiting the scope of protection of the present invention. All technologies implemented based on the above content of the present invention are included in the scope that the present invention is intended to protect.

[0065] In the description of the invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they cannot be understood as limitations on the invention.

[0066] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0067] Example 1

[0068] See also Figure 1 , which is a longitudinal cross-sectional schematic diagram of the vertical cavity surface emitting laser in this embodiment, Figure 2 for Figure 1 A top view of Figure 3 for Figure 1 FIG. 1 is a top view of the position relationship among the first electrode 3, the second electrode 4, the first etching region 6 and the second etching region 7. FIG.

[0069] like Figure 1 As shown, the vertical cavity surface emitting laser provided in this embodiment includes a substrate 1, an epitaxial layer 2 is arranged on the substrate 1, and a first electrode 3, a second electrode 4, a third electrode 5, a first etching area 6, a second etching area 7, and a third etching area 8 are arranged on the epitaxial layer 2, wherein the first etching area 6 etches the epitaxial layer 1 and forms a truncated cone waveguide, and the cross section of the first etching area 6 is a circular ring structure, the first electrode 3 is arranged on the top of the truncated cone waveguide, the first electrode 3 is a circular ring structure and is concentric with the first etching area 6; the second etching area 7 is arranged adjacent to one side of the first etching area 6, and in this embodiment, the second etching area 7 is connected with the first etching area 6; an organic polymer layer 9 is arranged inside the first etching area 6 and the second etching area 7; the second electrode 4 is led out from the first electrode 3 and extends to the top of the second etching area 7.

[0070] The dielectric constant of the organic polymer layer 9 is less than or equal to 3. In this embodiment, the material of the organic polymer layer 9 is selected from low dielectric constant materials such as BCB (Benzocyclobutene Resin), PI (Polyimide), PR (Polyster Resin), and PS (Polystyrene). The thickness of the organic polymer layer 9 is equivalent to the depth of the first etching area 6 and the second etching area 7, and can be the corresponding depth ±1um. For example, the thickness of the organic polymer layer 9 is 2-4um, and 3um is exemplified.

[0071] The substrate 1 serves as a carrier of the epitaxial layer 2 and provides support for the epitaxial layer 2. At the same time, as a growth platform for the epitaxial layer 2, the material of the substrate 1 may be GaAs, which may be N-type doped or semi-doped GaAs depending on the specific application.

[0072] The epitaxial layer 2 includes an N-type ohmic contact layer, an N-DBR layer, an active area, an oxidation restriction layer, a P-DBR layer and a P-type ohmic contact layer, which are arranged in sequence from bottom to top, wherein the material of the N-type ohmic contact layer is N-type doped GaAs, and the material of the P-type ohmic contact layer is P-type doped GaAs; the N-DBR layer is N-type doped alternately grown Alx1Ga1-x1 As and Aly1 Ga1-y1As, and the P-DBR layer is P-type doped alternately grown Alx2 Ga1-x2 As and Aly2 Ga1-y2 As, wherein: x1 and x2 are independently selected from (0.1-0.15), exemplarily 0.12; y1 and y2 are independently selected from (0.85-0.9), exemplarily 0.88.

[0073] The material of the oxidation restriction layer is Alz Ga1-z As, z=0.96-1.0, exemplified by 0.96, 0.98, 1.0; the thickness of the oxidation restriction layer is 10-20nm, exemplified by 10nm, 12nm, 15nm, 20nm; the number of layers of the oxidation restriction layer is 1-3, exemplified by 2 layers.

[0074] The active region consists of quantum wells (MQWs) and a resonant cavity. The resonant cavity includes an upper part and a lower part to form a chamber structure, which clamps the quantum well in the middle, wherein: the quantum well is alternately grown by Inx3 Ga1-x3 As and Aly3 Ga1-y3 As, wherein x3=0.1-0.2, y3=0.2-0.4, and the cycle of alternating growth of Inx3 Ga1-x3 As and Aly3 Ga1-y3 As is 3-5 times; the material of the resonant cavity is GaAs, and the sum of the optical thickness of the quantum well and the resonant cavity is an integer multiple of half the wavelength of the laser lasing wavelength.

[0075] See also Figure 2 and Figure 3 As shown, the first electrode 3 is a ring structure with an inner diameter of 10-12um and an outer diameter of 16-20μm, coinciding with the center of the first etching area 6. Preferably, the material of the first electrode 3 is Ti / Pt / Au, with a thickness of 2500-3000A, exemplarily 2500A. The first electrode 3 is prepared by conventional methods in the art, such as by coating, and the coating method is electron beam thermal evaporation.

[0076] The second electrode 4 is connected to the outside of the first electrode 3 and leads to the top of the organic polymer layer in the second etching area 5. The second electrode 4 is a main structure including a connecting portion. The main structure is circular and coincides with the center of the second etching area. The diameter is 60-65um, 63um for example. The connecting portion connects the main structure and the first electrode 3 and can be any shape. The material of the second electrode 4 is TiW / Au or Ti / Au, the thickness is 10000-30000A, 25000A for example. The second electrode 4 is prepared by conventional methods in the art, such as by coating, and the coating method is a combination of magnetron sputtering and electroplating.

[0077] The third electrode 5 is located above the N-type ohmic contact layer and adjacent to the main epitaxial layer. The material of the third electrode 5 is Ni / Ge / Au / Ni / Au or GeAu / Ni / Au. The thickness of the third electrode 5 is 3000-4000A, and 3500A is exemplified. The third electrode 5 is prepared by conventional methods in the art, such as by coating, and the coating method is electron beam thermal evaporation.

[0078] The first etching area 5 is an annular groove structure, the bottom of the first etching area 5 is located at the top or inside of the N-type DBR layer, the annular groove structure is located in the epitaxial layer 2 and forms a truncated cone waveguide in the epitaxial layer 2, the first etching area 5 is formed by an ICP etching process, the etching is etched from the P-type ohmic contact layer through the P-type DBR layer and the resonant cavity, and stops after entering the N-type DBR layer, the etching depth is 3.8-4.2um, 4.0um is exemplary, and the stop point is monitored by the 670nm laser extreme value monitoring curve. The inner diameter of the bottom of the first etching area 5 is 20-30um, 25um is exemplary, and the bottom width of the groove of the first etching area 5 is 4-8um, 6um is exemplary.

[0079] The second etching area 6 is connected to the first etching area 5, and the bottom of the second etching area 6 is located on the top or inside of the N-type DBR layer. The second etching area 6 is formed by an ICP etching process. The etching starts from the P-type ohmic contact layer, passes through the P-type DBR layer and the resonant cavity, and stops after entering the N-type DBR layer. The etching depth is 3-5um, exemplarily 3.2um, and the bottom of the etching area body is 70-75um, exemplarily 75um.

[0080] The third etching area 8 is used to expose the N-type ohmic contact layer of the epitaxial layer 2 to form a main epitaxial layer. The third etching area 8 is formed by an ICP etching process with an etching depth of 9-11um, exemplarily 9um, and the stop point is monitored by a 670nm laser extreme value monitoring curve.

[0081] As a preferred solution of this embodiment, the projection area of ​​the second electrode 4 on the substrate 1 should include the projection area of ​​the first etched region 5 on the substrate 1 to increase the heat dissipation characteristics of the laser chip, that is, the second electrode 4 is not only connected to the first electrode 3, but also surrounds the first etched region 6 outside the first electrode 3.

[0082] The high-speed vertical cavity surface emitting laser of the present invention is provided with etching areas (first etching areas 6 and second etching areas 7) below the first electrode 3 and the second electrode 4, and with low dielectric constant organic polymers (forming organic polymer layers) in the first etching areas 6 and the second etching areas 7, and the low dielectric constant organic polymer materials replace the semiconductor materials with high dielectric constants, thereby reducing the equivalent dielectric constant of the epitaxial layer between the electrodes, reducing the parasitic capacitance of the chip, and improving the modulation bandwidth and transmission rate of the vertical cavity surface emitting laser. At the same time, the chip structure and preparation method will not introduce too much stress mismatch, and there will not be too much height difference on the chip surface, so the reliability of the chip can be guaranteed.

[0083] Example 2

[0084] See also Figure 4 As shown, a method for preparing a vertical cavity surface emitting laser in embodiment 1 comprises the following steps:

[0085] S1: Select an N-type doped GaAs substrate or a semi-doped GaAs substrate as substrate 1, use MOCVD (Metal-organic Chemical Vapor Deposition) equipment on substrate 1, use trimethylgallium (TMGa), trimethylaluminum (TMAl), trimethylindium (TMIn) as group III sources, arsenic (AsH3) as group V source, silane (SiH4) as N-type doping source, carbon tetrachloride (CBr4) as P-type doping source, and sequentially grow an N-type ohmic contact layer, an N-type DBR layer, a resonant cavity layer (a quantum well is formed inside the resonant cavity), an oxidation restriction layer, a P-type DBR layer and a P-type ohmic contact layer on substrate 1 to form an epitaxial layer 2, wherein the N-type ohmic contact layer functions to form an N-type ohmic contact, the resonant cavity layer functions to serve as a light-emitting area, the oxidation restriction layer functions to limit current and light, and the N-type DBR layer and the P-type DBR layer function to form a reflector.

[0086] S2: See Figure 4As shown in (2), a first electrode 3 is deposited on the surface of the epitaxial layer 2. The evaporated material is Ti / Pt / Au with a thickness of 2500A. The electrode is annealed at 390°C for 30s to form an ohmic contact with the P-type ohmic contact layer on the top of the epitaxial layer 2. The first electrode 3 is a ring structure.

[0087] S3: See Figure 4 As shown in (3), EPG562 photoresist is used, and a mask of the first etching region 6 is formed around the first electrode 3 through photolithography alignment, and the PR (photoresist) mask is cured, and then ICP etching (inductively coupled plasma etching) is performed to form the first etching region 6 (process parameters: Cl2 flow rate 4sccm, Ar flow rate 25sccm, N2 flow rate 5sccm, ICP-RF power 300W, Table RF power 55W, temperature 20°C), and the etching stop point is monitored by the 670nm laser extreme value monitoring curve;

[0088] S4: See Figure 4 As shown in (4), the epitaxial layer 2 is wet oxidized to form an oxidation restriction hole, and the oxidation temperature is 350°C-420°C, exemplarily 400°C; the oxidation restriction hole is located in the oxidation restriction layer, and its center coincides with the projection center of the center of the first electrode 3 on the oxidation restriction layer, and the radius of the oxidation restriction hole is smaller than the inner circle radius of the ring of the first electrode 3;

[0089] S5: See Figure 4 As shown in (5), a mask for a second etching region 7 is formed on the surface of the epitaxial layer 2 next to the first etching region 6 by photolithography alignment, and the PR mask is cured, and then ICP etching is performed to form the second etching region 7 (process parameters: Cl2 flow rate 4sccm, Ar flow rate 25sccm, N2 flow rate 5sccm, ICP-RF power 300W, Table RF power 55W, temperature 20°C);

[0090] S6: See Figure 4 As shown in (6), a passivation layer is deposited on the surface of the unetched epitaxial layer 2 to protect the oxidation limiting holes;

[0091] S7: See Figure 4 As shown in (7), BCB is filled into the first etching area 6 and the second etching area 7 on the epitaxial layer 2 by spin coating BCB, photolithography patterning of BCB, and BCB curing.

[0092] S8: See Figure 4As shown in (8), a pattern of a second electrode 4 is formed above the first electrode 3, the first etching area 6, and the second etching area 7 by a photolithography process, and the second electrode 4 is prepared by a magnetron sputtering and electroplating process, so that it is connected to the first electrode 3 and led out to the organic polymer 9 above the second etching area 7, and the plating material is TiW / Au with a thickness of 25000A;

[0093] S9: See Figure 4 As shown in (9), the epitaxial layer 2 is subjected to ICP etching to form a third etching region 8 to expose the N-type ohmic contact layer to form a main epitaxial structure (process parameters: Cl2 flow rate 6 sccm, Ar flow rate 25 sccm, N2 flow rate 5 sccm, ICP-RF power 350 W, Table RF power 55 W, temperature 20°C), and the etching stop point is monitored by a 670 nm laser extreme value monitoring curve;

[0094] S10: See Figure 4 As shown in (10), a third electrode 5 is deposited on the surface of the N-type ohmic contact layer. The evaporated material is Ni / Ge / Au / Ni / Au with a thickness of 3500A, and annealed at 390°C for 30s to form an ohmic contact with the N-type ohmic contact layer at the bottom of the epitaxial layer 2;

[0095] S11: depositing a passivation layer on the structure prepared in step S10 and etching windows at the second electrode 4 and the third electrode 5;

[0096] S12: Thin the wafer to 100-150μm, perform on-chip performance testing, and then perform chip cleavage and packaging.

[0097] The transmission rate eye diagram test of the high-speed vertical cavity surface emitting laser obtained in this embodiment is performed, and the results are as follows: Figure 5 As shown, from Figure 5 It can be seen that the 25 Gbit / s eye diagram of the high-speed VCSEL chip obtained in this embodiment is clearly opened, and the margin under its template is greater than 40%, and it has excellent optical signal transmission characteristics.

[0098] The above examples are used to illustrate the specific implementation of the present invention. However, the protection scope of the present invention is not limited to the above exemplary implementation. Any modification, equivalent substitution, improvement, etc. made by those skilled in the art within the spirit and principle of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A vertical cavity surface emitting laser, comprising a substrate, an epitaxial layer being arranged on the substrate, characterized in that: The epitaxial layer is provided with a first electrode, a second electrode, a first etched area, and a second etched area, wherein the first etched area and the second etched area are provided in the epitaxial layer, and the first etched area surrounds to form a truncated cone-shaped waveguide, and the first electrode is provided on the top of the truncated cone-shaped waveguide; the second etched area is connected to the first etched area, an organic polymer is provided inside the first etched area and the second etched area to form an organic polymer layer, and the second electrode is led out from the first electrode and extends to above the second etched area; The epitaxial layer includes an N-type ohmic contact layer, an N-DBR layer, an active region, an oxidation restriction layer, a P-DBR layer and a P-type ohmic contact layer arranged in sequence from bottom to top; The etching of the first etching area starts from the P-type ohmic contact layer, passes through the P-type DBR layer and the resonant cavity, and stops after entering the N-type DBR layer; The etching of the second etching area starts from the P-type ohmic contact layer, passes through the P-type DBR layer and the resonant cavity, and stops after entering the N-type DBR layer; The thickness of the organic polymer is ±1 um of the depth of the first etching area and the second etching area.

2. The vertical cavity surface emitting laser according to claim 1, characterized in that: The dielectric constant of the organic polymer layer is less than or equal to 3.

3. The vertical cavity surface emitting laser according to claim 1, characterized in that: The organic polymer is selected from one or more of BCB, PI, PR and PS.

4. The vertical cavity surface emitting laser according to claim 1, characterized in that: The first etching area and the second etching area have the same depth.

5. The vertical cavity surface emitting laser according to claim 1, characterized in that: The thickness of the organic polymer layer is 2-4 um.

6. The vertical cavity surface emitting laser according to any one of claims 1 to 5, characterized in that: The depth of the first etching area is 3.8-4.2 um.

7. The vertical cavity surface emitting laser according to any one of claims 1 to 5, characterized in that: The second etching region includes a main groove and a connecting groove. The main groove is connected with the first etching region through the connecting groove. The main groove is a circular groove.

8. The vertical cavity surface emitting laser according to any one of claims 1 to 5, characterized in that: The depth of the second etching area is 3-5 um.

9. A method for preparing the laser according to any one of claims 1 to 8, characterized in that: The following steps are involved: S1: growing an epitaxial layer on a substrate; S2: Disposing a first electrode on the surface of the epitaxial layer; S3: etching around the first electrode to form a first etching area; S4: etching next to the first etching region to form a second etching region; S5: filling the first etching area and the second etching area with an organic polymer; S6: Dispose a second electrode on the top of the second etched region.

10. The preparation method according to claim 9, characterized in that: The following steps are included between step S3 and step S4: wet oxidation is performed on the epitaxial layer to form oxidation limiting holes.

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