Timing Repair Method and System Based on Buffer Delay Data Fitting of Full-Chip Timing Report

Abstract

The present invention relates to the technical field of chip design, and provides a timing repair method for buffer delay data fitting based on a full-chip timing report. By reading the top-level timing report file including all path timing violation data, the corresponding unit boundary conditions in the top-level timing report file are extracted under different conditions, a linear fitting function of the unit boundary conditions and delay information is established, the unit boundary conditions and violation information corresponding to all target registers are extracted, and according to the binary function parameter group of the linear fitting function, the buffer type and delay information under different conditions are calculated, and a script file for engineering repair at each module level is generated. The present invention also discloses a system. This method and system can reduce invalid repeated iterative calculations during the chip design process, can quickly generate a script file for engineering repair, and is used for automatic repair of maintaining timing. It not only has high efficiency, is not prone to errors, but also improves the efficiency of timing repair during the entire chip design process.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and particularly to a timing repair method and system for buffer delay data fitting based on a full-chip timing report. Background Art

[0002] With the development of digital chip design technology, the complexity and integration of chips have been continuously improved, the design scale of chips has been continuously increased, and the frequency has been continuously increased. To address these challenges, designers need to divide the chip into more modules to better manage complexity and improve performance. The modular design method makes the design more controllable and makes parallel development and verification more convenient. By optimizing and analyzing the modules, the high-frequency requirements can be better met, and the reliability and maintainability of the chip can be improved.

[0003] As the number of modules in the chip is divided more and more, the requirements for high-quality timing signoff become more and more stringent. In the process of chip timing optimization, Fanout-Aware Least Slack determines the appropriate gate delay by considering the signal propagation path and driving ability to maximize the timing slack and meet the design requirements. The optimization of hold timing requires comprehensive consideration of timing analysis and constraints, logic optimization, hardware partitioning and routing, and clock optimization.

[0004] WO2022109873A1 discloses a timing margin determination method, device, test circuit system, and readable storage medium. Applied to a test circuit system, the test circuit system includes a first analog circuit and a delay introduction circuit. The first analog circuit is used to simulate the circuit in the first chip to be tested, and the delay introduction circuit is used to introduce timing delay for the first analog circuit. The method includes: receiving test configuration information; determining the current link to be tested in the first analog circuit according to the test configuration information; adjusting the current link to be tested, and / or introducing timing delay for the current link to be tested based on the delay introduction circuit to cause a timing violation in the first analog circuit; and determining the target timing margin of the current link to be tested when the current link to be tested has a timing violation.

[0005] CN110598235B discloses a method and system for repairing timing violations in chip design, including the following steps: step 100, after chip layout and routing, timing analysis is performed based on a timing analysis tool to obtain paths of all timing violations; step 200, sorting from large to small according to violation values, and selecting the path corresponding to the maximum violation value as the target repair path; step 300, capturing all basic units and their corresponding delay values on the data path of the aforementioned target repair path, sorting them according to the delay values, and selecting the basic units therein in sequence as target units according to the sorting; step 400, determining whether the violation of the aforementioned target repair path is a setup time violation or a hold time violation and repairing them respectively; during repair, the target units are replaced in sequence based on rules that do not affect other timing paths, until the timing converges or all target units are completely replaced, and all the above repair operations are obtained. ; Step 500, converting the above-mentioned repair operation into an operation command that can be recognized by the layout and routing tool, and performing the above-mentioned operation on the layout and routing tool based on this version of the layout and routing data; Step 600, verifying whether the timing analysis result after the above-mentioned operation meets the timing requirement, if not, returning to step 200, if satisfied, ending the repair; wherein, in the step 400, the method of replacing the target unit based on the rule that does not affect other timing paths is: in the case of a setup time violation, judging whether the hold time of all timing paths passing through the target unit in the fastest delay environment has a margin, and replacing the target unit if there is a margin, otherwise not replacing; in the case of a hold time violation, judging whether the setup time of all timing paths passing through the target unit in the slowest delay environment has a margin, and replacing the target unit if there is a margin, otherwise not replacing.

[0006] CN117494628A discloses a chip timing repair method, device, equipment and storage medium, including: in the engineering modification stage, obtaining a target chip block and a target system on chip; obtaining a target node in the target chip block as an output port, and establishing a two-level clock tree; connecting the output port to the clock end of the first trigger in the target system on chip through the two-level clock tree, and repairing the timing violation between the interface of the target chip block and the target system on chip through the two-level clock tree.

[0007] Since the optimization for hold timing often involves inserting buffers in advance at the boundaries of each module, violations that occur under all working conditions cannot be modified in a targeted manner. Such redundant design not only reduces the performance of the entire system, but also increases power consumption. Summary of the invention

[0008] Through long-term practice, it is found that for the optimization of the hierarchical module boundary timing, in the early stage of chip design, inserting buffers in advance at the boundaries of each module in the process can avoid a large number of violations to a certain extent, but it is difficult to ensure that the hold timing of this path meets the design requirements under all Process Voltage Temperature (PVT) conditions. An excessive amount of redundant design will also lead to a reduction in the overall system performance and an increase in power consumption. If manual inspection of the timing report is used to find the points on the path that need to be repaired, manually insert buffers, manually route wires, etc., it is time-consuming and laborious, error-prone, and cannot completely repair all technical problems such as hold timing violations.

[0009] In view of this, the present invention provides a timing repair method based on buffer delay data fitting of a full-chip timing report, including,

[0010] Step S1, reading a top-level timing report file including timing violation data of all paths, where the violation data at least includes path information, as well as the cell name, cell type, cell boundary conditions, and delay information of the device units on the path;

[0011] Step S2, according to the cell type, extracting the corresponding cell boundary conditions and the delay information in the top-level timing report file under different conditions, where the cell boundary conditions include the transition time of the input signal and the output load; the delay information is mapped to the corresponding cell boundary conditions in the form of a two-dimensional array variable;

[0012] Step S3, calling a linear fitting function, using the cell boundary conditions and the delay information in Step S2 as input data, and superimposing the linear fitting functions to output a binary function parameter group of the linear fitting function;

[0013] Step S4, extracting the cell boundary conditions and violation information corresponding to all target registers, and calculating the buffer type and delay information under different conditions according to the binary function parameter group of the linear fitting function to generate a script file for engineering repair at each module level.

[0014] Among them, the transition time of the input signal (input transition), that is, the time required for the signal to reach the termination point from the starting point, is usually used to measure the response speed of the circuit.

[0015] The output load (output load), that is, the load resistor or capacitor and other components connected to the output terminal of the circuit. The size of the output load will affect the output voltage and output current of the circuit, so the influence of the output load needs to be considered when designing the circuit.

[0016] The script file for engineering repair (Engineering Change Order, ECO), also known as the ECO script file.

[0017] Preferably, in step S4, it includes

[0018] Step S41, parsing and sorting the violation values of the target register under different modules, different conditions, and different paths;

[0019] Step S42, for all the target registers, calculating the corresponding delay values by using linear fitting parameters, and selecting multiple buffer types that meet different conditions according to the delay values;

[0020] Step S43, selecting the buffer type corresponding to the violation information in the worst - case condition;

[0021] Step S44, generating the buffer engineering repair script files at each module level.

[0022] Preferably, all path timing violation data includes the violation data of the device units at each module level in the chip.

[0023] Preferably, the device units include buffers, timing devices, NAND gate devices, and the timing devices include registers.

[0024] Preferably, the buffer types are different under different conditions, and the different conditions include process, voltage, and temperature conditions.

[0025] Preferably, inputting the script file for engineering repair into the corresponding buffer for timing repair.

[0026] The present invention also discloses a system for performing the above - mentioned timing repair method based on buffer delay data fitting of the full - chip timing report. The system includes

[0027] An acquisition module, configured to read the top - level timing report file including the timing violation data in all paths, where the violation data at least includes path information, and the unit name, unit type, unit boundary conditions, and delay information of the device units on the path;

[0028] A pre - processing module, configured to extract the corresponding unit boundary conditions and the delay information in the top - level timing report file under different conditions according to the unit type. The unit boundary conditions include the transition time of the input signal and the output load; the delay information is mapped to the corresponding unit boundary conditions in the form of a two - dimensional array variable;

[0029] A fitting module, configured to call a linear fitting function, use the unit boundary conditions and the delay information in step S2 as input data, perform superposition by using the linear fitting function, and output a binary function parameter group of the linear fitting function;

[0030] A repair module, configured to extract the unit boundary conditions and violation information corresponding to all target registers, calculate buffer types and delay information under different conditions according to the binary function parameter group of the linear fitting function, and generate a script file for engineering repair at each module level.

[0031] Preferably, the repair module includes

[0032] A parsing sub-module, configured to parse and sort the violation values of the target register under different modules, different conditions, and different paths;

[0033] A calculation sub-module, configured to calculate the corresponding delay values for all the target registers by using the linear fitting parameters, and select multiple buffer types that meet different conditions according to the delay values;

[0034] A screening sub-module, configured to select the buffer type corresponding to the violation information in the worst-case condition;

[0035] A repair file generation module, configured to generate a buffer engineering repair script file at each module level.

[0036] The present invention further provides an electronic device, including at least one processor; and a memory communicatively connected to the at least one processor; wherein,

[0037] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can execute the above-mentioned timing repair method for fitting buffer delay data based on a full-chip timing report.

[0038] The present invention further provides a machine-readable storage medium, on which instructions are stored, and the instructions are used to enable a machine to execute the above-mentioned timing repair method for fitting buffer delay data based on a full-chip timing report of the present application.

[0039] Compared with the prior art, the present invention, through steps S1 - S4, reads the top - level timing report file including all path timing violation data, and according to the unit type, extracts the corresponding unit boundary conditions in the top - level timing report file under different conditions, including the transition time of the input signal and the output load; maps the delay information to the corresponding unit boundary conditions in the form of a two - dimensional array variable, calls the linear fitting function, and can establish a linear fitting function between the unit boundary conditions and the delay information, and outputs the binary function parameter group in the linear fitting function. Finally, extracts the unit boundary conditions and violation information corresponding to all target registers, calculates the buffer type and delay information under different conditions according to the binary function parameter group of the linear fitting function, and generates the engineering repair script files at each module level. The present invention also discloses a system. This method and system can, during the chip design process, obtain the violation data within the global scope, calculate the delay information by data fitting for the target registers under different process, voltage, and temperature conditions, and select the appropriate buffer type, reducing the ineffective repeated iterative calculations, and can quickly generate the engineering repair script files for the automatic repair of maintaining the timing. It is not only highly efficient but also not prone to errors, improving the efficiency of timing repair in the entire chip design process.

[0040] Other features and advantages of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which form a part of the present invention, are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0042] Figure 1 It is a schematic diagram of a timing repair method for buffer delay data fitting based on the full - chip timing report according to an embodiment of the present invention;

[0043] Figure 2 It is a flowchart of a timing repair method for buffer delay data fitting based on the full - chip timing report according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] The following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0045] To enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0046] It should be noted that the terms "first", "second", "third", etc. in the specification and claims of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to implement the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0047] In the prior art, for the optimization of the hierarchical module boundary timing, in the early stage of chip design, buffers are inserted in advance at the boundaries of each module in the process, which can avoid a large number of violations to a certain extent, but it is difficult to ensure that the hold timing of this path meets the design requirements under all process-voltage-temperature (PVT) conditions. A sufficient amount of redundant design will also lead to a reduction in the overall system performance and an increase in power consumption. If manual inspection of the timing report is used to find the points on the path that need to be repaired, manually insert buffers, manually route wires, etc., it is time-consuming and laborious, error-prone, and cannot completely repair all hold timing violations and other technical problems. As Figure 1-2 shown, the present invention provides a timing repair method based on buffer delay data fitting of a full-chip timing report. The timing repair method based on buffer delay data fitting of a full-chip timing report includes

[0048] Step S1, reading a top-level timing report file including all path timing violation data, where the violation data at least includes path information, and the cell name, cell type, cell boundary conditions, and delay information of the device units on the path;

[0049] Step S2: According to the unit type, extract the corresponding unit boundary conditions and delay information in the top-level timing report file under different conditions. The unit boundary conditions include the transition time of the input signal and the output load. The delay information is mapped to the corresponding unit boundary conditions in the form of a two-dimensional array variable.

[0050] Step S3: Call a linear fitting function, use the unit boundary conditions and the delay information in Step S2 as input data, and perform linear fitting function superposition to output a binary function parameter group of the linear fitting function.

[0051] Step S4: Extract the unit boundary conditions and violation information corresponding to all target registers, calculate the buffer type and delay information under different conditions according to the binary function parameter group of the linear fitting function, and generate a script file for engineering repair at each module level.

[0052] Through Steps S1 - S4, the present invention reads the top-level timing report file including all path timing violation data, extracts the corresponding unit boundary conditions in the top-level timing report file under different conditions according to the unit type, including the transition time of the input signal and the output load; maps the delay information to the corresponding unit boundary conditions in the form of a two-dimensional array variable, and calls a linear fitting function to establish a linear fitting function of the unit boundary conditions and the delay information, and output the binary function parameter group in the linear fitting function. Finally, extract the unit boundary conditions and violation information corresponding to all target registers, calculate the buffer type and delay information under different conditions according to the binary function parameter group of the linear fitting function, and generate a script file for engineering repair at each module level. It is used to identify the most serious timing violations, predict the circuit delay under different conditions, and select appropriate buffers to repair these violations, and finally generate a repair plan to meet the timing requirements. This method can, during the chip design process, obtain violation data within the global scope, calculate the delay information by data fitting for target registers under different process, voltage, and temperature conditions, and select the appropriate buffer type, reducing ineffective repeated iterative calculations, being able to quickly generate a script file for engineering repair for automatic repair of timing, not only being highly efficient but also not prone to errors, improving the efficiency of timing repair in the entire chip design process.

[0053] During the static timing analysis (STA) of chip design, for the paths with violation information of hold timing, it is necessary to solve the problem by increasing the delay of these paths, which is achieved by inserting buffers, increasing logic gate delays, or adjusting wiring. To better identify and fix these violations, so as to ensure that the chip can operate normally under various working conditions. In the preferred case of the present invention, step S4 includes,

[0054] Step S41, parsing the violation values of the target registers under different modules, different conditions, and different paths and sorting them;

[0055] Step S42, for all the target registers, calculating the corresponding delay values by using linear fitting parameters, and selecting multiple buffer types that meet different conditions according to the delay values;

[0056] Step S43, selecting the buffer type corresponding to the violation information in the worst-case scenario;

[0057] Step S44, generating buffer engineering repair script files at each module level.

[0058] In step S41, identify the timing violations of specific registers under different design modules, working conditions, and signal transmission paths. The violation value represents the degree to which the timing requirements are not met, usually the difference between the actual delay and the target delay. Sorting these violation values helps to determine which violations are the most serious and have the highest priority and should be solved first.

[0059] Use linear fitting or other mathematical models, such as neural network models, to predict the signal delays under different working conditions. According to these delay values, select appropriate buffer types for each target register. Buffers can adjust the signal strength and increase or decrease the delay to meet the timing requirements. This step involves selecting appropriate buffer types for the registers under different working conditions (such as process, temperature, voltage changes).

[0060] Among all working conditions, pay special attention to the violation information in the worst-case scenario, which is usually a standard practice in the design and verification processes. The worst case usually refers to the most unfavorable working conditions (such as the highest temperature, the lowest voltage, etc.), under which the circuit performance is the worst. Select the buffer type that can repair the violations under these conditions to ensure that the circuit does not violate the timing under any conditions.

[0061] During the timing analysis process, detailed information about all violations is collected, including violation types (such as setup or hold violations), violation values, violation paths, module information, and the conditions under which the violations occur. To traverse the violation information in the entire chip more globally and completely, in a preferred embodiment of the present invention, the timing violation data in all paths includes the violation data of the device units at each module level in the chip. The timing violation data is screened and extracted according to the module to which it belongs, the specific conditions under which it occurs (such as different process, voltage, temperature conditions PVT, or different modes or clock domains), and the types of violation paths. For each violation path, the violation value is calculated, which is the difference between the actual path delay and the required delay. For a setup violation, the violation value is the required time minus the actual path delay; for a hold violation, the violation value is the actual path delay minus the required time. The collected violations are sorted according to their violation values, generally starting from the largest violation value, because this indicates the most serious timing violation.

[0062] To better repair the timing of different device units during the chip design process, in a preferred embodiment of the present invention, the device units include buffers, timing devices, and NAND gate devices, and the timing devices include registers. A buffer is used in digital circuits to enhance the driving ability of a signal. It helps the signal to be transmitted over a long line without attenuation, or prevents the signal from decreasing in the case of being connected to multiple inputs. In timing analysis, a buffer is used to adjust the path delay to help meet the timing requirements. By selecting different buffer types and sizes, the delay on the signal path can be increased or decreased to solve the timing violation. Timing devices are devices related to timing control, such as registers. A register is a storage device used to store and transmit data in each clock cycle. They play a key role in determining the data flow and processing, and are an important part of timing analysis. Timing devices ensure data synchronization and maintain the stability of data when a specific clock edge arrives, which is crucial for avoiding timing violations. NAND gate devices, the NAND gate is one of the basic logic gates and is used to implement the logical NAND operation in digital circuits. It accepts two or more input signals. If all inputs are "high" (1), the output is "low" (0); if at least one input is "low" (0), the output is "high" (1). NAND gates are combined into more complex logic functions in digital logic design, such as inverters, AND gates, OR gates, etc.

[0063] During the chip design process, different process, voltage, and temperature conditions have a significant impact on the performance of the circuit. To ensure that the circuit can operate reliably under all operating conditions, a buffer type suitable for these conditions is selected. For example, process variations may cause the transistors to be faster or slower, which affects the circuit's delay time. A buffer type that can adapt to these process variations needs to be selected to ensure that the circuit can meet the timing requirements even under the slowest process conditions. In the preferred case of the present invention, the buffer types are different under different conditions, and the different conditions include process, voltage, and temperature conditions. For example, when the voltage is low, the transistor switching speed slows down, resulting in an increase in the circuit's delay; conversely, when the voltage is high, the transistor switching speed speeds up, and the delay decreases. An increase in temperature causes a decrease in the carrier mobility of the transistor, thereby increasing the delay; while a decrease in temperature may increase the carrier mobility and reduce the delay.

[0064] Analyze and select the buffer type, and generate specific engineering repair solutions for each module, including specifying the insertion or replacement of buffers at specific locations in the circuit, or adjusting the parameters of existing buffers. The repair solutions are usually customized for each module because different modules may face different timing requirements and operating conditions. In the preferred case of the present invention, the script file of the engineering repair is input into the corresponding buffer for timing repair.

[0065] The present invention also discloses a system for performing the above-described timing repair method for buffer delay data fitting based on the full-chip timing report. The system includes,

[0066] An acquisition module for reading a top-level timing report file including all path timing violation data, where the violation data at least includes path information, as well as the cell name, cell type, cell boundary conditions, and delay information of the device units on the path;

[0067] A preprocessing module for extracting the corresponding cell boundary conditions and delay information in the top-level timing report file under different conditions according to the cell type. The cell boundary conditions include the transition time of the input signal and the output load; the delay information is mapped to the corresponding cell boundary conditions in the form of a two-dimensional array variable;

[0068] A fitting module for calling a linear fitting function, using the cell boundary conditions and delay information in step S2 as input data, and superimposing the linear fitting functions to output a binary function parameter group of the linear fitting function;

[0069] A repair module for extracting the cell boundary conditions and violation information corresponding to all target registers, calculating the buffer type and delay information under different conditions according to the binary function parameter group of the linear fitting function, and generating a script file for engineering repair at each module level.

[0070] This system reads the top-level timing report file including all path timing violation data through an acquisition module. The preprocessing module extracts the corresponding unit boundary conditions in the top-level timing report file according to the unit type under different conditions, including the transition time of the input signal and the output load; maps the delay information to the corresponding unit boundary conditions in the form of a two-dimensional array variable. The fitting module calls a linear fitting function to establish a linear fitting function between the unit boundary conditions and the delay information, and outputs the binary function parameter group in the linear fitting function. The repair module extracts the unit boundary conditions and violation information corresponding to all target registers, calculates the buffer type and delay information under different conditions according to the binary function parameter group of the linear fitting function, and generates a script file for engineering repair at each module level. It is used to identify the most serious timing violations, predict the circuit delay under different conditions, and select appropriate buffers to repair these violations, and finally generate a repair plan to meet the timing requirements. This system can, during the chip design process, obtain violation data within the global scope, calculate the delay information through data fitting for target registers under different processes, voltages, and temperature conditions, and select appropriate buffer types, reducing ineffective repeated iterative calculations, and can quickly generate a script file for engineering repair for automatic repair of timing, which is not only highly efficient but also less error-prone, improving the efficiency of timing repair in the entire chip design process.

[0071] To better identify and repair these violations to ensure that the chip can operate normally under various working conditions, identify the timing violations of specific registers under different design modules, working conditions, and signal transmission paths. In the preferred case of the present invention, the repair module includes

[0072] A parsing sub-module for parsing and sorting the violation values of the target register under different modules, different conditions, and different paths;

[0073] A calculation sub-module for calculating the corresponding delay values for all the target registers using the linear fitting parameters, and selecting multiple buffer types that meet different conditions according to the delay values;

[0074] A screening sub-module for selecting the buffer type corresponding to the violation information in the worst-case scenario;

[0075] A repair file generation module for generating a buffer engineering repair script file at each module level.

[0076] The present invention also provides an electronic device, at least one processor; and

[0077] A memory communicatively connected to the at least one processor; wherein,

[0078] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the above-mentioned method.

[0079] The present invention also provides a machine-readable storage medium, on which instructions are stored for causing a machine to execute the method as described above in this application.

[0080] It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0081] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0082] In several embodiments provided by the present invention, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical or other forms.

[0083] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0084] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0085] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a mobile terminal, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical discs.

[0086] The foregoing are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A timing repair method based on buffer delay data fitting of the full-chip timing report, characterized in that The timing repair method based on buffer delay data fitting of the full-chip timing report includes: Step S1, read the top-level timing report file including timing violation data in all paths, where the violation data at least includes path information, as well as the cell name, cell type, cell boundary conditions, and delay information of the device cells on the path; Step S2, according to the cell type, extract the corresponding cell boundary conditions and the delay information in the top-level timing report file under different conditions. The cell boundary conditions include the transition time of the input signal and the output load; the delay information is mapped to the corresponding cell boundary conditions in the form of a two-dimensional array variable, where the buffer types are different under different conditions, and different conditions include process, voltage, and temperature conditions; Step S3, call the linear fitting function, use the cell boundary conditions and the delay information in Step S2 as input data, and superimpose the linear fitting functions to output the binary function parameter group of the linear fitting function; Step S4, extract the cell boundary conditions and violation information corresponding to all target registers, and calculate the buffer types and delay information under different conditions according to the binary function parameter group of the linear fitting function, and generate the engineering repair script file at each module level.

2. The timing repair method based on fitting buffer delay data of the full-chip timing report according to claim 1, characterized in that In Step S4, it includes: Step S41, parse the violation values of the target registers under different modules, different conditions, and different paths and sort them; Step S42, for all the target registers, calculate the corresponding delay values using the linear fitting parameters, and select multiple buffer types that meet different conditions according to the delay values; Step S43, select the buffer type corresponding to the violation information in the worst-case condition; Step S44, generate the buffer engineering repair script file at each module level.

3. The timing repair method based on buffer delay data fitting of the full-chip timing report according to claim 1, wherein All path timing violation data includes the violation data of the device cells at each module level in the chip.

4. The timing repair method for buffer delay data fitting based on the full-chip timing report according to claim 3, characterized in that The device cells include buffers, timing devices, and NAND gate devices, and the timing devices include registers.

5. The timing repair method based on buffer delay data fitting of the full-chip timing report according to any one of claims 1-4, characterized in that, Input the engineering repair script file into the corresponding buffer for timing repair.

6. A system for performing a timing repair method of buffer delay data fitting based on a full-chip timing report according to any one of claims 1-5, characterized in that, The system includes: An acquisition module, used to read the top-level timing report file including timing violation data in all paths, where the violation data at least includes path information, as well as the cell name, cell type, cell boundary conditions, and delay information of the device cells on the path; A preprocessing module, used to extract the corresponding cell boundary conditions and the delay information in the top-level timing report file under different conditions according to the cell type. The cell boundary conditions include the transition time of the input signal and the output load; the delay information is mapped to the corresponding cell boundary conditions in the form of a two-dimensional array variable, where the buffer types are different under different conditions, and different conditions include process, voltage, and temperature conditions; A fitting module, used to call the linear fitting function, use the cell boundary conditions and the delay information in Step S2 as input data, and superimpose the linear fitting functions to output the binary function parameter group of the linear fitting function; A repair module, configured to extract the cell boundary conditions and violation information corresponding to all target registers, calculate buffer types and delay information under different conditions according to the binary function parameter group of the linear fitting function, and generate a script file for engineering repair at each module level.

7. The system according to claim 6, characterized in that, The repair module includes a parsing sub-module, configured to parse and sort the violation values of the target registers under different modules, different conditions, and different paths; a calculation sub-module, configured to calculate the corresponding delay values for all the target registers by using linear fitting parameters, and select multiple buffer types that meet different conditions according to the delay values; a screening sub-module, configured to select the buffer type corresponding to the violation information in the worst-case condition; a repair file generation module, configured to generate a buffer engineering repair script file at each module level.

8. An electronic device, characterized in that, at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the timing repair method for buffer delay data fitting based on the full-chip timing report according to any one of claims 1-5.

9. A machine-readable storage medium, characterized in that, Instructions are stored on the machine-readable storage medium, and the instructions are used to cause the machine to execute the timing repair method for buffer delay data fitting based on the full-chip timing report according to any one of claims 1-5 of the present application.

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