Super junction device and manufacturing method thereof

Abstract

The present invention discloses a superjunction device, wherein the superjunction structure is formed in a first epitaxial layer and is composed of a plurality of alternating first conductivity type columns and second conductivity type columns. The first epitaxial layer at the bottom of the superjunction structure constitutes a buffer layer. The second conductivity type column is composed of a second conductivity type epitaxial layer filled in a superjunction trench. The superjunction trench has a first width and a first depth, the buffer layer has a second thickness, and the sum of the first depth and the second thickness is equal to the thickness of the first epitaxial layer. The second doping concentration varies within a filling process window of the second conductivity type epitaxial layer. While keeping the thickness of the first epitaxial layer unchanged, the aspect ratio and the second thickness of the superjunction trench are set according to the filling process window, so that at the second doping concentration minimum and the second doping concentration maximum corresponding to the filling process window, the breakdown voltage of the superjunction device is greater than or equal to the rated breakdown voltage. The present invention also discloses a method for manufacturing a superjunction device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a super junction device; the present invention also relates to a method for manufacturing the super junction device. Background Art

[0002] Superjunction devices, such as superjunction MOSFETs, are based on existing VDMOS devices by inserting lateral P-type pillars into the vertical drift region. By utilizing the lateral depletion of the P-type pillars and the N-type drift region, the doping concentration of the drift region can be significantly increased without reducing the breakdown voltage, thus breaking the one-dimensional theoretical limit of silicon devices and achieving lower specific on-resistance. More importantly, the limit value of the specific on-resistance of superjunction devices is proportional to the P-type pillar (P pillar).

[0003] The closer the distance between the P-type pillars, the lower the specific on-resistance of the super-junction device. This provides a direction for continuously optimizing device performance.

[0004] Currently, there are two main methods for realizing the P-type column of super junction structure:

[0005] One is based on multiple epitaxy, and the other is based on deep trench etching and P-type silicon filling. Both technologies are currently mainstream in the market.

[0006] Super junction power devices are widely used in power conversion circuits due to their high breakdown voltage and low on-resistance. The structure of a typical super junction power device is as follows: Figure 1 As shown, taking N-type superjunction MOSFET as an example, existing superjunction devices include:

[0007] Super junction power devices are widely used in power conversion circuits due to their high breakdown voltage and low on-resistance. The structure of a typical super junction power device is as follows: Figure 1 As shown, taking N-type superjunction MOSFET as an example, existing superjunction devices include:

[0008] The N+ doped semiconductor substrate is, for example, a silicon substrate 101 , which is thinned to serve as a drain region.

[0009] An N-type epitaxial layer 102 is formed on the surface of the silicon substrate 101 .

[0010] The P-type pillars 103 are composed of a P-type epitaxial layer filled in the superjunction trench. The N-type epitaxial layer 102 between the P-type pillars 103 forms N-type pillars, and the P-type pillars 103 and N-type pillars are alternately arranged to form a superjunction structure.

[0011] The remaining N-type epitaxial layer 102 at the bottom of the super junction structure forms an N-type buffer layer 102a. Figure 1The bottom surface of the superjunction structure is marked with a dotted line, and the N-type epitaxial layer 102 at the bottom of the dotted line is a buffer layer marked with a mark 102 a .

[0012] A channel region 104 composed of a P-type well is formed in the top region of the P-type pillar 103 and extends to the top region of the N-type pillar.

[0013] The N-type epitaxial layer 102 at the bottom of the channel region 104 constitutes a drift region.

[0014] Figure 1 The gate structure is a planar gate, including a gate dielectric layer 107 and a polysilicon gate 108 stacked in sequence. The surface of the channel region 104 covered by the polysilicon gate 108 is used to form a conductive channel.

[0015] Source regions 105 composed of N+ regions are self-alignedly formed on the surface of the channel region 104 on both sides of the polysilicon gate 108 .

[0016] A body lead region 106 composed of a P+ region is also formed on the surface of the channel region 104 .

[0017] The top of the source region 105 and the body lead region 106 are connected to the source 109 composed of the front metal layer through the same contact hole. The top of the polysilicon gate 108 is connected to the gate composed of the front metal layer through the corresponding contact hole.

[0018] A drain electrode composed of a back metal layer 110 is formed on the back side of the drain region.

[0019] In the off state, the gate voltage is 0V, the channel region 104 under the polysilicon gate 108 cannot form an inversion layer, and no conductive channel is generated. The P-type column 103 and the N-type column form a reverse-biased PN junction, and the P-type column 103 and the N-type column deplete each other. In an ideal state, when the P-type impurities and N-type impurities are completely balanced, the breakdown voltage (BVdss) of the device is independent of the resistivity of the N-type epitaxial layer 102.

[0020] Therefore, superjunction devices can have both high breakdown voltage and very low specific on-resistance.

[0021] In the on state, the gate voltage is greater than the threshold voltage, and the channel region 104 below the polysilicon gate 108 forms an N-type inversion layer, generating a conductive channel. Because the N-type epitaxial layer 102 is highly doped, it has a low specific on-resistance.

[0022] In existing superjunction fabrication processes for trench-filled P-type pillars (P pillars), the superjunction trench depth must be increased to improve the superjunction structure's withstand voltage, while simultaneously increasing the doping concentration of the N-type epitaxial layer 102 to reduce on-resistance. However, increasing the superjunction trench depth increases the difficulty of filling the P-type epitaxial layer that forms the P-type pillars 103, as well as the difficulty of maintaining a stable doping concentration in the P-type epitaxial layer of the P-type pillars 103. Furthermore, increasing the doping concentration of the N-type epitaxial layer 102 further increases the difficulty of maintaining a stable doping concentration in the P-type epitaxial layer of the P-type pillars 103.

[0023] In addition, when the depth of the super junction trench is deepened, in addition to the adverse effect on the stability control of the doping concentration of the P-type epitaxial layer of the P-type column 103, it is also easy to cause holes to appear in the P-type epitaxial layer of the P-type column 103 during filling, thereby affecting the quality of the P-type column 103 and ultimately affecting the quality of the device.

[0024] At the same time, when the thickness of the N-type epitaxial layer 102 remains constant, the depth of the super junction trench increases, which will inevitably reduce the thickness of the N-type buffer layer at the bottom, which will affect the impact resistance of the device. Summary of the Invention

[0025] The technical problem to be solved by the present invention is to provide a superjunction device that can increase the filling process window for the second conductivity type pillars filling the superjunction trench and achieve the maximum filling process window under the condition that the thickness of the epitaxial layer corresponding to the drift region is constant. To this end, the present invention also provides a method for manufacturing the superjunction device.

[0026] To solve the above technical problems, the present invention provides a super junction device comprising a super junction structure formed in a first epitaxial layer doped with a first conductivity type, wherein the first epitaxial layer at the bottom of the super junction structure constitutes a buffer layer.

[0027] The super junction structure is composed of a plurality of first conductivity type columns and second conductivity type columns that are alternately arranged.

[0028] The second conductive type column is composed of a second conductive type epitaxial layer filled in the super junction trench.

[0029] The first conductive type pillars are composed of the first epitaxial layer between the second conductive type pillars.

[0030] The super junction trench has a first width and a first depth, the buffer layer has a second thickness, the sum of the first depth and the second thickness is equal to the thickness of the first epitaxial layer, and the aspect ratio of the super junction trench is the ratio of the first depth to the first width.

[0031] The first doping concentration of the first conductive type column matches the second doping concentration of the second conductive type column; the second doping concentration varies within a filling process window of the second conductive type epitaxial layer.

[0032] Under the condition of keeping the thickness of the first epitaxial layer unchanged, the aspect ratio and the second thickness of the super junction trench are set according to the filling process window, so that at the second doping concentration minimum and the second doping concentration maximum corresponding to the filling process window, the breakdown voltage of the super junction device is greater than or equal to the rated breakdown voltage, so as to ensure that the breakdown voltage of the super junction device is greater than or equal to the rated breakdown voltage when the second doping concentration changes within the filling process window, and the second thickness meets the requirements of the avalanche breakdown resistance of the super junction device.

[0033] A further improvement is that the aspect ratio of the super junction trench is set according to the maximum filling process window, so as to increase the filling process window.

[0034] A further improvement is that the aspect ratio of the super junction trench and the second thickness are selected from multiple sets of experimental values.

[0035] In each group of experimental values, by changing the experimental value of the aspect ratio and the experimental value of the second thickness of the super junction trench, a first curve of the breakdown voltage of the corresponding super junction device as the second doping concentration changes is obtained, and the variation range of the second doping concentration above the rated breakdown voltage in each of the first curves is compared, and the experimental value of the aspect ratio of the super junction trench corresponding to the first curve with the largest variation range of the second doping concentration is selected as the aspect ratio of the super junction trench and the second thickness experimental value is selected as the second thickness.

[0036] A further improvement is that the operating voltage of the super junction device is 450V to 550V, and the rated breakdown voltage is greater than or equal to the operating voltage of the super junction device.

[0037] A further improvement is that the aspect ratio of the super junction trench is 7.8 to 8.8.

[0038] A further improvement is that the second thickness is 8 microns to 10 microns.

[0039] A further improvement is that the super junction device is formed by multiple device unit structures connected in parallel, each of the device unit structures is formed on a corresponding super junction unit, and each of the super junction units is composed of a first conductive type column and its adjacent second conductive type column.

[0040] Each of the device unit structures includes a gate structure, a channel region and a source region.

[0041] A further improvement is that the super junction device is a super junction MOSFET, and a drain region heavily doped with the first conductivity type is formed on the back side of the buffer layer.

[0042] To solve the above technical problems, the present invention provides a method for manufacturing a super junction device, comprising the following steps:

[0043] Step 1: providing a first epitaxial layer doped with a first conductivity type.

[0044] Step 2: forming a super junction trench in a selected region of the first epitaxial layer, with the first epitaxial layer at the bottom of the super junction trench serving as a buffer layer.

[0045] The super junction trench has a first width and a first depth, the buffer layer has a second thickness, the sum of the first depth and the second thickness is equal to the thickness of the first epitaxial layer, and the aspect ratio of the super junction trench is the ratio of the first depth to the first width.

[0046] Step three: filling the super junction trench with a second conductive type epitaxial layer to form second conductive type pillars, and forming first conductive type pillars with the first epitaxial layer between the second conductive type pillars.

[0047] A super junction structure is formed by a plurality of alternately arranged first conductive type columns and second conductive type columns.

[0048] The first doping concentration of the first conductive type column matches the second doping concentration of the second conductive type column; the second doping concentration varies within a filling process window of the second conductive type epitaxial layer.

[0049] Under the condition of keeping the thickness of the first epitaxial layer unchanged, the aspect ratio and the second thickness of the super junction trench in step 2 are pre-set according to the filling process window, so that at the second doping concentration minimum and the second doping concentration maximum corresponding to the filling process window, the breakdown voltage of the super junction device is greater than or equal to the rated breakdown voltage, to ensure that the breakdown voltage of the super junction device is greater than or equal to the rated breakdown voltage when the second doping concentration changes within the filling process window, and the second thickness meets the requirements of the avalanche breakdown resistance of the super junction device.

[0050] A further improvement is that the aspect ratio of the super junction trench is set according to the maximum filling process window, so as to increase the filling process window.

[0051] A further improvement is that the aspect ratio of the super junction trench and the second thickness are selected from multiple sets of experimental values, and the step of selecting the aspect ratio of the super junction trench and the second thickness includes:

[0052] A plurality of sets of experimental values ​​for the aspect ratio and the second thickness of the super junction trench are set.

[0053] For each group of experimental values ​​of the aspect ratio and the second thickness of the super junction trench, the second doping concentration is changed and the breakdown voltage of the super junction device is measured to obtain a first curve of the breakdown voltage of the corresponding super junction device changing with the second doping concentration.

[0054] Compare the variation ranges of the second doping concentration above the rated breakdown voltage in each of the first curves and select the experimental value of the aspect ratio of the super junction trench corresponding to the first curve with the largest variation range of the second doping concentration as the aspect ratio of the super junction trench and the experimental value of the second thickness as the second thickness.

[0055] A further improvement is that the operating voltage of the super junction device is 450V to 550V, and the rated breakdown voltage is greater than or equal to the operating voltage of the super junction device.

[0056] A further improvement is that the aspect ratio of the super junction trench is 7.8 to 8.8.

[0057] A further improvement is that the second thickness is 8 microns to 10 microns.

[0058] Further improvements include:

[0059] A device unit structure is formed on the top of each super junction unit; each super junction unit is composed of a first conductive type column and its adjacent second conductive type column; the super junction device is formed by connecting multiple device unit structures in parallel, and each device unit structure includes a gate structure, a channel region and a source region.

[0060] A further improvement is that the super junction device is a super junction MOSFET.

[0061] After the front side process is completed, the following back side processes are also included:

[0062] A drain region heavily doped with the first conductivity type is formed on the back side of the buffer layer.

[0063] Unlike the prior art method of increasing the breakdown voltage of the device by increasing the depth of the super junction structure and increasing the aspect ratio of the super junction trench, the present invention takes into account the problem that it is difficult to control the doping concentration of the second conductive type epitaxial layer used to form the second conductive type column when filling the super junction trench. Under the condition that the thickness of the epitaxial layer corresponding to the drift region, that is, the first epitaxial layer, is constant, the aspect ratio of the super junction trench and the bottom buffer layer are optimized. This optimization is set according to the filling process window of the second conductive type epitaxial layer. In this way, it can be ensured that when the doping concentration of the second conductive type epitaxial layer changes due to fluctuations in the filling process itself, the actual concentration of the second conductive type epitaxial layer finally formed can make the breakdown voltage of the device greater than the rated breakdown voltage. Therefore, the present invention can reduce the restrictions on the filling process window of the second conductive type epitaxial layer, thereby increasing the filling process window of the second conductive type column filling the super junction trench, thereby reducing the difficulty of controlling the doping concentration of the second conductive type epitaxial layer, and can obtain the maximum filling process window under the condition that the thickness of the epitaxial layer corresponding to the drift region is constant.

[0064] Since the depth of the super junction trench is deeper and the aspect ratio is larger, the difficulty of filling the second conductive type epitaxial layer increases. In addition to the increased difficulty in controlling the doping concentration, voids can also be easily formed. Therefore, unlike the prior art which simply increases the aspect ratio of the super junction trench, the aspect ratio of the super junction trench of the present invention is actually set within a range smaller than the aspect ratio of the super junction trench of the existing super junction device. This is obviously beneficial to reducing the number of voids and improving the filling quality of the second conductive type epitaxial layer.

[0065] At the same time, under the condition that the thickness of the first epitaxial layer is constant, after the depth of the super junction trench is reduced, the thickness of the corresponding buffer layer will increase, which can further improve the device's ability to resist avalanche breakdown. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0067] Figure 1 It is a schematic diagram of the structure of an existing super junction device;

[0068] Figure 2 1 is a schematic structural diagram of a super junction device according to an embodiment of the present invention;

[0069] Figure 3A This is the curve of the breakdown voltage of the existing super junction device changing with the doping concentration of the P-type column;

[0070] Figure 3B 1 is a curve showing a change in breakdown voltage of a super junction device according to an embodiment of the present invention as a function of doping concentration of a P-type column;

[0071] Figure 43 is a curve showing the variation of the breakdown voltage with the doping concentration of the P-type column corresponding to multiple sets of experimental values ​​used in the super junction device according to the embodiment of the present invention. DETAILED DESCRIPTION

[0072] like Figure 2 FIG. 1 is a schematic diagram of the structure of a super junction device according to an embodiment of the present invention. The super junction device according to an embodiment of the present invention includes:

[0073] A super junction structure is formed in the first epitaxial layer 202 doped with the first conductivity type, and the first epitaxial layer 202 at the bottom of the super junction structure constitutes a buffer layer 202 a. Figure 2 In FIG, the bottom surface of the super junction structure is shown as the dotted line AA.

[0074] The super junction structure is composed of a plurality of first conductivity type pillars and second conductivity type pillars 204 arranged alternately.

[0075] The second conductive type pillar 204 is composed of a second conductive type epitaxial layer filled in the super junction trench 203 .

[0076] The first conductive type pillars are composed of the first epitaxial layer 202 between the second conductive type pillars 204 .

[0077] The super junction trench 203 has a first width and a first depth, the buffer layer 202a has a second thickness, the sum of the first depth and the second thickness is equal to the thickness of the first epitaxial layer 202, and the aspect ratio of the super junction trench 203 is the ratio of the first depth to the first width.

[0078] The first doping concentration of the first conductivity type column matches the second doping concentration of the second conductivity type column 204; the second doping concentration varies within a filling process window for the second conductivity type epitaxial layer. That is, due to production process fluctuations, even if the process conditions set when achieving the second doping concentration remain the same, the second doping concentration may also fluctuate due to the production process. However, the second doping concentration may vary within the filling process window.

[0079] Under the condition of keeping the thickness of the first epitaxial layer 202 unchanged, the aspect ratio and the second thickness of the super junction trench 203 are set according to the filling process window, so that at the second doping concentration minimum value and the second doping concentration maximum value corresponding to the filling process window, the breakdown voltage of the super junction device is greater than or equal to the rated breakdown voltage, so as to ensure that the breakdown voltage of the super junction device is greater than or equal to the rated breakdown voltage when the second doping concentration changes within the filling process window, and the second thickness meets the requirements of the avalanche breakdown resistance of the super junction device.

[0080] In the embodiment of the present invention, the super junction device is formed by connecting a plurality of device unit structures in parallel, each of which is formed on a corresponding super junction unit, and each super junction unit is composed of a first conductive type column and an adjacent second conductive type column 204. Figure 2 Only one second conductive type column 204 is shown.

[0081] Each of the device unit structures includes a gate structure (not shown), a channel region 205 and a source region 206 .

[0082] The gate structure adopts a planar gate or a trench gate, including a gate conductive material layer such as a polysilicon gate, with a gate dielectric layer between the polysilicon gate and the corresponding channel region 205, and the surface of the channel region 205 covered by the polysilicon gate is used to form a conductive channel.

[0083] A contact hole is formed on the top of the source region 206 and connected to the source electrode formed by the front metal layer through the contact hole. A body lead region 207 heavily doped with the second conductivity type is also formed at the bottom of the contact hole on the top of the source region 206, and the body lead region 207 is also connected to the source electrode through the contact hole on the top.

[0084] The superjunction device is a superjunction MOSFET, and a drain region 201 heavily doped with the first conductivity type is formed on the back side of the buffer layer 202a. In an embodiment of the present invention, the first epitaxial layer 202 is formed on the surface of a semiconductor substrate heavily doped with the first conductivity type, such as a silicon substrate, and the drain region 201 is formed by thinning the back side of the semiconductor substrate, or is formed by performing back side ion implantation heavily doped with the first conductivity type into the thinned back side of the semiconductor substrate.

[0085] In the embodiment of the present invention, the superjunction device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, and the second conductivity type pillar 204 is a P-type pillar. In other embodiments, the superjunction device may be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0086] In order to more clearly illustrate the super junction device according to the embodiment of the present invention, a further description is given below with reference to a set of specific parameters:

[0087] The operating voltage of the super junction device is 450V to 550V, and the rated breakdown voltage is greater than or equal to the operating voltage of the super junction device.

[0088] The aspect ratio of the super junction trench 203 is 7.8-8.8.

[0089] The second thickness is 8 micrometers to 10 micrometers.

[0090] In existing super junction devices, the aspect ratio and depth of the super junction trench do not take into account the role of the filling process window. The super junction trench is often set as follows: Figure 2 The structure shown in the dotted box 203a has a deeper depth and a larger aspect ratio; at this time, when the second doping concentration changes within a smaller range, it is easy to make the breakdown voltage of the device lower than the rated breakdown voltage, which will make the filling process window smaller and the process difficulty increased. Figure 3A As shown, it is a curve 301 of the breakdown voltage of the existing super junction device as a function of the doping concentration of the P-type column. It can be seen that the breakdown voltage is greater than or equal to the rated breakdown voltage only when the doping concentration of the P-type column is between dmin1 and dmax1. If the variation range of the doping concentration of the P-type column exceeds the interval from dmin1 to dmax1, the breakdown voltage will be reduced to below the rated breakdown voltage, so that the device cannot operate under normal operating voltage. Since in the existing super junction device, the aspect ratio and depth of the super junction trench are not set according to the filling process window, and the variation range of the doping concentration of the P-type column is limited by the filling process window, under a certain filling process, it is possible that the variation range of the doping concentration of the P-type column exceeds the interval from dmin1 to dmax1, thereby making the super junction device unable to be used normally. Or it is necessary to increase the difficulty of the filling process so as to reduce the filling process window, thereby reducing the variation range of the doping concentration of the P-type column to the range of dmin1 to dmax1, but this will increase the process cost, and the manufacturing process will continue to improve. After the manufacturing process is improved, it is still impossible to guarantee that the variation range of the doping concentration of the P-type column will not exceed the range of dmin1 to dmax1. Take an existing N-type super junction device with a specification of 500V as an example: the thickness of the first epitaxial layer 202 is 45μm, the width of the super junction trench 203a is 3.8~4.1μm, the depth of the super junction trench 203a is 40~42μm, the thickness of the buffer layer 202a is 3~5μm, the aspect ratio of the super junction trench 203a is 9.7~11, and its breakdown voltage varies with Ppillar, that is, the doping concentration of the P-type column. Figure 3A As shown in the curve 301, the doping concentration needs to be controlled between dmin1 and dmax1 to meet the rated breakdown voltage.

[0091] like Figure 3B 302 is a curve showing a variation of the breakdown voltage of the super junction device according to an embodiment of the present invention with the doping concentration of the P-type column. Figure 3BIn the embodiment of the present invention, when the doping concentration of the P-type column is between dmin2 and dmax2, the breakdown voltage will be greater than or equal to the rated breakdown voltage; because, in the embodiment of the present invention, the aspect ratio and depth of the super junction trench 203 and the second thickness are set according to the actual filling process window, the filling process window makes the variation range of the doping concentration of the P-type column not exceed the interval of dmin2 and dmax2, so it can ensure that the breakdown voltage of the device is greater than the rated breakdown voltage, so that the device can work normally. Take an N-type super junction device of an embodiment of the present invention with a specification of 500V as an example: the thickness of the first epitaxial layer 202 is 45μm, the width of the super junction trench 203a is 4.2~4.5μm, the depth of the super junction trench 203a is 35~37μm, the thickness of the buffer layer 202a is 8~10μm, and the aspect ratio of the super junction trench 203a is 7.8~8.8, as shown below. Figure 3B The breakdown voltage distribution shown, Figure 3B The interval range of dmin2 and dmax2 in Figure 3A The range between dmin1 and dmax1 is wide, so the super-junction device in this embodiment of the present invention can maintain a breakdown voltage greater than the rated value within a wide range of P pillar doping concentrations. The P pillar filling process window only needs to be within the range between dmin2 and dmax2, thus increasing the P pillar filling process window. Furthermore, while the thickness of the first epitaxial layer 202 remains unchanged, the reduced trench depth of the super-junction trench 203 in this embodiment of the present invention reduces the difficulty of the P pillar filling process, improves filling concentration consistency, and reduces the probability of voids, thereby improving P pillar filling quality. Furthermore, the thicker buffer layer 202a enhances the device's avalanche breakdown resistance.

[0092] In some preferred embodiments, the aspect ratio of the super junction trench 203 is set according to the maximum filling process window to increase the filling process window. The aspect ratio and the second thickness of the super junction trench 203 are selected from multiple sets of experimental values.

[0093] In each group of experimental values, by changing the experimental value of the aspect ratio and the experimental value of the second thickness of the super junction trench 203, a first curve of the breakdown voltage of the corresponding super junction device as the second doping concentration changes is obtained, and the variation range of the second doping concentration above the rated breakdown voltage in each of the first curves is compared, and the experimental value of the aspect ratio of the super junction trench 203 corresponding to the first curve with the largest variation range of the second doping concentration is selected as the aspect ratio of the super junction trench 203 and the second thickness experimental value is selected as the second thickness.

[0094] like Figure 4 , which is a curve showing the variation of the breakdown voltage with the doping concentration of the P-type column corresponding to multiple sets of experimental values ​​used in the super junction device according to the embodiment of the present invention, i.e., the first curve. Figure 4 5 first curves are shown, which are marked with markers 401, 402, 403, 404 and 405 respectively. The parameters corresponding to each of the first curves are described as follows:

[0095] The parameters corresponding to curve 401 and Figure 3A The parameters of curve 301 are the same as:

[0096] The first epitaxial layer 202 has a thickness of 45 μm, the super junction trench 203 a has a width of 3.8-4.1 μm, a depth of 40-42 μm, a thickness of the buffer layer 202 a of 3-5 μm, and an aspect ratio of 9.7-11.

[0097] The parameters corresponding to curve 402 are:

[0098] The thickness of the first epitaxial layer 202 is 45 μm, the width of the super junction trench 203 a is 3.8-4.1 μm, the depth of the super junction trench 203 a is 38-40 μm, the thickness of the buffer layer 202 a , i.e. the second thickness, is 5-7 μm, and the aspect ratio of the super junction trench 203 a is 9.3-10.5.

[0099] Compared with the parameters of curve 401 , in curve 402 , the depth of the super junction trench 203 a is reduced by 2 μm, and the thickness of the buffer layer 202 a is increased by 2 μm.

[0100] The parameters corresponding to curve 403 are:

[0101] The thickness of the first epitaxial layer 202 is 45 μm, the width of the super junction trench 203 a is 4.0-4.3 μm, the depth of the super junction trench 203 a is 38-40 μm, the thickness of the buffer layer 202 a is 5-7 μm, and the aspect ratio of the super junction trench 203 a is 8.8-10.

[0102] Compared with the parameters of curve 401 , in curve 403 , the depth of the super junction trench 203 a is reduced by 2 μm, the thickness of the buffer layer 202 a is increased by 2 μm, and the width of the super junction trench 203 a is increased by 0.2 μm.

[0103] The parameters corresponding to curve 404 are:

[0104] The first epitaxial layer 202 has a thickness of 45 μm, the super junction trench 203 a has a width of 4.2-4.5 μm, a depth of 35-37 μm, the buffer layer 202 a has a thickness of 8-10 μm, and the super junction trench 203 a has an aspect ratio of 7.8-8.8.

[0105] Compared with the parameters of curve 401 , in curve 403 , the depth of the super junction trench 203 a is reduced by 5 μm, the thickness of the buffer layer 202 a is increased by 5 μm, and the width of the super junction trench 203 a is increased by 0.4 μm.

[0106] The parameters corresponding to curve 405 are:

[0107] The first epitaxial layer 202 has a thickness of 45 μm, the super junction trench 203 a has a width of 4.4-4.7 μm, a depth of 33-35 μm, the buffer layer 202 a has a thickness of 10-12 μm, and the super junction trench 203 a has an aspect ratio of 7.0-8.0.

[0108] Compared with the parameters of curve 401 , in curve 403 , the depth of the super junction trench 203 a is reduced by 7 μm, the thickness of the buffer layer 202 a is increased by 7 μm, and the width of the super junction trench 203 a is increased by 0.6 μm.

[0109] right Figure 4 Comparing the curves in the figure, we can see that:

[0110] In curve 401, the variation range of the doping concentration of the P pillar needs to be limited between dmin101 and dmax101, that is, the filling process window of the P pillar needs to be limited between dmin101 and dmax101. Figure 3A The curve 301 in is the same, so dmin101 is equal to dmin1, and dmax101 is equal to dmax1.

[0111] Relative to curve 401:

[0112] The breakdown voltage of curve 402 is reduced, and the filling process window is reduced;

[0113] The P pillar filling process window of curve 403 is enlarged, and the breakdown voltage consistency is improved;

[0114] Curve 404 has the largest P pillar filling process window, the best breakdown voltage consistency, and good avalanche breakdown resistance.

[0115] The P pillar filling process window of curve 405 is reduced, and the breakdown voltage is reduced.

[0116] From the above, it can be seen that the parameters of curve 404 can be selected as the parameters of the super junction device of the embodiment of the present invention, so, Figure 3B Curve 302 and Figure 4 The same as curve 404 in FIG.

[0117] Different from the prior art in which the breakdown voltage of the device is improved by increasing the depth of the super junction structure and the aspect ratio of the super junction trench, the embodiment of the present invention takes into account the problem that the doping concentration of the second conductive type epitaxial layer used to form the second conductive type column 204 is difficult to control when filling the super junction trench 203. Under the condition that the thickness of the epitaxial layer corresponding to the drift region, that is, the first epitaxial layer 202, is certain, the aspect ratio of the super junction trench 203 and the buffer layer 202a at the bottom are optimized. This optimization is set according to the filling process window of the second conductive type epitaxial layer, so that the second conductive type column 204 can be guaranteed to be filled with the second conductive type epitaxial layer. When the doping concentration of the second conductive type epitaxial layer changes due to fluctuations in the filling process itself, the actual concentration of the second conductive type epitaxial layer finally formed can make the breakdown voltage of the device greater than the rated breakdown voltage. Therefore, the embodiment of the present invention can reduce the restrictions on the filling process window of the second conductive type epitaxial layer, thereby increasing the filling process window of the second conductive type column 204 filling the super junction trench 203, thereby reducing the difficulty of controlling the doping concentration of the second conductive type epitaxial layer, and can obtain the maximum filling process window under the condition that the thickness of the epitaxial layer corresponding to the drift region is certain.

[0118] Since the depth of the super junction trench 203 is deeper and the aspect ratio is larger, the difficulty of filling the second conductive type epitaxial layer increases. In addition to the increased difficulty in controlling the doping concentration, voids can also be easily formed. Therefore, unlike the prior art that simply increases the aspect ratio of the super junction trench 203, the aspect ratio of the super junction trench 203 in the embodiment of the present invention is actually set within a range smaller than the aspect ratio of the super junction trench 203 of the existing super junction device. This is obviously beneficial to reducing the number of voids and improving the filling quality of the second conductive type epitaxial layer.

[0119] At the same time, under the condition that the thickness of the first epitaxial layer 202 is constant, after the depth of the super junction trench 203 is reduced, the thickness of the corresponding buffer layer 202a will increase, which can further improve the avalanche breakdown resistance of the device.

[0120] The method for manufacturing a super junction device according to an embodiment of the present invention comprises the following steps:

[0121] Step 1: providing a first epitaxial layer 202 doped with a first conductivity type.

[0122] Step 2: forming a super junction trench 203 in a selected region of the first epitaxial layer 202 , with the first epitaxial layer 202 at the bottom of the super junction trench 203 serving as a buffer layer 202 a .

[0123] The super junction trench 203 has a first width and a first depth, the buffer layer 202a has a second thickness, the sum of the first depth and the second thickness is equal to the thickness of the first epitaxial layer 202, and the aspect ratio of the super junction trench 203 is the ratio of the first depth to the first width.

[0124] Step three: filling the super junction trench 203 with a second conductive type epitaxial layer to form second conductive type pillars 204 , and forming first conductive type pillars from the first epitaxial layer 202 between the second conductive type pillars 204 .

[0125] A super junction structure is formed by a plurality of alternately arranged first conductive type columns and second conductive type columns 204 .

[0126] The first doping concentration of the first conductive type column matches the second doping concentration of the second conductive type column 204 ; the second doping concentration varies within a filling process window of the second conductive type epitaxial layer.

[0127] Under the condition of keeping the thickness of the first epitaxial layer 202 unchanged, the aspect ratio and the second thickness of the super junction trench 203 in step 2 are pre-set according to the filling process window, so that at the second doping concentration minimum and the second doping concentration maximum corresponding to the filling process window, the breakdown voltage of the super junction device is greater than or equal to the rated breakdown voltage, so as to ensure that the breakdown voltage of the super junction device is greater than or equal to the rated breakdown voltage when the second doping concentration changes within the filling process window, and the second thickness meets the requirements of the avalanche breakdown resistance of the super junction device.

[0128] The method of the embodiment of the present invention further includes:

[0129] A device unit structure is formed on the top of each super junction unit; each super junction unit is composed of a first conductive type column and its adjacent second conductive type column 204; the super junction device is formed by multiple device unit structures connected in parallel, and each device unit structure includes a gate structure, a channel region 205 and a source region 206.

[0130] The gate structure adopts a planar gate or a trench gate, including a gate conductive material layer such as a polysilicon gate, with a gate dielectric layer between the polysilicon gate and the corresponding channel region 205, and the surface of the channel region 205 covered by the polysilicon gate is used to form a conductive channel.

[0131] The following front processes are also included:

[0132] An interlayer film, a contact hole and a front metal layer are formed, and the front metal layer is patterned to form a source electrode and a gate electrode.

[0133] A contact hole is formed at the top of the source region 206 and is connected to the source electrode formed by the front metal layer through the contact hole. A heavily doped body lead region 207 of the second conductivity type is also formed at the bottom of the contact hole at the top of the source region 206. The body lead region 207 is also connected to the source electrode through the contact hole at the top. The polysilicon gate is connected to the gate electrode through a corresponding contact hole at the top.

[0134] In the method of the embodiment of the present invention, the super junction device is a super junction MOSFET.

[0135] After the front side process is completed, the following back side processes are also included:

[0136] A drain region heavily doped with the first conductivity type is formed on the back side of the buffer layer 202a. In the method of the embodiment of the present invention, the first epitaxial layer 202 is formed on the surface of a semiconductor substrate heavily doped with the first conductivity type, such as a silicon substrate, and the drain region 201 is formed by thinning the back side of the semiconductor substrate, or by performing back side ion implantation of heavily doped first conductivity type into the back side of the thinned semiconductor substrate.

[0137] In the embodiment of the present invention, the superjunction device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, and the second conductivity type pillar 204 is a P-type pillar. In other embodiments, the superjunction device may be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0138] In the method of the embodiment of the present invention, the aspect ratio of the super junction trench 203 is set according to the maximum filling process window, so as to increase the filling process window.

[0139] In some preferred embodiments, the aspect ratio of the super junction trench 203 and the second thickness are selected from multiple sets of experimental values. The step of selecting the aspect ratio of the super junction trench 203 and the second thickness includes:

[0140] A plurality of sets of experimental values ​​for the aspect ratio and the second thickness of the super junction trench 203 are set.

[0141] For each group of experimental values ​​of the aspect ratio and the second thickness of the super junction trench 203, the second doping concentration is changed and the breakdown voltage of the super junction device is measured to obtain a first curve of the breakdown voltage of the corresponding super junction device changing with the second doping concentration.

[0142] Compare the variation ranges of the second doping concentration above the rated breakdown voltage in each of the first curves and select the experimental value of the aspect ratio of the super junction trench 203 corresponding to the first curve with the largest variation range of the second doping concentration as the aspect ratio of the super junction trench 203 and the experimental value of the second thickness as the second thickness.

[0143] In order to more clearly illustrate the method for manufacturing a super junction device according to an embodiment of the present invention, a further description is given below with reference to a set of specific parameters:

[0144] The operating voltage of the super junction device is 450V to 550V, and the rated breakdown voltage is greater than or equal to the operating voltage of the super junction device.

[0145] The aspect ratio of the super junction trench 203 is 7.8-8.8.

[0146] The second thickness is 8 micrometers to 10 micrometers.

[0147] The present invention has been described in detail above by using specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A super junction device, characterized in that: include: A super junction structure is formed in a first epitaxial layer doped with a first conductivity type, wherein the first epitaxial layer at the bottom of the super junction structure constitutes a buffer layer; The super junction structure is composed of a plurality of first conductivity type columns and second conductivity type columns arranged alternately; The second conductive type column is composed of a second conductive type epitaxial layer filled in the super junction trench; The first conductive type pillars are composed of the first epitaxial layer between the second conductive type pillars; The super junction trench has a first width and a first depth, the buffer layer has a second thickness, the sum of the first depth and the second thickness is equal to the thickness of the first epitaxial layer, and the aspect ratio of the super junction trench is the ratio of the first depth to the first width; A first doping concentration of the first conductive type column matches a second doping concentration of the second conductive type column; the second doping concentration varies within a filling process window of the second conductive type epitaxial layer; Under the condition that the thickness of the first epitaxial layer remains unchanged, the aspect ratio and the second thickness of the super junction trench are set according to the filling process window, so that at the second doping concentration minimum value and the second doping concentration maximum value corresponding to the filling process window, the breakdown voltage of the super junction device is greater than or equal to the rated breakdown voltage, so as to ensure that the breakdown voltage of the super junction device is greater than or equal to the rated breakdown voltage when the second doping concentration changes within the filling process window; The operating voltage of the super junction device is 450V to 550V, and the rated breakdown voltage is greater than or equal to the operating voltage of the super junction device; The aspect ratio of the super junction trench is 7.8 to 8.8; The second thickness is 8 micrometers to 10 micrometers.

2. The superjunction device according to claim 1, wherein: The aspect ratio of the super junction trench is set according to the maximum filling process window, so as to increase the filling process window.

3. The super junction device according to claim 1, wherein: The super junction device is formed by connecting a plurality of device unit structures in parallel, each of the device unit structures is formed on a corresponding super junction unit, and each of the super junction units is composed of a first conductive type column and an adjacent second conductive type column; Each of the device unit structures includes a gate structure, a channel region and a source region.

4. The super junction device according to claim 3, wherein: The super junction device is a super junction MOSFET, and a drain region heavily doped with a first conductivity type is formed on the back side of the buffer layer.

5. A method for manufacturing a super junction device, characterized in that: The steps include: Step 1: providing a first epitaxial layer doped with a first conductivity type; Step 2: forming a super junction trench in a selected area of ​​the first epitaxial layer, with the first epitaxial layer at the bottom of the super junction trench serving as a buffer layer; The super junction trench has a first width and a first depth, the buffer layer has a second thickness, the sum of the first depth and the second thickness is equal to the thickness of the first epitaxial layer, and the aspect ratio of the super junction trench is the ratio of the first depth to the first width; Step 3: filling the super junction trench with a second conductive type epitaxial layer to form a second conductive type column, and forming a first conductive type column with the first epitaxial layer between the second conductive type columns; A super junction structure is formed by a plurality of alternatingly arranged first conductive type columns and second conductive type columns; A first doping concentration of the first conductive type column matches a second doping concentration of the second conductive type column; the second doping concentration varies within a filling process window of the second conductive type epitaxial layer; Under the condition that the thickness of the first epitaxial layer remains unchanged, the aspect ratio and the second thickness of the super junction trench in step 2 are pre-set according to the filling process window, so that at the second doping concentration minimum value and the second doping concentration maximum value corresponding to the filling process window, the breakdown voltage of the super junction device is greater than or equal to the rated breakdown voltage, thereby ensuring that the breakdown voltage of the super junction device is greater than or equal to the rated breakdown voltage when the second doping concentration changes within the filling process window; The operating voltage of the super junction device is 450V to 550V, and the rated breakdown voltage is greater than or equal to the operating voltage of the super junction device; The aspect ratio of the super junction trench is 7.8 to 8.8; The second thickness is 8 micrometers to 10 micrometers.

6. The method for manufacturing a super junction device according to claim 5, wherein: The aspect ratio of the super junction trench is set according to the maximum filling process window, so as to increase the filling process window.

7. The method for manufacturing a super junction device according to claim 6, wherein: The aspect ratio of the super junction trench and the second thickness are selected from multiple sets of experimental values, and the steps of selecting the aspect ratio of the super junction trench and the second thickness include: Setting a plurality of sets of experimental values ​​for aspect ratios of the super junction trench and second thickness; For each group of experimental values ​​of the aspect ratio and the second thickness of the super junction trench, varying the second doping concentration and measuring the breakdown voltage of the super junction device, to obtain a first curve showing a change in the breakdown voltage of the super junction device as a function of the second doping concentration; Compare the variation ranges of the second doping concentration above the rated breakdown voltage in each of the first curves and select the experimental value of the aspect ratio of the super junction trench corresponding to the first curve with the largest variation range of the second doping concentration as the aspect ratio of the super junction trench and the experimental value of the second thickness as the second thickness.

8. The method for manufacturing a super junction device according to claim 5, wherein: Also includes: A device unit structure is formed on the top of each super junction unit; each super junction unit is composed of a first conductive type column and its adjacent second conductive type column; the super junction device is formed by connecting multiple device unit structures in parallel, and each device unit structure includes a gate structure, a channel region and a source region.

9. The method for manufacturing a super junction device according to claim 8, wherein: The super junction device is a super junction MOSFET; After the front side process is completed, the following back side processes are also included: A drain region heavily doped with the first conductivity type is formed on the back side of the buffer layer.

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