Semiconductor power device and method for manufacturing the same

Abstract

The present invention provides a semiconductor power device and a preparation method thereof, wherein the semiconductor power device comprises: a semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer; a gate structure located in the drift layer; a well region located in the drift layer on both sides of the gate structure; a protection unit surrounding the bottom surface and part of the side wall of the gate structure in the drift layer; the protection unit comprises: a first doped protection layer located in the drift layer at the bottom of the gate structure; a second doped protection layer located in the drift layer at the side wall and part of the bottom of the gate structure, the conductivity type of the first doped protection layer is the same as the conductivity type of the well region and opposite to the conductivity type of the second doped protection layer, the doping concentration of the second doped protection layer is greater than the doping concentration of the drift layer, and the second doped protection layer and the first doped protection layer form a PN junction. The protection of the gate dielectric layer is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor power device and a preparation method thereof. Background Art

[0002] Power semiconductor devices are the core components for power conversion and circuit control in power electronic devices. With the development of new energy vehicles, photovoltaics, rail transit, smart grids and other industries in recent years, the market demand for power devices has increased rapidly. The third-generation semiconductor SiC materials have obvious advantages in bandgap width, thermal conductivity, critical breakdown field strength, and electron saturation drift velocity, which is in line with the development trend of small and lightweight, efficient integration, safety and reliability of future power electronic systems.

[0003] With the continuous iteration of planar SiC MOSFET technology, its cell size reduction capability is gradually approaching its limit. In comparison, trench SiC MOSFET is destined to be the development trend of the next generation of SiC power devices due to its natural advantages such as smaller cell size and higher channel density. For trench SiC MOSFET, the electric field concentration of its bottom gate oxide in the reverse blocking state is a key issue that restricts its performance and reliability. Summary of the invention

[0004] The technical problem to be solved by the present invention is how to improve the problem of electric field concentration in the bottom area of ​​the gate structure of a semiconductor power device in a reverse blocking state.

[0005] In order to solve the above technical problems, the present invention provides a semiconductor power device, comprising: a semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer; a gate structure located in the drift layer; a well region, respectively located in the drift layer on both sides of the gate structure; a protection unit surrounding the bottom surface and part of the side wall of the gate structure in the drift layer; the protection unit comprises: a first doped protection layer, located in the drift layer at the bottom of the gate structure; a second doped protection layer, located in the drift layer at the side wall and part of the bottom of the gate structure, the conductivity type of the first doped protection layer is the same as the conductivity type of the well region and is opposite to the conductivity type of the second doped protection layer, the doping concentration of the second doped protection layer is greater than the doping concentration of the drift layer, and the second doped protection layer and the first doped protection layer form a PN junction.

[0006] Optionally, a partial area of ​​the well region serves as a channel region, the channel region contacts a side wall of the gate structure, and a doping concentration of the channel region is lower than a doping concentration of the well region outside the channel region.

[0007] Optionally, the doping concentration of the channel region is 1E16atom / cm 3~5E17atom / cm 3 ; The doping concentration of the well region outside the channel region is 5E16atom / cm 3 ~2E18atom / cm 3 .

[0008] Optionally, the well region includes a first well region and a second well region on the side of the first well region facing the semiconductor substrate layer, and the second well region is in contact with the first well region; a portion of the first well region serves as a channel region; and the second doping protection layer on the side wall of the gate structure is located between the second well region and the gate structure.

[0009] Optionally, the doping concentration of the second well region is less than the doping concentration of the first well region outside the channel region.

[0010] Optionally, a surface of the channel region facing the semiconductor substrate layer is flush with a surface of the well region outside the channel region facing the semiconductor substrate layer.

[0011] Optionally, a longitudinal distance between a surface of the well region facing the semiconductor substrate layer and a surface of the first doping protection layer facing the semiconductor substrate layer is 0.3 micrometers to 1.5 micrometers.

[0012] Optionally, the doping concentration of the second doping protection layer is 2 to 10 times the doping concentration of the drift layer.

[0013] Optionally, the second doping protection layer is located on both sides of the first doping protection layer along the width direction of the gate structure and does not surround the surface of the first doping protection layer facing the semiconductor substrate layer; or, the second doping protection layer is located on both sides of the first doping protection layer along the width direction of the gate structure and also surrounds the surface of the first doping protection layer facing the semiconductor substrate layer.

[0014] Optionally, the doping concentration of the first doping protection layer is greater than the doping concentration of the second doping protection layer.

[0015] Optionally, the semiconductor power device is a SiC-based semiconductor power device.

[0016] The present invention also provides a method for preparing a semiconductor power device, comprising: forming a drift layer on one side of a semiconductor substrate layer; forming a gate structure, a well region and a protection unit in the drift layer; the well regions are respectively located in the drift layer on both sides of the gate structure; the protection unit surrounds the bottom surface and part of the side wall of the gate structure; forming the protection unit comprises: forming a first doped protection layer, the first doped protection layer is located in the drift layer at the bottom of the gate structure; forming a second doped protection layer, the second doped protection layer is located in the drift layer at part of the side wall and part of the bottom of the gate structure, the conductivity type of the first doped protection layer is the same as the conductivity type of the well region and is opposite to the conductivity type of the second doped protection layer, the doping concentration of the second doped protection layer is greater than the doping concentration of the drift layer, and the second doped protection layer and the first doped protection layer form a PN junction.

[0017] Optionally, the process of forming the gate structure, the well region and the protection unit in the drift layer includes: forming a first doping region extending from a surface of the drift layer on one side away from the semiconductor substrate to a part of the thickness of the drift layer; forming an initial well region in the drift layer on both sides of the first doping region and in the first doping region, wherein the doping concentration of the initial well region in the first doping region is less than the doping concentration of the initial well region on both sides of the first doping region, and a surface of the initial well region in the first doping region facing the semiconductor substrate layer is away from the semiconductor substrate layer relative to a surface of the first doping region facing the semiconductor substrate layer; forming a trench in the first doping region that penetrates the initial well region in the first doping region and extends to the bottom of the initial well region, wherein the lateral dimension of the trench is less than the lateral dimension of the first doping region, and the bottom surface of the trench is away from the semiconductor substrate layer relative to a surface of the first doping region facing the semiconductor substrate layer; wherein the remaining initial well region around the trench forms the well region, and the remaining first doping region around the trench forms the second doping protection layer; after forming the trench, forming a first doping protection layer in the drift layer at a part of the bottom of the trench.

[0018] Optionally, a surface of a side of the initial well region in the first doping region facing the semiconductor substrate layer is flush with a surface of a side of the initial well region on both sides of the first doping region facing the semiconductor substrate layer; or, a surface of a side of the initial well region in the first doping region facing the semiconductor substrate layer is farther away from the semiconductor substrate layer than a surface of a side of the initial well region on both sides of the first doping region facing the semiconductor substrate layer.

[0019] The technical solution of the present invention has the following technical effects:

[0020] The semiconductor power device provided by the technical solution of the present invention is provided with a protection unit surrounding the bottom surface and part of the side wall of the gate structure in the drift layer. The protection unit comprises: a first doped protection layer, located in the drift layer at the bottom of the gate structure; a second doped protection layer, located in the drift layer at the side wall and the bottom of the gate structure, the conductivity type of the first doped protection layer is the same as the conductivity type of the well region and opposite to the conductivity type of the second doped protection layer, the doping concentration of the second doped protection layer is greater than the doping concentration of the drift layer, and the second doped protection layer and the first doped protection layer form a PN junction. In this way, during the reverse withstand voltage process, the PN junction is depleted, part of the electric field peak is transferred to the junction of the PN junction, and the PN junction protects the gate dielectric layer at the bottom of the gate structure. Secondly, the well region and the drift layer at the bottom of the well region are depleted, and part of the electric field peak is transferred to the junction of the well region and the drift layer, protecting the gate dielectric layer in the side wall region of the gate structure. Due to the increased protection of the gate dielectric layer, the reverse breakdown voltage is increased.

[0021] Secondly, when the semiconductor power device is forward-conducted, electrons pass from the first source region through the channel region and the second doped protection layer at the bottom of the channel region. Because the doping concentration of the second doped protection layer is greater than the doping concentration of the drift layer, the forward conduction resistance is reduced.

[0022] Furthermore, the doping concentration of the channel region is lower than the doping concentration of the well region outside the channel region, so that the channel region is more easily inverted and the channel resistance is smaller.

[0023] The method for preparing a semiconductor power device provided by the present invention forms a protection unit, the protection unit includes a first doped protection layer and a second doped protection layer, the second doped protection layer and the first doped protection layer form a PN junction, during the reverse withstand voltage process, the PN junction is depleted, part of the electric field peak is transferred to the junction of the PN junction, the PN junction protects the gate dielectric layer at the bottom of the gate structure, and secondly, the well region and the drift layer at the bottom of the well region are depleted, part of the electric field peak is transferred to the junction of the well region and the drift layer, and the gate dielectric layer in the sidewall region of the gate structure is protected. Due to the increased protection of the gate dielectric layer, the withstand voltage capability of the device is improved.

[0024] Furthermore, after the first doping region is formed and the trench is formed, the second doping protection layer is formed by the remaining first doping region around the trench. Since the first doping region is formed before the trench is formed, the edge position and edge morphology of the first doping region can be well controlled, so the morphology and size of the formed second doping protection layer can be well controlled, and the size of the cell will not be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A schematic diagram of the structure of a semiconductor power device provided by an embodiment of the present invention;

[0027] Figure 2 A schematic structural diagram of a semiconductor power device provided by another embodiment of the present invention;

[0028] Figure 3 A schematic structural diagram of a semiconductor power device provided by another embodiment of the present invention;

[0029] Figure 4 A schematic structural diagram of a semiconductor power device provided by another embodiment of the present invention;

[0030] Figures 5 to 13 A schematic structural diagram of a semiconductor power device manufacturing process provided by an embodiment of the present invention;

[0031] Figures 14 to 16 A schematic structural diagram of a semiconductor power device manufacturing process provided by another embodiment of the present invention;

[0032] Figures 17 to 23 A schematic structural diagram of a semiconductor power device manufacturing process provided by another embodiment of the present invention;

[0033] Figure 24 to Figure 25 A schematic structural diagram of a semiconductor power device manufacturing process provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0034] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0036] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0037] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0038] An embodiment of the present invention provides a semiconductor power device, referring to Figure 1 ,include:

[0039] Semiconductor substrate layer 100;

[0040] A drift layer 110 located on one side of the semiconductor substrate layer 100;

[0041] A gate structure located in the drift layer 110;

[0042] Well regions 150 are respectively located in the drift layer 110 on both sides of the gate structure;

[0043] A protection unit surrounding the bottom surface and part of the side wall of the gate structure in the drift layer 110; the protection unit comprises: a first doped protection layer 140, located in the drift layer 110 at the bottom of the gate structure; a second doped protection layer 130, located in the drift layer 110 at part of the side wall and the bottom of the gate structure, the conductivity type of the first doped protection layer 140 is the same as the conductivity type of the well region 150 and opposite to the conductivity type of the second doped protection layer 130, the doping concentration of the second doped protection layer 130 is greater than the doping concentration of the drift layer 110, and the second doped protection layer 130 and the first doped protection layer 140 form a PN junction.

[0044] The gate structure includes a gate dielectric layer 121 and a gate electrode layer 122 .

[0045] In this embodiment, during the reverse withstand voltage test of the semiconductor power device, the PN junction formed by the second doped protection layer 130 and the first doped protection layer 140 is depleted, and the electric field peak is transferred to the junction of the PN junction. The PN junction protects the gate dielectric layer 121 at the bottom of the gate structure. Secondly, the well region 150 and the drift layer 110 at the bottom of the well region 150 are depleted, and the gate dielectric layer 121 in the sidewall region of the gate structure is protected. Since the electric field strength at the position of the gate dielectric layer 121 is reduced, the protection capability of the gate dielectric layer 121 is improved.

[0046] Secondly, the doping concentration of the second doped protection layer 130 is greater than the doping concentration of the drift layer 110 , so when the semiconductor power device is forward-conducted, the resistance of the second doped protection layer 130 is small, thereby reducing the forward conduction resistance.

[0047] It should be noted that if the protection unit is not provided, even if the well region and the drift layer at the bottom of the well region are depleted, there is almost no protection for the gate dielectric layer in the sidewall region of the gate structure. Because in the reverse blocking state of the semiconductor power device, the electric field concentration will occur at the bottom gate dielectric layer position in the gate structure of the semiconductor power device without the protection unit, and the gate dielectric layer at the bottom of the gate structure is easy to break down. Therefore, the depletion of the drift layer in the well region and the bottom of the well region has no chance to play a protective role on the gate dielectric layer in the sidewall region of the gate structure. After the protection unit is provided, in the reverse blocking state of the semiconductor power device, the protection unit can alleviate the electric field concentration at the bottom gate dielectric layer position in the gate structure. The protection unit has a better protective effect on the gate dielectric layer, and the gate dielectric layer is not easy to break down. Therefore, the depletion of the drift layer in the well region and the bottom of the well region can increase the protection of the gate dielectric layer.

[0048] In this embodiment, the new generation of SiC-based semiconductor power devices represented by SiC have higher reverse withstand voltage, lower forward conduction loss, faster switching frequency and stronger environmental tolerance compared to Si-based semiconductor power devices, and are therefore considered to be a new hope in the field of power conversion. It should be noted that in this embodiment, the semiconductor substrate layer 100 is silicon carbide (SiC) doped with conductive ions. In one embodiment, the conductive ions in the semiconductor substrate layer 100 are N-type ions. In other embodiments, the conductivity type of the semiconductor substrate layer 100 is not limited.

[0049] In one embodiment, the conductivity type of the drift layer 110 is the same as the conductivity type of the semiconductor substrate layer 100, and the doping concentration of the drift layer 110 is less than the doping concentration of the semiconductor substrate layer 100. In one embodiment, the material of the drift layer is silicon carbide doped with N-type conductive ions. The N-type conductive ions may be phosphorus ions or nitrogen ions.

[0050] The conductivity type of the well region 150 is opposite to the conductivity type of the drift layer 110. In this embodiment, when the conductivity type of the drift layer 110 is N-type, the conductivity type of the well region 150 is P-type.

[0051] In this embodiment, the semiconductor power device further includes: a first source region 160 located in the well region 150, and the conductivity type of the first source region 160 is opposite to the conductivity type of the well region 150. In this embodiment, when the conductivity type of the well region 150 is P type, the conductivity type of the first source region 160 is N type.

[0052] In this embodiment, the semiconductor power device further includes: a second source region 170 located in the well region 150, the conductivity type of the second source region 170 being opposite to the conductivity type of the first source region 160. The second source region 170 is located on a side of the first source region 160 away from the gate structure along the width direction of the gate structure.

[0053] In this embodiment, the drain electrode layer 180 is further included and is located on a surface of the semiconductor substrate layer 100 that is away from the drift layer 110 .

[0054] The gate structure includes a gate dielectric layer 121 and a gate electrode layer 122 . The gate dielectric layer 121 is located on a surface of the gate electrode layer 122 facing the semiconductor substrate layer 100 (ie, a bottom surface of the gate electrode layer 122 ) and a sidewall of the gate electrode layer 122 .

[0055] In one embodiment, the material of the gate dielectric layer 121 includes silicon oxide, and the material of the gate electrode layer 122 includes polysilicon.

[0056] In one embodiment, a portion of the well region 150 serves as a channel region 151, and the channel region 151 contacts the side wall of the gate structure. Specifically, the channel region 151 contacts a portion of the gate dielectric layer 121 located on the side of the gate electrode layer 122, and the doping concentration of the channel region 151 is less than the doping concentration of the well region 150 outside the channel region 151, so that the channel region 151 is easier to invert and the channel resistance is smaller.

[0057] In one embodiment, the doping concentration of the channel region 151 is 1E16 atom / cm 3 ~5E17atom / cm 3; The doping concentration of the well region 150 outside the channel region 151 is 5E16atom / cm 3 ~2E18atom / cm 3 .

[0058] In one embodiment, reference Figure 1 The surface of the channel region 151 facing the semiconductor substrate layer 100 is flush with the surface of the well region 150 outside the channel region 151 facing the semiconductor substrate layer 100 .

[0059] In one embodiment, the longitudinal distance between the surface of the well region 150 facing the semiconductor substrate layer 100 and the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 is 0.3 micrometers to 1.5 micrometers, for example, 0.3 micrometers, 0.5 micrometers, 0.8 micrometers, 1.0 micrometers, 1.2 micrometers or 1.5 micrometers, and the direction of the longitudinal distance is parallel to the thickness direction of the semiconductor substrate layer 100. The longitudinal distance between the surface of the well region 150 facing the semiconductor substrate layer 100 and the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 is less than or equal to 1.5 micrometers, so that the longitudinal distance between the surface of the well region 150 facing the semiconductor substrate layer 100 and the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 is closer, so that the well region 150 and the drift layer 100 at the bottom of the well region 150 are depleted to better protect the gate dielectric layer in the sidewall region of the gate structure. The longitudinal distance between the surface of the well region 150 facing the semiconductor substrate layer 100 and the surface of the first doped protection layer 140 facing the semiconductor substrate layer 100 is greater than or equal to 0.3 microns. The interface position of the well region 150 and the drift layer 100 at the bottom of the well region 150 is too close to the protection unit at the bottom of the gate structure. The width of the forward conduction path in the first doped protection layer 140 will be affected, and the degree of reducing the resistance of the forward conduction path is limited. Therefore, the longitudinal distance between the surface of the well region 150 facing the semiconductor substrate layer 100 and the surface of the first doped protection layer 140 facing the semiconductor substrate layer 100 is preferably in the range of 0.3 microns to 1.5 microns.

[0060] In other embodiments, there is no limitation on the longitudinal distance between the surface of the well region 150 facing the semiconductor substrate layer 100 and the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 .

[0061] In one embodiment, the doping concentration of the second doping protection layer 130 is 2 to 10 times, for example, 2, 5 or 10 times, the doping concentration of the drift layer 110. In one embodiment, for example, the doping concentration of the second doping protection layer 130 is 1E16 atom / cm 3 ~2E17atom / cm 3 If the doping concentration of the second doped protective layer 130 is too high, the PN junction formed by the second doped protective layer 130 and the first doped protective layer 140 is prone to premature breakdown when the electric field is too high in the reverse blocking state, and the degree of protection for the gate dielectric layer is small. If the doping concentration of the second doped protective layer 130 is too low, the effect of the protection unit on alleviating the electric field concentration at the bottom of the gate dielectric layer in the gate structure is weakened, which is not conducive to further improving the effect of protecting the gate dielectric layer.

[0062] In one embodiment, the second doping protection layer 130 is located on both sides of the first doping protection layer 140 along the width direction of the gate structure and also surrounds the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 .

[0063] In one embodiment, the doping concentration of the first doping protection layer 140 is greater than the doping concentration of the second doping protection layer 130. Since the area of ​​the second doping protection layer 130 is greater than that of the first doping protection layer 140, it is necessary to set the doping concentration of the first doping protection layer 140 to be greater than that of the second doping protection layer 130, so as to achieve charge balance between the first doping protection layer 140 and the second doping protection layer 130 as much as possible, so that the depletion between the doping concentration of the first doping protection layer 140 and the second doping protection layer 130 is more sufficient.

[0064] In one embodiment, the thickness of the second doping protection layer 130 is 0.1 micrometer to 2 micrometers, for example, 0.1 micrometer, 0.5 micrometer, 1 micrometer, 1.5 micrometers or 2 micrometers.

[0065] In one embodiment, the thickness of the first doped protection layer 140 is 0.1 micrometer to 2 micrometers, for example, 0.1 micrometer, 0.5 micrometer, 1 micrometer, 1.5 micrometer or 2 micrometers. The surface of the second doped protection layer 130 located on the sidewall of the gate structure facing away from the semiconductor substrate layer 100 contacts the surface of the channel region 151 facing the semiconductor substrate layer 100.

[0066] It should be noted that when the semiconductor power device is forward-conducted, electrons pass from the first source region 160 through the channel region 151 and the second doped protection layer 130 at the bottom of the channel region 151, and continue downward to the drain electrode layer 180. Because the doping concentration of the second doped protection layer 130 is greater than the doping concentration of the drift layer 110, the forward conduction resistance is reduced.

[0067] Another embodiment of the present invention provides a semiconductor power device, referring to Figure 2 , this embodiment and Figure 1 The difference between the corresponding embodiments is that the second doping protection layer 130 is located on both sides of the first doping protection layer 140a along the width direction of the gate structure and does not surround the surface of the first doping protection layer 140a facing the semiconductor substrate layer 100. In this way, the thickness of the first doping protection layer 140a is relatively large, and the gate dielectric layer in the bottom area of ​​the gate structure is further away from the electric field peak of the PN junction depletion position formed by the first doping protection layer 140a and the second doping protection layer 130, so that the protection effect of the gate dielectric layer in the bottom area of ​​the gate structure is better.

[0068] In one embodiment, the thickness of the second doping protection layer 130 is 0.1 micrometer to 2 micrometers, for example, 0.1 micrometer, 0.5 micrometer, 1 micrometer, 1.5 micrometers or 2 micrometers.

[0069] In one embodiment, the thickness of the first doping protection layer 140 a is 0.1 micrometer to 2 micrometers, for example, 0.1 micrometer, 0.5 micrometer, 1 micrometer, 1.5 micrometers or 2 micrometers.

[0070] The doping concentration of the first doping protection layer 140a is referred to the content of the above embodiment. The doping concentration of the second doping protection layer 130 is referred to the content of the above embodiment. Figure 1 The description of the corresponding embodiments will not be repeated in detail.

[0071] Another embodiment of the present invention provides a semiconductor power device, referring to Figure 3 The difference between the semiconductor power device of this embodiment and the corresponding embodiment 1 is that: the well region includes a first well region 1501a and a second well region 1502a on the side of the first well region 1501a facing the semiconductor substrate layer 100, and the second well region 1502a is in contact with the first well region 1501a; a part of the first well region 1501a serves as a channel region 151; and the second doping protection layer 130 on the side wall of the gate structure is located between the second well region 1502a and the gate structure.

[0072] In one embodiment, the doping concentration of the second well region 1502 a is less than the doping concentration of the first well region 1501 a outside the channel region 151 .

[0073] Since the second well region 1502a is in contact with the second doped protection layer 130 on the side wall of the gate structure, the longitudinal distance between the interface position of the second well region 1502a and the drift layer 110 at the bottom of the second well region 1502a to the surface of the first doped protection layer 140 facing the semiconductor substrate layer 100 is small, so that the depletion of the drift layer 110 at the bottom of the second well region 1502a and the second well region 1502a can better protect the gate dielectric layer.

[0074] The surface of the second doping protection layer 130 located on the sidewall of the gate structure facing away from the semiconductor substrate layer 100 is in contact with the surface of the channel region 151 facing the semiconductor substrate layer 100 .

[0075] In one embodiment, the longitudinal distance between the surface of the well region 150 facing the semiconductor substrate layer 100 and the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 is 0.3 micrometers to 1.5 micrometers. Specifically, the longitudinal distance between the surface of the second well region 1502a facing the semiconductor substrate layer 100 and the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 is 0.3 micrometers to 1.5 micrometers.

[0076] In one embodiment, the doping concentration of the first doping protection layer 140 is greater than the doping concentration of the second doping protection layer 130 .

[0077] The other identical contents of the semiconductor power device in this embodiment and that in the first embodiment will not be described in detail.

[0078] Another embodiment of the present invention provides a semiconductor power device, referring to Figure 4 , this embodiment and Figure 3 The difference between the corresponding semiconductor power devices is that the second doping protection layer 130 is located on both sides of the first doping protection layer 140a along the width direction of the gate structure and does not surround the surface of the first doping protection layer 140a facing the semiconductor substrate layer 100. In this way, the thickness of the first doping protection layer 140a is relatively large, and the gate dielectric layer in the bottom area of ​​the gate structure is further away from the electric field peak of the PN junction depletion position formed by the first doping protection layer 140a and the second doping protection layer 130, so that the protection effect of the gate dielectric layer in the bottom area of ​​the gate structure is better.

[0079] In one embodiment, the thickness of the second doping protection layer 130 is 0.1 micrometer to 2 micrometers, for example, 0.1 micrometer, 0.5 micrometer, 1 micrometer, 1.5 micrometers or 2 micrometers.

[0080] In one embodiment, the thickness of the first doping protection layer 140 a is 0.1 micrometer to 2 micrometers, for example, 0.1 micrometer, 0.5 micrometer, 1 micrometer, 1.5 micrometers or 2 micrometers.

[0081] The content of the doping concentration of the first doping protection layer 140 a and the content of the doping concentration of the second doping protection layer 130 refer to the content of the above embodiment.

[0082] For other structures of this embodiment, please refer to Figure 3 The description of the corresponding embodiments will not be repeated in detail.

[0083] Another embodiment of the present invention also provides a method for preparing a semiconductor power device, comprising: forming a drift layer on one side of a semiconductor substrate layer; forming a gate structure, a well region and a protection unit in the drift layer; the well regions are respectively located in the drift layer on both sides of the gate structure; the protection unit surrounds the bottom surface and part of the side wall of the gate structure; forming the protection unit comprises: forming a first doped protection layer, the first doped protection layer is located in the drift layer at the bottom of the gate structure; forming a second doped protection layer, the second doped protection layer is located in the drift layer at part of the side wall and part of the bottom of the gate structure, the conductivity type of the first doped protection layer is the same as the conductivity type of the well region and is opposite to the conductivity type of the second doped protection layer, the doping concentration of the second doped protection layer is greater than the doping concentration of the drift layer, and the second doped protection layer and the first doped protection layer form a PN junction.

[0084] In one embodiment, the process of forming the gate structure, the well region and the protection unit in the drift layer includes: forming a first doping region extending from a surface of the drift layer facing away from the semiconductor substrate to a part of the thickness of the drift layer; forming an initial well region in the drift layer on both sides of the first doping region and in the first doping region, wherein the doping concentration of the initial well region in the first doping region is less than the doping concentration of the initial well region on both sides of the first doping region, and a surface of the initial well region in the first doping region facing the semiconductor substrate layer is away from the semiconductor substrate layer relative to a surface of the first doping region facing the semiconductor substrate layer; forming a trench in the first doping region that penetrates the initial well region in the first doping region and extends to the bottom of the initial well region, wherein the lateral dimension of the trench is less than the lateral dimension of the first doping region, and the bottom surface of the trench is away from the semiconductor substrate layer relative to a surface of the first doping region facing the semiconductor substrate layer; wherein the remaining initial well region around the trench forms the well region, and the remaining first doping region around the trench forms the second doping protection layer; after forming the trench, forming a first doping protection layer in the drift layer at a part of the bottom of the trench.

[0085] Combine the following Figures 5 to 13 The preparation method of semiconductor power devices is introduced in detail.

[0086] refer to Figure 5 , a drift layer 110 is formed on one side of the semiconductor substrate layer 100.

[0087] The material description of the drift layer 110 and the material description of the semiconductor substrate layer 100 refer to the contents of the aforementioned embodiment and will not be described in detail.

[0088] The formation process of the drift layer 110 includes an epitaxial process.

[0089] refer to Figure 6 , a first doped region 200 is formed in the drift layer 110 extending from a surface of the side of the drift layer 110 away from the semiconductor substrate 100 to a partial thickness.

[0090] The process of forming the first doping region 200 includes an ion implantation process.

[0091] The doping concentration of the first doping region 200 is greater than the doping concentration of the drift layer 110 , and the conductivity type of the first doping region 200 is the same as the conductivity type of the drift layer 110 .

[0092] refer to Figure 7 An initial well region is formed in the drift layer 110 on both sides of the first doping region 200 and in the first doping region 200, the doping concentration of the initial well region 220 in the first doping region 200 is less than the doping concentration of the initial well region 210 on both sides of the first doping region 200, and a side surface of the initial well region 220 in the first doping region 200 facing the semiconductor substrate layer 100 is away from the semiconductor substrate layer 100 relative to the side surface of the first doping region 200 facing the semiconductor substrate layer 100.

[0093] In one embodiment, the initial well regions 210 on both sides of the first doping region 200 have their surfaces facing the semiconductor substrate layer 100 farther away from the semiconductor substrate layer 100 than the surface of the first doping region 200 facing the semiconductor substrate layer 100 .

[0094] In one embodiment, a surface of the initial well region 220 in the first doping region 200 facing the semiconductor substrate layer 100 is flush with surfaces of the initial well regions 210 on both sides of the first doping region 200 facing the semiconductor substrate layer 100 .

[0095] The process of forming the initial well region includes an ion implantation process. In the process of forming the initial well region in the drift layer 110 on both sides of the first doping region 200 and in the first doping region 200, since part of the well ions implanted into the first doping region 200 by the ion implantation process will be neutralized with the doping ions in the first doping region 200, the doping concentration of the formed initial well region 220 is less than the doping concentration of the initial well region 210.

[0096] refer to Figure 8 A first initial source region 230 and a second source region 170 are formed in the drift layer 110 . The conductivity type of the first initial source region 230 is the same as that of the drift layer 110 and is opposite to that of the second source region 170 . The second source region 170 is located on both sides of the first initial source region 230 .

[0097] The process of forming the first initial source region 230 includes an ion implantation process. The process of forming the second source region 170 includes an ion implantation process.

[0098] refer to Fig. 9 , forming a groove C in the first doping region 200 that penetrates the initial well region 220 in the first doping region 200 and extends to the bottom of the initial well region 220, wherein the lateral dimension of the groove C is smaller than the lateral dimension of the first doping region 200, and the bottom surface of the groove C is away from the semiconductor substrate layer 100 relative to the surface of the first doping region 200 on the side facing the semiconductor substrate layer 100, wherein the remaining initial well region around the groove C forms a well region 150, the remaining first doping region 200 around the groove C forms a second doping protection layer 130, and the remaining first initial source region 230 around the groove C forms a first source region 160.

[0099] The well region 150 is located at two sides of the gate structure along the width direction. The first source region 160 is located at two sides of the gate structure along the width direction.

[0100] The remaining initial well regions 210 and 220 around the trench C form the well region 150 .

[0101] Since the doping concentration of the initial well region 220 is lower than the doping concentration of the initial well region 210 , and the remaining initial well region 220 around the trench C constitutes the channel region 151 , the doping concentration of the channel region 151 is lower than the doping concentration of the well region 150 outside the channel region 151 .

[0102] In this embodiment, it also includes: before forming the groove C, forming a mask layer Y on a partial area of ​​the first initial source region 230 and the second source region 170; etching the initial well region 220 and the first doped region 200 at the bottom of the initial well region 220 using the mask layer Y as a mask to form a groove C in the first doped region 200 that penetrates the initial well region 220 and extends to the bottom of the initial well region 220.

[0103] The material of the mask layer Y includes photoresist or silicon oxide.

[0104] In this embodiment, ion compensation is used to make the doping concentration of the initial well region 220 lower than the doping concentration of the initial well region 210, and the well region 150 is formed in the process of forming the trench C, thereby making the doping concentration of the channel region 151 lower than the doping concentration of the well region 150 outside the channel region 151, and no additional process steps are required to form the channel region 151 separately. This makes the position of the channel region 151 more accurate and better aligned with other structures of the channel region 151.

[0105] In one embodiment, reference Fig. 9 The surface of the channel region 151 facing the semiconductor substrate layer 100 is flush with the surface of the well region 150 outside the channel region 151 facing the semiconductor substrate layer 100 .

[0106] Since the second doping protection layer 130 is formed by the first doping region 200 remaining around the groove C, and the first doping region 200 is formed before the groove C is formed, the edge position and edge morphology of the first doping region 200 can be well controlled, so the morphology and size of the formed second doping protection layer 130 can be well controlled without increasing the size of the cell.

[0107] It should be noted that if an ion implantation process is used to form a second doped protective layer after the groove is formed, the ions need to be implanted obliquely at the sidewalls of the groove and vertically at the bottom of the groove. The implantation requires multiple steps, and it is difficult to control the edge morphology of the second doped protective layer formed by the implantation in the process. Secondly, it is easy to make the size of the second doped protective layer larger than the designed size, and the size of the cell will increase.

[0108] refer to Fig.10 , a sidewall Y1 is formed on the sidewall of the trench C.

[0109] The process of forming the sidewall Y1 includes: forming initial sidewalls on the sidewalls and bottom wall of the trench C; etching the initial sidewalls to remove the initial sidewalls on the bottom wall of the trench C, and the remaining initial sidewalls on the sidewalls of the trench C form the sidewall Y1.

[0110] The material of the sidewall spacer Y1 includes silicon oxide or silicon nitride.

[0111] refer to Fig.10 After the trench C is formed, a first doped protection layer 140 is formed in the drift layer 110 at a portion of the bottom of the trench C.

[0112] The process of forming the first doped protective layer 140 in the drift layer 110 at the bottom of the trench C is as follows: ion implantation is performed on the drift layer 110 at the bottom of the trench C using the sidewall Y1 as a mask to form the first doped protective layer 140. Further, ion implantation is performed on the drift layer 110 at the bottom of the trench C using the sidewall Y1 and the mask layer Y as a mask to form the first doped protective layer 140. The sidewall Y1 defines the edge position of the first doped protective layer 140 on the one hand, and protects the structure of the sidewall of the trench C on the other hand.

[0113] It should be noted that in other embodiments, the sidewall Y1 may not be formed.

[0114] The second doping protection layer 130 is located on both sides of the first doping protection layer 140 along the width direction of the gate structure and also surrounds the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 .

[0115] refer to Fig.11 After forming the first doping protection layer 140, the side wall Y1 is removed.

[0116] refer to Fig.12 After forming the first doping protection layer 140, the mask layer Y is removed.

[0117] It should be noted that the order of the step of removing the spacer Y1 and the step of removing the mask layer Y can be adjusted. The mask layer Y can be removed after the spacer Y1 is removed, or the spacer Y1 can be removed after the mask layer Y is removed.

[0118] refer to Fig.13 A gate structure is formed in the trench C, the gate structure comprising a gate dielectric layer 121 and a gate electrode layer 122. A drain electrode layer 180 is formed on a surface of the semiconductor substrate layer 100 facing away from the drift layer 110.

[0119] Another embodiment of the present invention further provides a method for preparing a semiconductor power device. The difference between this embodiment and the method for preparing a semiconductor power device of the previous embodiment is that the second doping protection layer is located on both sides of the first doping protection layer 140a along the width direction of the gate structure and does not surround the surface of the first doping protection layer 140a facing the semiconductor substrate layer 100.

[0120] Reference below Figures 14 to 16 The preparation method of semiconductor power devices is introduced.

[0121] refer to Fig.14 , Fig.14 For Fig. 9Based on the schematic diagram, a sidewall Y1 is formed on the sidewall of the trench C; and a first doped protection layer 140 a is formed in the drift layer 110 at a portion of the bottom of the trench C.

[0122] The process of forming the first doped protection layer 140a in the drift layer 110 at the bottom of part of the groove C is an ion implantation process, and the depth of the ion implantation process is controlled so that the second doped protection layer is located on both sides of the first doped protection layer 140a along the width direction of the gate structure and does not surround the surface of the first doped protection layer 140a facing the semiconductor substrate layer 100.

[0123] The process of forming the first doped protective layer 140a in the drift layer 110 at the bottom of the trench C is as follows: ion implantation is performed on the drift layer 110 at the bottom of the trench C using the sidewall Y1 as a mask to form the first doped protective layer 140a. Further, ion implantation is performed on the drift layer 110 at the bottom of the trench C using the sidewall Y1 and the mask layer Y as a mask to form the first doped protective layer 140a. The sidewall Y1 defines the edge position of the first doped protective layer 140a on the one hand, and protects the structure of the sidewall of the trench C on the other hand.

[0124] It should be noted that in other embodiments, the sidewall Y1 may not be formed.

[0125] refer to Fig.15 , remove the side wall Y1 and the mask layer Y.

[0126] refer to Fig.16 A gate structure is formed in the trench C, the gate structure comprising a gate dielectric layer 121 and a gate electrode layer 122. A drain electrode layer 180 is formed on a surface of the semiconductor substrate layer 100 facing away from the drift layer 110.

[0127] The contents of this embodiment that are the same as those of the previous embodiment will not be described in detail.

[0128] Another embodiment of the present invention further provides a method for preparing a semiconductor power device. Figures 5 to 13 The difference between the preparation methods of the semiconductor power devices of the corresponding embodiments is that the surface of the initial well region in the first doping region facing the semiconductor substrate layer is farther away from the semiconductor substrate layer than the surfaces of the initial well regions on both sides of the first doping region facing the semiconductor substrate layer.

[0129] Reference below Figures 17 to 23 The preparation method of semiconductor power devices is introduced.

[0130] refer to Fig.17 , Fig.17 For Figure 6Based on the schematic diagram, an initial well region is formed in the drift layer 110 on both sides of the first doping region 200 and in the first doping region 200, the doping concentration of the initial well region 220a in the first doping region 200 is less than the doping concentration of the initial well region 210 on both sides of the first doping region 200, and a side surface of the initial well region 220a in the first doping region 200 facing the semiconductor substrate layer 100 is away from the semiconductor substrate layer 100 relative to the side surface of the first doping region 200 facing the semiconductor substrate layer 100.

[0131] In one embodiment, the initial well regions 210 on both sides of the first doping region 200 have their surfaces facing the semiconductor substrate layer 100 farther away from the semiconductor substrate layer 100 than the surface of the first doping region 200 facing the semiconductor substrate layer 100 .

[0132] In one embodiment, the initial well region 220 a in the first doping region 200 faces the semiconductor substrate layer 100 and is further away from the semiconductor substrate layer 100 than the initial well regions 210 on both sides of the first doping region 200 face the semiconductor substrate layer 100 .

[0133] The process of forming the initial well region includes an ion implantation process. In the process of forming the initial well region in the drift layer 110 on both sides of the first doping region 200 and in the first doping region 200, since part of the well ions implanted into the first doping region 200 by the ion implantation process will be neutralized with the doping ions in the first doping region 200, the doping concentration of the formed initial well region 220a is less than the doping concentration of the initial well region 210.

[0134] In one embodiment, the concentration distribution of the trapped ions injected into the first doping region 200 by the ion implantation process for forming the initial well region generally presents a regularity along the thickness direction: the concentration of the middle region in the region of the injected well ions is relatively high and the concentration of the region close to the bottom surface of the first doping region 200 is relatively low, that is, the concentration of the trapped ions in the first doping region 200 in the partial region close to the bottom surface of the first doping region 200 is relatively low, so the trapped ions in the partial region close to the bottom surface of the first doping region 200 are neutralized by the doped ions in the first doping region 200, and the partial region close to the bottom surface of the first doping region 200 with the trapped ions presents the conductivity type of the first doping region 200. For the region with a relatively high concentration of the trapped ions in the first doping region 200, part of the trapped ions are neutralized with the doped ions in the first doping region 200, and the remaining well ions in the region make the conductivity type of the region opposite to that of the first doping region 200, forming the initial well region 220a.

[0135] refer to Fig.18A first initial source region 230 and a second source region 170 are formed in the drift layer 110 . The conductivity type of the first initial source region 230 is the same as that of the drift layer 110 and is opposite to that of the second source region 170 . The second source region 170 is located on both sides of the first initial source region 230 .

[0136] The process of forming the first initial source region 230 includes an ion implantation process. The process of forming the second source region 170 includes an ion implantation process.

[0137] refer to Fig.19 , forming a trench C1 in the first doping region 200 that penetrates the initial well region 220a in the first doping region 200 and extends to the bottom of the initial well region 220a, wherein the lateral dimension of the trench C1 is smaller than the lateral dimension of the first doping region 200, and the bottom surface of the trench C1 is away from the semiconductor substrate layer 100 relative to the surface of the first doping region 200 on the side facing the semiconductor substrate layer 100, wherein the remaining initial well region around the trench C1 forms a well region 150a, the remaining first doping region 200 around the trench C1 forms a second doping protection layer 130, and the remaining first initial source region 230 around the trench C1 forms a first source region 160.

[0138] The well region 150a is located at both sides of the gate structure along the width direction. The first source region 160 is located at both sides of the gate structure along the width direction.

[0139] The remaining initial well region 210 and the initial well region 220 a around the trench C1 form the well region 150 a .

[0140] Since the doping concentration of the initial well region 220a is lower than the doping concentration of the initial well region 210, and the remaining initial well region 220a around the trench C1 constitutes the channel region 151, the doping concentration of the channel region 151 is lower than the doping concentration of the well region 150a outside the channel region 151.

[0141] In this embodiment, the method further includes: before forming the trench C1, forming a mask layer Y on a portion of the first initial source region 230 and the second source region 170; etching the initial well region 220a and the first doped region 200 at the bottom of the initial well region 220a using the mask layer Y as a mask to form a trench C1 in the first doped region 200 that penetrates the initial well region 220a and extends to the bottom of the initial well region 220a. The material of the mask layer Y includes photoresist or silicon oxide.

[0142] The well region 150a includes a first well region 1501a (refer to Fig.23 ) and the first well region 1501a toward the second well region 1502a on the side of the semiconductor substrate layer 100 (reference Fig.23), the second well region 1502a is in contact with the first well region 1501a; a portion of the first well region 1501a serves as the channel region 151; and the second doped protection layer 130 on the side wall of the gate structure is located between the second well region 1502a and the gate structure.

[0143] In one embodiment, the doping concentration of the second well region 1502 a is less than the doping concentration of the first well region 1501 a outside the channel region 151 .

[0144] Since the second well region 1502a is in contact with the second doped protection layer 130 on the side wall of the gate structure, the longitudinal distance between the interface position of the second well region 1502a and the drift layer 110 at the bottom of the second well region 1502a to the surface of the first doped protection layer 140 facing the semiconductor substrate layer 100 is small, so that the depletion of the drift layer 110 at the bottom of the second well region 1502a and the second well region 1502a can better protect the gate dielectric layer.

[0145] refer to Fig. 20 , forming a sidewall Y1 on the sidewall of the trench C1; after forming the trench C1, forming a first doped protection layer 140 in the drift layer 110 at a portion of the bottom of the trench C1.

[0146] The process of forming the first doped protection layer 140 in the drift layer 110 at the bottom of the trench C1 is as follows: ion implantation is performed on the drift layer 110 at the bottom of the trench C1 using the sidewall Y1 as a mask to form the first doped protection layer 140. Further, ion implantation is performed on the drift layer 110 at the bottom of the trench C1 using the sidewall Y1 and the mask layer Y as masks to form the first doped protection layer 140.

[0147] It should be noted that in other embodiments, the sidewall Y1 may not be formed.

[0148] The second doping protection layer 130 is located on both sides of the first doping protection layer 140 along the width direction of the gate structure and also surrounds the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 .

[0149] refer to Fig.21 After forming the first doping protection layer 140, the sidewall Y1 is removed; after forming the first doping protection layer 140, the mask layer Y is removed.

[0150] The mask layer Y is removed after the sidewall spacer Y1 is removed, or the mask layer Y is removed before the sidewall spacer Y1 is removed.

[0151] refer to Fig. 22, a gate structure is formed in the trench C, the gate structure including a gate dielectric layer 121 and a gate electrode layer 122; a drain electrode layer 180 is formed on a surface of the semiconductor substrate layer 100 facing away from the drift layer 110.

[0152] Another embodiment of the present invention also provides a method for preparing a semiconductor power device. The difference between this embodiment and the previous embodiment is that the second doping protection layer 130 is located on both sides of the first doping protection layer 140a along the width direction of the gate structure and does not surround the surface of the first doping protection layer 140a facing the semiconductor substrate layer 100.

[0153] Reference below Figure 24 to Figure 25 This paper introduces the preparation method of semiconductor power devices.

[0154] refer to Fig.24 , Fig.24 For Fig.19 Based on the schematic diagram, a sidewall Y1 is formed on the sidewall of the trench C1; and a first doped protection layer 140a is formed in the drift layer 110 at a portion of the bottom of the trench C.

[0155] The process of forming the first doped protection layer 140a in the drift layer 110 at the bottom of part of the trench C1 is an ion implantation process, and the depth of the ion implantation process is controlled so that the second doped protection layer 130 is located on both sides of the first doped protection layer 140a along the width direction of the gate structure and does not surround the surface of the first doped protection layer 140a facing the semiconductor substrate layer 100.

[0156] The process of forming the first doped protective layer 140a in the drift layer 110 at the bottom of the trench C1 is as follows: ion implantation is performed on the drift layer 110 at the bottom of the trench C1 using the sidewall Y1 as a mask to form the first doped protective layer 140a. Further, ion implantation is performed on the drift layer 110 at the bottom of the trench C1 using the sidewall Y1 and the mask layer Y as a mask to form the first doped protective layer 140a.

[0157] It should be noted that in other embodiments, the sidewall Y1 may not be formed.

[0158] refer to Fig.25 , remove the side wall Y1 and the mask layer Y; after removing the side wall Y1 and the mask layer Y, form a gate structure in the trench C1, the gate structure including a gate dielectric layer 121 and a gate electrode layer 122; form a drain electrode layer 180 on the surface of the semiconductor substrate layer 100 away from the drift layer 110.

[0159] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A semiconductor power device, characterized in that: include: Semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer; a gate structure located in the drift layer; Well regions are respectively located in the drift layer on both sides of the gate structure; A protection unit in the drift layer surrounding the bottom surface and part of the sidewall of the gate structure; the protection unit comprises: a first doped protection layer located in the drift layer at the bottom of the gate structure; A second doped protective layer is located in the drift layer on part of the sidewall and part of the bottom of the gate structure, the conductivity type of the first doped protective layer is the same as the conductivity type of the well region and is opposite to the conductivity type of the second doped protective layer, the doping concentration of the second doped protective layer is greater than the doping concentration of the drift layer, and the second doped protective layer and the first doped protective layer form a PN junction.

2. The semiconductor power device according to claim 1, characterized in that: A partial area of ​​the well region serves as a channel region, the channel region contacts a side wall of the gate structure, and a doping concentration of the channel region is lower than a doping concentration of the well region outside the channel region.

3. The semiconductor power device according to claim 2, characterized in that: The doping concentration of the channel region is 1E16atom / cm 3 ~5E17atom / cm 3 ; The doping concentration of the well region outside the channel region is 5E16atom / cm 3 ~2E18atom / cm 3 .

4. The semiconductor power device according to claim 1, characterized in that: The well region includes a first well region and a second well region on the side of the first well region facing the semiconductor substrate layer, the second well region is in contact with the first well region; a portion of the first well region serves as a channel region; and the second doping protection layer on the side wall of the gate structure is located between the second well region and the gate structure.

5. The semiconductor power device according to claim 4, characterized in that: The doping concentration of the second well region is lower than the doping concentration of the first well region outside the channel region.

6. The semiconductor power device according to claim 2, characterized in that: A surface of the channel region facing the semiconductor substrate layer is flush with a surface of the well region outside the channel region facing the semiconductor substrate layer.

7. The semiconductor power device according to claim 1, 4 or 6, characterized in that: A longitudinal distance between a surface of the well region facing the semiconductor substrate layer and a surface of the first doping protection layer facing the semiconductor substrate layer is 0.3 micrometers to 1.5 micrometers.

8. The semiconductor power device according to claim 1, characterized in that: The doping concentration of the second doping protection layer is 2 to 10 times the doping concentration of the drift layer.

9. The semiconductor power device according to claim 1, characterized in that: The second doped protection layer is located on both sides of the first doped protection layer along the width direction of the gate structure and does not surround the surface of the first doped protection layer facing the semiconductor substrate layer; Alternatively, the second doping protection layer is located on both sides of the first doping protection layer along the width direction of the gate structure and also surrounds the surface of the first doping protection layer facing the semiconductor substrate layer.

10. The semiconductor power device according to claim 1, characterized in that: The doping concentration of the first doping protection layer is greater than the doping concentration of the second doping protection layer.

11. The semiconductor power device according to claim 1, characterized in that: The semiconductor power device is a SiC-based semiconductor power device.

12. A method for preparing a semiconductor power device, characterized in that: include: forming a drift layer on one side of the semiconductor substrate layer; forming a gate structure, a well region and a protection unit in the drift layer; The well regions are respectively located in the drift layer on both sides of the gate structure; The protection unit surrounds the bottom surface and part of the side wall of the gate structure; Forming the protection unit includes: forming a first doped protection layer, wherein the first doped protection layer is located in the drift layer at the bottom of the gate structure portion; A second doped protective layer is formed, and the second doped protective layer is located in the drift layer at a portion of the sidewall and a portion of the bottom of the gate structure. The conductivity type of the first doped protective layer is the same as the conductivity type of the well region and is opposite to the conductivity type of the second doped protective layer. The doping concentration of the second doped protective layer is greater than the doping concentration of the drift layer. The second doped protective layer and the first doped protective layer form a PN junction.

13. The method for preparing a semiconductor power device according to claim 12, characterized in that: The process of forming the gate structure, the well region and the protection unit in the drift layer includes: forming a first doping region extending from a surface of the drift layer facing away from the semiconductor substrate to a part of the thickness of the drift layer; forming an initial well region in the drift layer on both sides of the first doping region and in the first doping region, wherein the doping concentration of the initial well region in the first doping region is less than the doping concentration of the initial well regions on both sides of the first doping region, and a surface of the initial well region in the first doping region facing the semiconductor substrate layer is away from the semiconductor substrate layer relative to a surface of the first doping region facing the semiconductor substrate layer; forming a trench in the first doping region that penetrates the initial well region in the first doping region and extends to the bottom of the initial well region, wherein the lateral dimension of the trench is less than the lateral dimension of the first doping region, and the bottom surface of the trench is away from the semiconductor substrate layer relative to a surface of the first doping region facing the semiconductor substrate layer; wherein the remaining initial well region around the trench forms the well region, and the remaining first doping region around the trench forms the second doping protection layer; after forming the trench, forming a first doping protection layer in the drift layer at a part of the bottom of the trench.

14. The method for preparing a semiconductor power device according to claim 13, characterized in that: A surface of the initial well region in the first doping region facing the semiconductor substrate layer is flush with surfaces of the initial well regions on both sides of the first doping region facing the semiconductor substrate layer; Alternatively, a surface of the initial well region in the first doping region facing the semiconductor substrate layer is farther away from the semiconductor substrate layer than a surface of the initial well region on both sides of the first doping region facing the semiconductor substrate layer.

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