Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel, wherein the array substrate includes a substrate, a first metal layer, a gate insulating layer, a second metal layer, a first passivation layer, a pixel electrode, a third metal layer and a common electrode; the first metal layer is arranged on the substrate, and the first metal layer includes a gate; the gate insulating layer is arranged on the substrate and covers the first metal layer; the second metal layer is arranged on the gate insulating layer, and the second metal layer includes a source and a drain; the pixel electrode is arranged on the gate insulating layer and electrically overlaps with the drain; the first passivation layer is arranged on the gate insulating layer and covers the second metal layer and the pixel electrode; the third metal layer is arranged on the first passivation layer, and the third metal layer includes a first connecting electrode and a second connecting electrode, and the second connecting electrode is electrically connected to the gate; the common electrode is arranged on the first passivation layer, and the common electrode is electrically overlapped with the first connecting electrode.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to an array substrate and a display panel. Background Art

[0002] In existing array substrates, the first metal layer at the bottom layer is generally used as the gate line and the common electrode line to transmit the gate signal and the common signal. In order to prevent signal short circuit, a safe distance needs to be reserved between the gate line and the common electrode line, which leads to a decrease in the pixel aperture ratio and the transmittance. In addition, since the common electrode that needs to access the common signal is usually set on the upper side of the first metal layer, and the second metal layer where the common electrode is located is separated from the first metal layer by the PV layer (passivation layer), it is necessary to open a hole in the PV layer (passivation layer) to achieve the bridging of the common electrode and the common electrode line. However, due to the limitation of the setting position of the common electrode line, the position of the opening of the PV layer is too close to the pixel opening area. At the same time, due to the limitation of the existing process level, the opening edge of the PV layer will appear uneven, resulting in poor fluidity of the alignment liquid around the opening of the PV layer, thereby causing the alignment liquid to accumulate, and then causing the problem of uneven brightness of the panel display. Summary of the Invention

[0003] Embodiments of the present application provide an array substrate and a display panel, which improve the problem of uneven display brightness of the panel while increasing the pixel aperture ratio and light transmittance.

[0004] In a first aspect, an embodiment of the present application provides an array substrate, comprising:

[0005] substrate;

[0006] A first metal layer is provided on the substrate, wherein the first metal layer includes a gate;

[0007] a gate insulating layer, disposed on the substrate and covering the first metal layer;

[0008] A second metal layer is provided on the gate insulating layer, wherein the second metal layer includes a source electrode and a drain electrode;

[0009] a pixel electrode, disposed on the gate insulating layer and electrically connected to the drain electrode;

[0010] a first passivation layer, disposed on the gate insulating layer and covering the second metal layer and the pixel electrode;

[0011] A third metal layer is provided on the first passivation layer, the third metal layer includes a first connecting electrode and a second connecting electrode, the second connecting electrode is electrically connected to the gate; and

[0012] A common electrode is disposed on the first passivation layer, and the common electrode is electrically connected to the first connecting electrode.

[0013] In one embodiment, the common electrode corresponds to the pixel electrode in position, and the orthographic projection of the common electrode on the substrate covers the orthographic projection of the pixel electrode on the substrate;

[0014] The first connecting electrode and the common electrode are arranged side by side, and two opposite ends of the first connecting electrode and the common electrode are electrically overlapped.

[0015] In one embodiment, the common electrode is provided on the entire surface;

[0016] The first connecting electrode is disposed on a side of the common electrode away from the first passivation layer and is in electrical contact with the common electrode.

[0017] In one embodiment, the array substrate further includes an active layer, and the active layer is disposed on the gate insulating layer;

[0018] The source electrode and the drain electrode are arranged on the active layer. One side of the drain electrode extends along the side of the active layer to be located above the gate insulating layer and is electrically connected to the pixel electrode.

[0019] In one embodiment, the array substrate further includes an active layer, and the active layer is disposed on the gate insulating layer;

[0020] The source electrode and the drain electrode are arranged on the active layer, and one side of the pixel electrode extends along the side of the active layer to the drain electrode and is in electrical contact with the drain electrode.

[0021] In one embodiment, the thickness of the third metal layer is set to

[0022] In one embodiment, the array substrate further includes:

[0023] a second passivation layer, the second passivation layer being disposed on the first passivation layer and covering the first connecting electrode and the second connecting electrode;

[0024] an alignment layer, the alignment layer being disposed on the second passivation layer and being disposed on the entire surface; and

[0025] A spacer column is arranged on the alignment layer.

[0026] In one embodiment, the second passivation layer includes a first isolation portion covering the first connecting electrode and a second isolation portion covering the second connecting electrode. The first isolation portion and the second isolation portion form a limiting retaining wall for limiting the spacer column.

[0027] In one embodiment, the array substrate includes a plurality of scan lines and a plurality of data lines arranged in a vertical and horizontal manner to define a plurality of pixel areas arranged in an array, each of the pixel areas correspondingly includes a sub-pixel, the sub-pixel includes a thin film transistor and the pixel electrode spaced apart in a first direction, the thin film transistor includes the gate, the source, and the drain;

[0028] The scan line extends along the second direction and is electrically connected to the gate;

[0029] The first connecting electrode is located at the periphery of the sub-pixel and overlaps with the scan line and the data line;

[0030] The second connecting electrode extends along the first direction. The first connecting electrode is located within a region where the thin film transistor is located and partially overlaps with the drain electrode.

[0031] In a second aspect, an embodiment of the present application provides a display panel, comprising an array substrate and a color filter substrate disposed opposite to each other, and a liquid crystal layer disposed between the array substrate and the color filter substrate;

[0032] Wherein, the array substrate is configured as the above-mentioned array substrate, and the spacer columns of the array substrate are connected to the color filter substrate.

[0033] Beneficial effect: In the array substrate provided by the present application, a gate is provided on a substrate, a gate insulating layer covering the gate is provided on the substrate, a source and a drain are provided on the gate insulating layer, a pixel electrode is provided on the gate insulating layer, a first passivation layer covering the second metal layer and the pixel electrode is provided on the gate insulating layer, a third metal layer and the common electrode are provided on the first passivation layer, the third metal layer includes a first connecting electrode and a second connecting electrode, the first connecting electrode is electrically connected to the common electrode, and the second connecting electrode is electrically connected to the gate through a first via hole; it can be seen that since the pixel electrode and the common electrode are both prepared in the driving circuit layer of the array substrate, the array substrate adopts HFS (English full name: High transmission Fringe Field Switching, Chinese abbreviation: high transmission fringe field switching) display mode; and, since a third metal layer is added to the first passivation layer, the common electrode is connected to the gate through the third metal layer, so the common electrode line set in the same layer as the gate in the prior art can be eliminated, and there is no need to reserve a safety distance in each sub-pixel, thereby increasing the pixel aperture ratio and light transmittance; at the same time, the common electrode and the first connecting electrode are set in the same layer and electrically overlapped, so the contact hole is eliminated on the first passivation layer and at a position close to the pixel opening, thereby improving the flow uniformity of the alignment liquid and improving the problem of uneven brightness of the panel display. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0035] Figure 1 A first film layer diagram of a display panel provided in an embodiment of the present application;

[0036] Figure 2 A second film layer diagram of a display panel provided in an embodiment of the present application;

[0037] Figure 3 A film layer diagram of a display panel (from another perspective) provided in an embodiment of the present application;

[0038] Figure 4 A top view of the third metal layer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0040] In the description of this application, it should be understood that the terms "upper," "lower," "front," "back," "left," "right," "inner," and "outer," etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of this application and should not be construed as limiting this application. Furthermore, unless otherwise expressly provided or limited, a first feature being "above" or "below" a second feature merely indicates that the first feature is at a higher or lower level than the second feature, and does not indicate a direct connection.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only, and features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0042] The disclosure below provides many different embodiments for realizing the different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples, and the purpose is not to limit the present application. In addition, the examples of various specific processes and materials provided in the present application, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0043] The embodiments of the present application provide an array substrate and a display panel. The display panel may be a display panel of a mobile phone, a computer, a tablet, a display screen, etc., and is not limited here.

[0044] In a first aspect, an embodiment of the present application provides an array substrate 1. Figures 1 to 3The array substrate 1 includes a substrate 10, a first metal layer 20, a gate insulating layer 30, a second metal layer 40, a pixel electrode 50, a first passivation layer 60, a third metal layer 70 and a common electrode 80; the first metal layer 20 is arranged on the substrate 10, and the first metal layer 20 includes a gate 201; the gate insulating layer 30 is arranged on the substrate 10 and covers the first metal layer 20; the second metal layer 40 is arranged on the gate insulating layer 30, and the second metal layer 40 includes a source 401 and a drain 402; the pixel electrode 50 is arranged on The first passivation layer 60 is arranged on the gate insulating layer 30 and electrically overlaps with the drain electrode 402; the first passivation layer 60 is arranged on the gate insulating layer 30 and covers the second metal layer 40 and the pixel electrode 50; the third metal layer 70 is arranged on the first passivation layer 60, and the third metal layer 70 includes a first connecting electrode 701 and a second connecting electrode 702, and the second connecting electrode 702 is electrically connected to the gate 201; the common electrode 80 is arranged on the first passivation layer 60, and the common electrode 80 is electrically overlapped with the first connecting electrode 701.

[0045] In the array substrate 1 provided in the present application, a gate 201 is provided on a substrate 10, a gate insulating layer 30 covering the gate 201 is provided on the substrate 10, a source 401 and a drain 402 are provided on the gate insulating layer 30, a pixel electrode 50 is provided on the gate insulating layer 30, a first passivation layer 60 covering the second metal layer 40 and the pixel electrode 50 is provided on the gate insulating layer 30, a third metal layer 70 and the common electrode 80 are provided on the first passivation layer 60, the third metal layer 70 includes a first connecting electrode 701 and a second connecting electrode 702, the first connecting electrode 701 is electrically connected to the common electrode 80, and the second connecting electrode 702 is electrically connected to the gate 201; it can be seen that since the pixel electrode 50 and the common electrode 80 are both prepared in the driving circuit layer of the array substrate 1, the array substrate 1 adopts HFS (English full name: High transmission Fringe Field Switching, Chinese abbreviation: high transmission edge field switching) display mode; and, since a third metal layer 70 is added to the first passivation layer 60, the common electrode 80 is connected to the gate 201 through the third metal layer 70, so the common electrode 80 line set on the same layer as the gate 201 in the prior art can be eliminated, and there is no need to reserve a safety distance in each sub-pixel d, thereby increasing the pixel aperture ratio and light transmittance; at the same time, the common electrode 80 and the first connecting electrode 701 are set on the same layer and electrically overlapped, so the opening of the contact hole on the first passivation layer 60 and at a position close to the pixel opening is cancelled, thereby improving the flow uniformity of the alignment liquid and improving the problem of uneven brightness of the panel display.

[0046] The present application does not impose any specific limitation on the arrangement of the common electrode 80 and the pixel electrode 50 .

[0047] See also Figure 1 In the first embodiment of the present application, the common electrode 80 corresponds to the pixel electrode 50 in position, and the orthographic projection of the common electrode 80 on the substrate 10 overlaps the orthographic projection of the pixel electrode 50 on the substrate 10. The first connecting electrode 701 is arranged side by side with the common electrode 80, and the first connecting electrode 701 and the common electrode 80 are electrically overlapped at two opposite ends. The side-by-side arrangement of the first connecting electrode 701 and the common electrode 80 can reduce the overall thickness of the array substrate 1.

[0048] See also Figure 2In the second embodiment of the present application, the common electrode 80 is provided on the entire surface; the first connecting electrode 701 is provided on the side of the common electrode 80 away from the first passivation layer 60 and is in electrical contact with the common electrode 80. A horizontal magnetic field is formed between the common electrode 80 and the pixel electrode 50 to control the deflection of the liquid crystal in the liquid crystal layer 3. The entire surface of the common electrode 80 not only simplifies the production of the common electrode 80, but also adaptably increases the area of ​​the pixel electrode 50, thereby increasing the coverage of the horizontal magnetic field and improving light transmittance.

[0049] The present application does not impose any specific limitation on the connection method between the drain electrode 402 and the pixel electrode 50 .

[0050] See also Figure 1 In the first embodiment of the present application, the array substrate 1 further includes an active layer 90, which is disposed on the gate insulating layer 30; the source electrode 401 and the drain electrode 402 are disposed on the active layer 90, and one side of the drain electrode 402 extends along the side of the active layer 90 to be located above the gate insulating layer 30, and is electrically overlapped with the pixel electrode 50.

[0051] See also Figure 2 In the second embodiment of the present application, the array substrate 1 further includes an active layer 90, which is disposed on the gate insulating layer 30. The source electrode 401 and the drain electrode 402 are disposed on the active layer 90. One side of the pixel electrode 50 extends along the side of the active layer 90 to the drain electrode 402 and is in electrical contact with the drain electrode 402. The common electrode 80 is disposed on the entire surface, and the pixel electrode 50 extends to the covered portion of the drain electrode 402, thereby increasing the area of ​​the pixel electrode 50, thereby increasing the coverage of the horizontal magnetic field and improving light transmittance.

[0052] In this application, the thickness of the third metal layer 70 is set to In this way, the overall thickness of the array substrate 1 will not be affected.

[0053] In this application, the thickness of the second passivation layer 100 is set to In this way, the overall thickness of the array substrate 1 will not be affected.

[0054] Please see further Figure 1 and Figure 2The array substrate 1 further includes a second passivation layer 100, an alignment layer 110 and a spacer column 120; the second passivation layer 100 is arranged on the first passivation layer 60 and covers the first connecting electrode 701 and the second connecting electrode 702; the alignment layer 110 is arranged on the second passivation layer 100, and the alignment layer 110 is arranged on the entire surface; the spacer column 120 is arranged on the alignment layer 110.

[0055] In one embodiment, the second passivation layer 100 includes a first isolation portion covering the first connection electrode 701 and a second isolation portion covering the second connection electrode 702. The first isolation portion and the second isolation portion enclose a limiting retaining wall 130 for limiting the spacer column 120. It can be seen that the third metal layer 70 and the second passivation layer 100 both have thicknesses. The stacking of the first isolation portion and the first connection electrode 701, and the stacking of the second isolation portion and the second connection electrode 702 form a protrusion on the first passivation layer 60, so that the first isolation portion and the second isolation portion enclose a limiting retaining wall 130 for limiting the spacer column 120 and preventing the spacer column 120 from sliding when the array substrate 1 and the color filter substrate 2 are assembled. This improves the phenomenon of broken bright spots and blue-white spots caused by the sliding of the spacer column 120, thereby improving the quality of the display panel 1000.

[0056] Please see further Figure 3In one embodiment, the array substrate further includes an auxiliary electrode layer 140, which is arranged between the second passivation layer 100 and the alignment layer 110. The auxiliary electrode layer 140 is in a non-pixel opening area. The auxiliary electrode layer 140 includes a first auxiliary electrode 1401 and a second auxiliary electrode 1402 that are spaced apart. The first passivation layer 60 is provided with a first contact hole at a position corresponding to the second metal layer 40 and a second contact hole at a position corresponding to the first metal layer 20. The second passivation layer 100 is provided with a third contact hole at a position corresponding to the first contact hole and a fourth contact hole at a position corresponding to the second contact hole. A fifth contact hole is opened on the gate insulating layer 30 at a position corresponding to the second contact hole. The first auxiliary electrode 1401 is connected to the gate insulating layer 30 via the first contact hole and the second contact hole. The third contact hole is electrically connected to the second metal layer 40, and the first auxiliary electrode 1401 is electrically connected to the first metal layer 20 via the fourth contact hole, the second contact hole and the fifth contact hole; the gate insulation layer 30 is also provided with a sixth contact hole at a position corresponding to the first metal layer 20, the first passivation layer 60 is also provided with a seventh contact hole at a position corresponding to the sixth contact hole, the second passivation layer 100 is also provided with an eighth contact hole at a position corresponding to the seventh contact hole, and the second passivation layer 100 is provided with a ninth contact hole at a position corresponding to the third metal layer, the second auxiliary electrode 1402 is electrically connected to the gate 201 via the eighth contact hole, the seventh contact hole and the sixth contact hole, and the second auxiliary electrode 1402 is electrically connected to the second connecting electrode 702 via the ninth contact hole.

[0057] See also Figure 4 The array substrate 1 includes a plurality of scan lines a and a plurality of data lines b arranged in a vertical and horizontal manner to define a plurality of pixel areas c arranged in an array, each of the pixel areas c corresponds to a sub-pixel d, and the sub-pixel d includes a thin film transistor d1 and the pixel electrode 50 arranged at intervals in the first direction F1, and the thin film transistor d1 includes the gate 201, the source 401 and the drain 402; the scan line a extends along the second direction F2 and is electrically connected to the gate 201; the first connection electrode 701 is located at the periphery of the sub-pixel d and is overlapped with the scan line a and the data line b; the second connection electrode 702 extends along the first direction F1, the first connection electrode 701 is within the region where the thin film transistor d1 is located, and partially overlaps with the drain 402.

[0058] It can be understood that the third metal layer 70 is not light-transmissive, and the first connecting electrode 701 is arranged along the routing of the scanning line a and the data line b, so as to avoid the first connecting electrode 701 appearing in the pixel opening, thereby improving the pixel opening ratio; and the second connecting electrode 702 is within the area where the thin film transistor d1 is located, and will not affect the pixel opening ratio.

[0059] In a second aspect, embodiments of the present application provide a display panel 1000. The display panel 1000 includes an array substrate 1 and a color filter substrate 2 disposed opposite each other, and a liquid crystal layer 3 disposed between the array substrate 1 and the color filter substrate 2. Spacer columns 120 of the array substrate 1 are connected to the color filter substrate 2. It should be noted that the array substrate 1 is configured as the aforementioned array substrate 1, that is, the array substrate 1 has all the aforementioned embodiments of the array substrate 1. The display panel 1000 also has all the technical features of all the aforementioned embodiments of the array substrate 1, and also has all the beneficial effects brought about by all the technical features, which will not be described in detail here.

[0060] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0061] The above is a detailed introduction to an array substrate and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: The array substrate includes: substrate; A first metal layer is provided on the substrate, wherein the first metal layer includes a gate; a gate insulating layer, disposed on the substrate and covering the first metal layer; A second metal layer is provided on the gate insulating layer, wherein the second metal layer includes a source electrode and a drain electrode; a pixel electrode, disposed on the gate insulating layer and electrically connected to the drain electrode; a first passivation layer, disposed on the gate insulating layer and covering the second metal layer and the pixel electrode; A third metal layer is provided on the first passivation layer, the third metal layer includes a first connecting electrode and a second connecting electrode, the second connecting electrode is electrically connected to the gate; and A common electrode is disposed on the first passivation layer, and the common electrode is electrically connected to the first connecting electrode.

2. The array substrate according to claim 1, wherein: The common electrode corresponds to the pixel electrode in position, and the orthographic projection of the common electrode on the substrate covers the orthographic projection of the pixel electrode on the substrate; The first connecting electrode and the common electrode are arranged side by side, and two opposite ends of the first connecting electrode and the common electrode are electrically overlapped.

3. The array substrate according to claim 1, wherein: The common electrode is arranged on the entire surface; The first connecting electrode is disposed on a side of the common electrode away from the first passivation layer and is in electrical contact with the common electrode.

4. The array substrate according to claim 1, wherein: The array substrate further comprises an active layer, wherein the active layer is arranged on the gate insulating layer; The source electrode and the drain electrode are arranged on the active layer. One side of the drain electrode extends along the side of the active layer to be located above the gate insulating layer and is electrically connected to the pixel electrode.

5. The array substrate according to claim 1, wherein: The array substrate further comprises an active layer, wherein the active layer is arranged on the gate insulating layer; The source electrode and the drain electrode are arranged on the active layer, and one side of the pixel electrode extends along the side of the active layer to the drain electrode and is in electrical contact with the drain electrode.

6. The array substrate according to claim 1, wherein: The thickness of the third metal layer is set to 7. The array substrate according to claim 1, wherein: The array substrate further includes: a second passivation layer, the second passivation layer being disposed on the first passivation layer and covering the first connecting electrode and the second connecting electrode; an alignment layer, the alignment layer being disposed on the second passivation layer and being disposed on the entire surface; and A spacer column is arranged on the alignment layer.

8. The array substrate according to claim 7, wherein: The second passivation layer includes a first isolation portion covering the first connection electrode and a second isolation portion covering the second connection electrode. The first isolation portion and the second isolation portion form a limiting barrier wall for limiting the spacer column.

9. The array substrate according to claim 1, wherein: The array substrate includes a plurality of scan lines and a plurality of data lines arranged in a vertical and horizontal manner to define a plurality of pixel areas arranged in an array, each of the pixel areas corresponding to a sub-pixel, the sub-pixel including a thin film transistor and the pixel electrode spaced apart in a first direction, the thin film transistor including the gate, the source, and the drain; The scan line extends along the second direction and is electrically connected to the gate; The first connecting electrode is located at the periphery of the sub-pixel and overlaps with the scan line and the data line; The second connecting electrode extends along the first direction. The first connecting electrode is located within a region where the thin film transistor is located and partially overlaps with the drain electrode.

10. A display panel, characterized in that: It comprises an array substrate and a color filter substrate which are arranged opposite to each other, and a liquid crystal layer arranged between the array substrate and the color filter substrate; Wherein, the array substrate is configured as the array substrate according to any one of claims 1 to 9, and the spacer columns of the array substrate are connected to the color filter substrate.

Images