A transimpedance amplifier based on a three-stage amplifier and a feed-forward inverting amplifier

Abstract

The application belongs to the technical field of analog integrated circuit design, and discloses a transimpedance amplifier based on a three-stage amplifier and a feedforward inverting amplifier, which comprises a first-stage amplifier, a second-stage amplifier, a third-stage amplifier, a feedforward inverting amplifier and a Miller compensation circuit; the first-stage amplifier, the second-stage amplifier and the third-stage amplifier are connected in series in sequence, the feedforward inverting amplifier is connected with the input end of the first-stage amplifier and the output end of the third-stage amplifier respectively; and the Miller compensation circuit is connected with the second-stage amplifier in parallel; the application can enable the transimpedance amplifier to realize high gain, high bandwidth and high stability at the same time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog integrated circuit design, and particularly relates to a trans-impedance amplifier based on a three-stage amplifier and a feedforward inverting amplifier. BACKGROUND

[0002] In a wireless receiver system, in order to ensure the linearity of the system, the radio frequency signal is often down-converted in current mode, which requires the module following the mixer to have as low an input impedance as possible, so the trans-impedance amplifier is currently widely used. Because the radio frequency signal is down-converted in current mode, the output node impedance of the low noise amplifier in the system is reduced, and the voltage amplification factor is reduced, so the noise performance of the trans-impedance amplifier becomes particularly important. In addition, the linearity, stability, bandwidth and other indicators of the trans-impedance amplifier also need to be considered comprehensively in the design.

[0003] In the prior art, when high gain is achieved, the number of gain stages of the amplifier is usually increased, but the increase in the number of gain stages of the amplifier will also cause insufficient phase margin, so a phase compensation circuit is used to improve the stability of the circuit, but the phase compensation circuit usually sacrifices the bandwidth of the system, so the existing high-gain amplifier cannot simultaneously achieve high stability and high bandwidth. SUMMARY

[0004] The present application provides a trans-impedance amplifier based on a three-stage amplifier and a feedforward inverting amplifier, which can enable the trans-impedance amplifier to achieve high gain, high bandwidth and high stability at the same time.

[0005] The present application provides a trans-impedance amplifier based on a three-stage amplifier and a feedforward inverting amplifier, which can enable the trans-impedance amplifier to achieve high gain, high bandwidth and high stability at the same time.

[0006] The first-stage amplifier, the second-stage amplifier and the third-stage amplifier are connected in series, the feedforward inverting amplifier is connected to the input end of the first-stage amplifier and the output end of the third-stage amplifier respectively, and the Miller compensation circuit is connected in parallel to the second-stage amplifier.

[0007] Further, the first-stage amplifier includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a first resistor and a second resistor.

[0008] The drain of the first PMOS tube is connected to the drain of the first NMOS tube and the high-voltage input end of the first resistor respectively, the source is connected to the drain of the third PMOS tube, and the gate is a differential input end VIN.

[0009] The drain of the second PMOS is connected to the drain of the second NMOS and the high voltage input end of the second resistor respectively, the source is connected to the drain of the third PMOS, and the gate is the differential input end VIP;

[0010] The gates of the first NMOS and the second NMOS are connected to each other and connected to the low voltage input end of the first resistor and the second resistor connected to each other, and the sources of the first NMOS and the second NMOS are grounded;

[0011] The gate of the third PMOS receives the first bias voltage, and the source receives the power supply voltage.

[0012] Further, a common mode detection feedback circuit connected to the second stage amplifier and the third stage amplifier respectively is further included.

[0013] Further, the second stage amplifier includes a third NMOS, a fourth NMOS, a fourth PMOS and a fifth PMOS; the gate of the third NMOS is connected to the drain of the first NMOS, the drain is connected to the drain of the fourth PMOS, and the source is grounded; the gate of the fourth NMOS is connected to the drain of the second NMOS, the drain is connected to the drain of the fifth PMOS, and the source is grounded; the gate of the fourth PMOS and the gate of the fifth PMOS both receive the common mode feedback voltage of the common mode detection feedback circuit, and the sources of the fourth PMOS and the fifth PMOS both receive the power supply voltage.

[0014] Further, the third stage amplifier includes a fifth NMOS, a sixth NMOS, a sixth PMOS and a seventh PMOS; the gate of the fifth NMOS is connected to the gate of the sixth PMOS, and is connected to the Miller compensation circuit, the drain of the third NMOS and the drain of the fourth PMOS respectively, the drain of the fifth NMOS is connected to the drain of the sixth PMOS, and is commonly connected to the feedforward inverting amplifier;

[0015] The gate of the sixth NMOS is connected to the gate of the seventh PMOS, and is connected to the Miller compensation circuit, the drain of the fourth NMOS and the drain of the fifth PMOS respectively, the drain of the sixth NMOS is connected to the drain of the seventh PMOS, and is commonly connected to the feedforward inverting amplifier; the sources of the fifth NMOS and the sixth NMOS are both grounded, and the sources of the sixth PMOS and the seventh PMOS both receive the power supply voltage.

[0016] Further, the feedforward inverting amplifier comprises a seventh NMOS, an eighth NMOS, an eighth PMOS and a ninth PMOS; the gate of the seventh NMOS and the gate of the eighth PMOS are connected to each other and are commonly connected to the gate of the first PMOS, the drain of the seventh NMOS and the drain of the eighth PMOS are connected to each other and are commonly connected to the drain of the fifth NMOS and the drain of the sixth PMOS; the gate of the eighth NMOS and the gate of the ninth PMOS are connected to each other and are commonly connected to the gate of the second PMOS, the drain of the eighth NMOS and the drain of the ninth PMOS are connected to each other and are commonly connected to the drain of the sixth NMOS and the drain of the seventh PMOS; the source of the seventh NMOS and the source of the eighth NMOS are grounded, and the source of the eighth PMOS and the source of the ninth PMOS receive a power supply voltage.

[0017] Further, the Miller compensation circuit comprises a third resistor and a fourth resistor, and a first capacitor and a second capacitor;

[0018] The third resistor is connected in series with the first capacitor, and the fourth resistor is connected in series with the second capacitor;

[0019] The third resistor is connected to the drain of the first NMOS and the gate of the third NMOS respectively; the first capacitor is connected to the drain of the third NMOS, the gate of the fifth NMOS, the drain of the fourth PMOS and the gate of the sixth PMOS respectively;

[0020] The fourth resistor is connected to the drain of the second NMOS and the gate of the fourth NMOS respectively; the second capacitor is connected to the drain of the fourth NMOS, the gate of the sixth NMOS, the drain of the fifth PMOS and the gate of the seventh PMOS respectively.

[0021] Further, the common mode detection feedback circuit comprises a ninth NMOS, a tenth NMOS, an eleventh NMOS, a tenth PMOS, an eleventh PMOS, a fifth resistor, a sixth resistor, a seventh resistor and a third capacitor;

[0022] The source of the ninth NMOS is grounded, the gate is connected to a second bias voltage, and the drain is connected to the source of the tenth NMOS and the source of the eleventh NMOS respectively; the drain of the tenth NMOS is connected to the gate and the drain of the tenth PMOS respectively, and the drain of the eleventh NMOS is connected to the gate and the drain of the eleventh PMOS respectively;

[0023] The sources of the tenth PMOS and the eleventh PMOS receive a power supply voltage;

[0024] The gate of the tenth NMOS is connected to the third resistor, the sixth resistor and the seventh resistor respectively;

[0025] The gate of the eleventh NMOS tube receives a reference voltage; the fifth resistor and the third capacitor are connected in series, the fifth resistor is connected to the gate and the drain of the tenth PMOS tube respectively, and the drain of the tenth PMOS tube outputs a common-mode feedback voltage;

[0026] The sixth resistor is connected to the drains of the seventh PMOS tube and the sixth NMOS tube respectively.

[0027] The seventh resistor is connected to the drains of the sixth PMOS tube and the fifth NMOS tube respectively.

[0028] Further, the first resistor and the second resistor have the same resistance.

[0029] Further, the first bias voltage or the second bias voltage ranges from 10uA to 900uA.

[0030] Further, the open loop gain of the transimpedance amplifier is 100dB.

[0031] Further, the reference voltage is half of the power supply voltage.

[0032] In summary, compared with the prior art, the technical scheme provided by the embodiment of the application has at least the following beneficial effects:

[0033] The transimpedance amplifier based on the three-stage amplifier and the feedforward inverting amplifier provided by the embodiment of the application first realizes high gain of the transimpedance amplifier through the three-stage amplifier in series, and a feedforward inverting amplifier is connected in parallel to the three-stage amplifier, the introduction of the feedforward inverting amplifier compensates for the pole generated at the output node, thereby expanding the bandwidth of the amplifier and improving the stability of the transimpedance amplifier; the situation of sacrificing bandwidth to ensure stability is avoided; in addition, since the transimpedance amplifier usually forms a "parallel-parallel negative feedback" structure when in use, the Miller compensation circuit is arranged between the input node and the output node of the second-stage amplifier, i.e., in parallel to the second-stage amplifier, so that the Miller compensation is not affected by the "parallel-parallel feedback", and the stability of the transimpedance amplifier is further improved. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A signal block diagram of the transimpedance amplifier based on the three-stage amplifier and the feedforward inverting amplifier is provided for an exemplary embodiment of the application.

[0035] Figure 2 A transceiver system block diagram is provided for an exemplary embodiment of the application.

[0036] Figure 3 A parallel-parallel feedback schematic diagram is provided for an exemplary embodiment of the application.

[0037] Figure 4A circuit schematic of a three-stage amplifier and a feed-forward inverting amplifier is provided for one example embodiment of the present application.

[0038] Figure 5 A circuit schematic of a common-mode detection feedback circuit is provided for one example embodiment of the present application.

[0039] BRIEF DESCRIPTION OF DRAWINGS

[0040] M1, first PMOS transistor; M2, second PMOS transistor; M3, first NMOS transistor; M4, second NMOS transistor; M5, third PMOS transistor; M6, third NMOS transistor; M7, fourth NMOS transistor; M8, fourth PMOS transistor; M9, fifth PMOS transistor; M10, fifth NMOS transistor; M11, sixth NMOS transistor; M12, sixth PMOS transistor; M13, seventh PMOS transistor; M14, seventh NMOS transistor; M15, eighth NMOS transistor; M16, eighth PMOS transistor; M17, ninth PMOS transistor; M18, ninth NMOS transistor; M19, tenth NMOS transistor; M20, eleventh NMOS transistor; M21, tenth PMOS transistor; M22, eleventh PMOS transistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments.

[0042] Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0043] See Figure 1 The embodiments of the present application provide a trans-impedance amplifier based on a three-stage amplifier and a feed-forward inverting amplifier, which comprises a first-stage amplifier, a second-stage amplifier, a third-stage amplifier, a feed-forward inverting amplifier and a Miller compensation circuit.

[0044] The first-stage amplifier, the second-stage amplifier and the third-stage amplifier are connected in series in turn, the feed-forward inverting amplifier is connected to the input end of the first-stage amplifier and the output end of the third-stage amplifier respectively, and the Miller compensation circuit is connected in parallel with the second-stage amplifier.

[0045] The first-stage amplifier is Figure 1Gm1, the value of Gm1 represents the gain of the first stage amplifier, the second stage amplifier is Gm2, the value of Gm2 represents the gain of the second stage amplifier, the third stage amplifier is Gm3, the value of Gm3 represents the gain of the third stage amplifier, and the feedforward inverting amplifier is Gmf, the value of Gmf represents the gain of the feedforward inverting amplifier.

[0046] Cc and Rz are the output capacitance and output resistance of the Miller compensation circuit.

[0047] CL is the load capacitance, Cf and Rf are the output capacitance and output resistance of the feedforward inverting amplifier respectively, R11 and C11 are the output resistance and output capacitance of the first stage amplifier respectively, R22 and C22 are the output resistance and output capacitance of the second stage amplifier respectively, and R33 and C33 are the output resistance and output capacitance of the third stage amplifier respectively.

[0048] In the specific implementation process, please refer to Figure 2 , a transimpedance amplifier (TIA) is usually connected behind the receiver mixer, and the down-converted signals flow through the signal paths composed of the first, second and third stage amplifiers in parallel and the path of the feedforward inverting amplifier, and then are received by the low-pass filter.

[0049] In the prior art, the number of amplifier stages is usually two or more, and the problem of insufficient phase margin needs to be handled. With each increase in the number of amplifier stages, the phase delay of the system increases. In a feedback system, this can cause the phase delay to accumulate to 180 degrees or more, making the system in a marginally stable or unstable state. Phase compensation is needed to ensure the stability of the system, but phase compensation usually sacrifices the bandwidth of the system, resulting in the inability to achieve high stability and high bandwidth at the same time.

[0050] In the above embodiment, the transimpedance amplifier structure of the present application adopts a three-stage amplifier plus a feedforward inverting amplifier, and the open-loop gain of the three-stage amplifier can reach 100dB; the introduction of the feedforward inverting amplifier compensates for the pole generated at the output node, expands the bandwidth of the amplifier, and improves the stability of the amplifier.

[0051] In addition, due to the connection relationship, the output of the first stage amplifier is connected to the input of the second stage amplifier, and the output of the second stage amplifier is connected to the input of the third stage amplifier; the input of the feedforward inverting amplifier is connected to the input of the first stage amplifier, and the output of the feedforward inverting amplifier is connected to the output of the third stage amplifier, and the transimpedance amplifier usually adds a shunt-shunt negative feedback on this basis when applied, such as Figure 3 and Figure 4As shown, the input of the first stage amplifier is the gate of M1 and M2, and the output of the first stage amplifier is the drain of M1, M2, M3 and M4; the input of the second stage amplifier is the gate of M6 and M7, and the output of the second stage amplifier is the drain of M6, M8, M7 and M9; the input of the third stage amplifier is the gate of M10, M12, M11 and M13, and the output of the third stage amplifier is the drain of M10, M12, M11 and M13; the input of the feed-forward amplifier is the gate of M14, M16, M15 and M17, and the output is the drain of M14, M16, M15, M17, and the shunt-shunt negative feedback is located between the differential input node VIP of the first stage amplifier and the differential output node VON of the third stage amplifier, and between the input node VIN of the first stage amplifier and the differential output node VOP of the third stage amplifier, and the circuit form is that the eighth resistor R8 and the fourth capacitor C4 are connected in parallel, and the ninth resistor R9 and the fifth capacitor C5 are connected in parallel.

[0052] Since the stability of the transimpedance amplifier is also usually susceptible to shunt-shunt feedback, the present application introduces Miller compensation between the output node and the input node of the second stage amplifier, and separates the introduced pole. Due to the Miller effect, the equivalent capacitance at the input node of the second stage amplifier increases, and the equivalent capacitance at the output decreases, at which time the pole at the input becomes the main pole, and due to the negative feedback, the output impedance at the output decreases, so the pole at the output is pushed out of the unit gain bandwidth and becomes the second secondary pole. The right half plane zero point generated by the Miller compensation can be moved to a far position in the left half plane by adjusting Rz. The first pole introduced by the op-amp output node is not affected by the compensation circuit and is still located within the unit gain bandwidth. The feed-forward compensation adds a zero point in the left half plane to the circuit, and by adjusting the transconductance size of the feed-forward stage, the zero point and the first secondary pole can form a zero-pole pair, thereby reducing the deterioration of the phase margin of the first secondary pole to some extent.

[0053] The proof process is as follows: according to Kirchhoff's current law, the node current equations for the three amplifier nodes are listed as follows:

[0054]

[0055]

[0056]

[0057] where R o and C o are the total output resistance and the total output capacitance of the transimpedance amplifier, respectively.

[0058] R o = R 33 / / R f

[0059] C o = C 33 + C f + C L

[0060] By combining the above three equations, the transfer function of the trans-impedance amplifier can be obtained as:

[0061]

[0062] A = R 11 C 11 + R 22 C 22 + R 11 C c + R 22 C c + R z C c + Gm2R 22 R 11 C c

[0063] C = R 11 R 22 R z C 11 C 22 C c

[0064] D = A·Gm f — Gm1Gm3R 11 R 22 C c + Gm1Gm2Gm3R 11 R 22 R z C c

[0065]

[0066] Analyzing the poles of the transfer function, it is obvious that the output node of the amplifier introduces a pole, which is generally the first-order pole of the amplifier, and is independent of frequency compensation. The expression is as follows:

[0067]

[0068] Next, analyze the poles introduced by (1+As+Bs 2 + Cs 3 ) in the denominator of the transfer function. The cubic polynomial is the same as the denominator of the two-stage Miller-compensated amplifier transfer function, and also has a similar pole distribution as the two-stage Miller-compensated amplifier. Since the pole frequency introduced by the cubic term is very far, the cubic term is ignored here, and it is assumed that Gm2R 22>>1, C c >>C 11 &C 22 , C o >>C 11 &C 22 and assuming that the interval between the two poles is far at this time, the expression of the main pole p1 and the second secondary pole p3 can be obtained:

[0069]

[0070]

[0071] The numerator of the transfer function is analyzed by the same method, and the expression of the two main zeros of the transfer function can be obtained:

[0072]

[0073]

[0074] In some embodiments, referring to Figure 4 , the first-stage amplifier includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M5, a first NMOS transistor M3, a second NMOS transistor M4, a first resistor R1, and a second resistor R2.

[0075] The first resistor R1 and the second resistor R2 have the same resistance value. The drain of the first PMOS transistor M1 is connected to the drain of the first NMOS transistor M3 and the high-voltage input end of the first resistor R1, the source is connected to the drain of the third PMOS transistor M5, and the gate is the differential input end VIN. The drain of the second PMOS transistor M2 is connected to the drain of the second NMOS transistor M4 and the high-voltage input end of the second resistor R2, the source is connected to the drain of the third PMOS transistor M5, and the gate is the differential input end VIP.

[0076] The gates of the first NMOS transistor M3 and the second NMOS transistor M4 are connected to each other and connected to the low-voltage input end of the first resistor R1 and the second resistor R2 connected to each other, and the sources of the first NMOS transistor M3 and the second NMOS transistor M4 are grounded.

[0077] The gate of the third PMOS transistor M5 receives a first bias voltage, and the source receives a power supply voltage.

[0078] Specifically, since the noise of the first stage amplifier contributes most to the total noise, the noise of the amplification tubes M1, M2 and the noise of the load tubes M3, M4 can be reduced. Generally, after the current is determined, the noise of M1 and M2 will not change substantially. Increasing the width-length ratio can slightly reduce the noise of M1 and M2, but will cause the drain voltage of M1 and M2 to change. Therefore, it is more reasonable to reduce the noise of M3 and M4 first. To reduce the noise of M3 and M4, only the channel length needs to be increased, which can reduce their flicker noise and further reduce the input reference noise of the operational amplifier. The MOS tubes in the second stage, the third stage and the feedforward stage can use tubes with moderate channel length, such as 100n, to balance the bandwidth and noise performance.

[0079] See Figure 5 In some embodiments, the transimpedance amplifier of the present application further comprises a common mode detection feedback circuit connected with the second stage amplifier and the third stage amplifier respectively.

[0080] See Figure 4 The second stage amplifier comprises a third NMOS tube M6, a fourth NMOS tube M7, a fourth PMOS tube M8 and a fifth PMOS tube M9. The gate of the third NMOS tube M6 is connected with the drain of the first NMOS tube M3, the drain is connected with the drain of the fourth PMOS tube M8, and the source is grounded. The gate of the fourth NMOS tube M7 is connected with the drain of the second NMOS tube M4, the drain is connected with the drain of the fifth PMOS tube M9, and the source is grounded. The gates of the fourth PMOS tube M8 and the fifth PMOS tube M9 both receive a common mode feedback voltage from the common mode detection feedback circuit, and the sources of the fourth PMOS tube M8 and the fifth PMOS tube M9 both receive a power supply voltage.

[0081] Further, the third stage amplifier comprises a fifth NMOS tube M10, a sixth NMOS tube M11, a sixth PMOS tube M12 and a seventh PMOS tube M13. The gate of the fifth NMOS tube M10 is connected with the gate of the sixth PMOS tube M12, and is connected with the Miller compensation circuit, the drain of the third NMOS tube M6 and the drain of the fourth PMOS tube M8 respectively. The drain of the fifth NMOS tube M10 is connected with the drain of the sixth PMOS tube M12, and is commonly connected to the feedforward inverting amplifier.

[0082] The gate of the sixth NMOS tube M11 is connected with the gate of the seventh PMOS tube M13, and is connected with the Miller compensation circuit, the drain of the fourth NMOS tube M7 and the drain of the fifth PMOS tube M9 respectively. The drain of the sixth NMOS tube M11 is connected with the drain of the seventh PMOS tube M13, and is commonly connected to the feedforward inverting amplifier.

[0083] The source of the fifth NMOS transistor M10 and the source of the sixth NMOS transistor M11 are both grounded, and the source of the sixth PMOS transistor M12 and the source of the seventh PMOS transistor M13 both receive a power supply voltage.

[0084] Further, the feedforward inverting amplifier comprises a seventh NMOS transistor M14, an eighth NMOS transistor M15, an eighth PMOS transistor M16 and a ninth PMOS transistor M17; the gate of the seventh NMOS transistor M14 and the gate of the eighth PMOS transistor M16 are interconnected and are commonly connected to the gate of the first PMOS transistor M1, and the drain of the seventh NMOS transistor M14 and the drain of the eighth PMOS transistor M16 are interconnected and are commonly connected to the drain of the fifth NMOS transistor M10 and the drain of the sixth PMOS transistor M12.

[0085] The gate of the eighth NMOS transistor M15 and the gate of the ninth PMOS transistor M17 are interconnected and are commonly connected to the gate of the second PMOS transistor M2, and the drain of the eighth NMOS transistor M15 and the drain of the ninth PMOS transistor M17 are interconnected and are commonly connected to the drain of the sixth NMOS transistor M11 and the drain of the seventh PMOS transistor M13.

[0086] The source of the seventh NMOS transistor M14 and the source of the eighth NMOS transistor M15 are both grounded, and the source of the eighth PMOS transistor M16 and the source of the ninth PMOS transistor M17 both receive a power supply voltage.

[0087] Further, the Miller compensation circuit comprises a third resistor R3 and a fourth resistor R4, and a first capacitor C1 and a second capacitor C2. Among them, the third resistor R3 and the fourth resistor R4 have the same resistance value.

[0088] The third resistor R3 is connected in series with the first capacitor C1, and the fourth resistor R4 is connected in series with the second capacitor C2.

[0089] The third resistor R3 is connected to the drain of the first NMOS transistor M3 and the gate of the third NMOS transistor M6, respectively; the first capacitor C1 is connected to the drain of the third NMOS transistor M6, the gate of the fifth NMOS transistor M10, the drain of the fourth PMOS transistor M8 and the gate of the sixth PMOS transistor M12, respectively; the fourth resistor R4 is connected to the drain of the second NMOS transistor M4 and the gate of the fourth NMOS transistor M7, respectively; and the second capacitor C2 is connected to the drain of the fourth NMOS transistor M7, the gate of the sixth NMOS transistor M11, the drain of the fifth PMOS transistor M9 and the gate of the seventh PMOS transistor M13, respectively.

[0090] Further, the common mode detection feedback circuit comprises a ninth NMOS transistor M18, a tenth NMOS transistor M19, an eleventh NMOS transistor M20, a tenth PMOS transistor M21, an eleventh PMOS transistor M22, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and a third capacitor C3; the source of the ninth NMOS transistor M18 is connected to the ground, the gate is connected to the second bias voltage, and the drain is connected to the source of the tenth NMOS transistor M19 and the source of the eleventh NMOS transistor M20.

[0091] The drain of the tenth NMOS transistor M19 is connected to the gate and the drain of the tenth PMOS transistor M21, and the drain of the eleventh NMOS transistor M20 is connected to the gate and the drain of the eleventh PMOS transistor M22.

[0092] The first bias voltage BIAS1 or the second bias voltage BIAS2 has a value in the range of 10uA-900uA.

[0093] Specifically, the BIAS2 current of the common mode detection feedback circuit is usually less than or equal to the BIAS1 current of the differential operational amplifier, but this is mainly determined by the bandwidth and response speed of the differential operational amplifier and the common mode detection feedback circuit.

[0094] The source of the tenth PMOS transistor M21 and the source of the eleventh PMOS transistor M22 both receive the power supply voltage.

[0095] The gate of the tenth NMOS transistor M19 is connected to the third resistor R3, the sixth resistor R6 and the seventh resistor R7.

[0096] The gate of the eleventh NMOS transistor M20 receives a reference voltage; the fifth resistor R5 and the third capacitor C3 are connected in series, the fifth resistor R5 is connected to the gate and the drain of the tenth PMOS transistor M21, the drain of the tenth PMOS transistor M21 outputs a common mode feedback voltage; the sixth resistor R6 is connected to the drain of the seventh PMOS transistor M13 and the drain of the sixth NMOS transistor M11; the seventh resistor R7 is connected to the drain of the sixth PMOS transistor M12 and the drain of the fifth NMOS transistor M10.

[0097] The reference voltage is usually half of the power supply voltage VDD, and the sixth resistor R6 and the seventh resistor R7 have the same resistance value.

[0098] The fifth resistor and the third capacitor are connected in series to form the Miller compensation of the common mode detection feedback circuit.

[0099] Specifically, the common mode detection feedback circuit compares the values of VOP, VON and the reference voltage VCM, controls the common mode feedback voltage CMFB according to the comparison result, so that the value of (VOP+VON) / 2 is close to the value of VCM, so that the output CMFB voltage can stabilize the output of M8 and M9, and further stabilize the working state of M10 and M11.

[0100] Any combination of the technical features in the above embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, any combination of the technical features should be considered as within the scope of the present disclosure, as long as the combination is not contradictory.

[0101] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that, for ordinary skilled persons in the art, some modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A transimpedance amplifier based on a three-stage amplifier and a feedforward inverting amplifier, characterized in that, It includes a first-stage amplifier, a second-stage amplifier, a third-stage amplifier, a feedforward inverting amplifier, and a Miller compensation circuit, as well as a common-mode detection feedback circuit connected to the second-stage amplifier and the third-stage amplifier respectively; The first-stage amplifier, the second-stage amplifier, and the third-stage amplifier are connected in series. The feedforward inverting amplifier is connected to the input terminal of the first-stage amplifier and the output terminal of the third-stage amplifier, respectively. The first-stage amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first resistor, and a second resistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the high-voltage input terminal of the first resistor, the source is connected to the drain of the third PMOS transistor, and the gate is the differential input terminal VIN. The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and the high-voltage input terminal of the second resistor, the source is connected to the drain of the third PMOS transistor, and the gate is the differential input terminal VIP. The gates of the first NMOS transistor and the second NMOS transistor are interconnected and connected to each other. The low-voltage input terminal is connected to the first resistor and the second resistor. The sources of the first NMOS transistor and the second NMOS transistor are both grounded. The gate of the third PMOS transistor receives a first bias voltage, and the source receives a power supply voltage. The second-stage amplifier includes a third NMOS transistor, a fourth NMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor. The gate of the third NMOS transistor is connected to the drain of the first NMOS transistor, and the drain is connected to the drain of the fourth PMOS transistor. The source is grounded. The gate of the fourth NMOS transistor is connected to the drain of the second NMOS transistor, and the drain is connected to the drain of the fifth PMOS transistor. The source is grounded. The gates of the fourth PMOS transistor and the fifth PMOS transistor both receive the common-mode feedback voltage of the common-mode detection feedback circuit, and the sources of the fourth PMOS transistor and the fifth PMOS transistor both receive the power supply voltage. The Miller compensation circuit is connected in parallel with the second-stage amplifier.

2. The transimpedance amplifier based on a three-stage amplifier and a feedforward inverting amplifier according to claim 1, characterized in that, The third-stage amplifier includes a fifth NMOS transistor, a sixth NMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor; The gate of the fifth NMOS transistor is connected to the gate of the sixth PMOS transistor, and is respectively connected to the Miller compensation circuit, the drain of the third NMOS transistor and the drain of the fourth PMOS transistor. The drain of the fifth NMOS transistor is connected to the drain of the sixth PMOS transistor, and together they are connected to the feedforward inverting amplifier. The gate of the sixth NMOS transistor is connected to the gate of the seventh PMOS transistor, and is respectively connected to the Miller compensation circuit, the drain of the fourth NMOS transistor and the drain of the fifth PMOS transistor. The drain of the sixth NMOS transistor is connected to the drain of the seventh PMOS transistor, and together they are connected to the feedforward inverting amplifier. The source of the fifth NMOS transistor and the source of the sixth NMOS transistor are both grounded, and the source of the sixth PMOS transistor and the source of the seventh PMOS transistor both receive the power supply voltage.

3. The transimpedance amplifier based on a three-stage amplifier and a feedforward inverting amplifier according to claim 2, characterized in that, The feedforward inverting amplifier includes a seventh NMOS transistor, an eighth NMOS transistor, an eighth PMOS transistor, and a ninth PMOS transistor; The gate of the seventh NMOS transistor is connected to the gate of the eighth PMOS transistor and is also connected to the gate of the first PMOS transistor. The drain of the seventh NMOS transistor is connected to the drain of the eighth PMOS transistor and is also connected to the drain of the fifth NMOS transistor and the drain of the sixth PMOS transistor. The gate of the eighth NMOS transistor is connected to the gate of the ninth PMOS transistor and is also connected to the gate of the second PMOS transistor. The drain of the eighth NMOS transistor is connected to the drain of the ninth PMOS transistor and is also connected to the drain of the sixth NMOS transistor and the drain of the seventh PMOS transistor. The source of the seventh NMOS transistor and the source of the eighth NMOS transistor are both grounded, and the source of the eighth PMOS transistor and the source of the ninth PMOS transistor both receive the power supply voltage.

4. The transimpedance amplifier based on a three-stage amplifier and a feedforward inverting amplifier according to claim 3, characterized in that, The Miller compensation circuit includes a third resistor and a fourth resistor, as well as a first capacitor and a second capacitor. The third resistor is connected in series with the first capacitor, and the fourth resistor is connected in series with the second capacitor; The third resistor is connected to the drain of the first NMOS transistor and the gate of the third NMOS transistor, respectively. The first capacitor is connected to the drain of the third NMOS transistor, the gate of the fifth NMOS transistor, the drain of the fourth PMOS transistor, and the gate of the sixth PMOS transistor, respectively. The fourth resistor is connected to the drain of the second NMOS transistor and the gate of the fourth NMOS transistor, respectively. The second capacitor is connected to the drain of the fourth NMOS transistor, the gate of the sixth NMOS transistor, the drain of the fifth PMOS transistor, and the gate of the seventh PMOS transistor, respectively.

5. The transimpedance amplifier based on a three-stage amplifier and a feedforward inverting amplifier according to claim 4, characterized in that, The common-mode detection feedback circuit includes a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a fifth resistor, a sixth resistor, a seventh resistor, and a third capacitor. The source of the ninth NMOS transistor is grounded, the gate is connected to the second bias voltage, and the drain is connected to the source of the tenth NMOS transistor and the source of the eleventh NMOS transistor, respectively. The drain of the tenth NMOS transistor is connected to the gate and drain of the tenth PMOS transistor, and the drain of the eleventh NMOS transistor is connected to the gate and drain of the eleventh PMOS transistor. The sources of both the tenth PMOS transistor and the eleventh PMOS transistor receive the power supply voltage. The gate of the tenth NMOS transistor is connected to the third resistor, the sixth resistor, and the seventh resistor, respectively; The gate of the eleventh NMOS transistor receives the reference voltage; The fifth resistor and the third capacitor are connected in series. The fifth resistor is connected to the gate and drain of the tenth PMOS transistor, respectively. The drain of the tenth PMOS transistor outputs the common-mode feedback voltage. The sixth resistor is connected to the drain of the seventh PMOS transistor and the sixth NMOS transistor, respectively; The seventh resistor is connected to the drain of the sixth PMOS transistor and the fifth NMOS transistor, respectively.

6. The transimpedance amplifier based on a three-stage amplifier and a feedforward inverting amplifier according to claim 1, characterized in that, The first resistor and the second resistor have the same resistance value.

7. The transimpedance amplifier based on a three-stage amplifier and a feedforward inverting amplifier according to claim 5, characterized in that, The value of the first bias voltage or the second bias voltage ranges from 10uA to 900uA.

8. The transimpedance amplifier based on a three-stage amplifier and a feedforward inverting amplifier according to claim 1, characterized in that, The open-loop gain of the transimpedance amplifier is 100dB.

9. The transimpedance amplifier based on a three-stage amplifier and a feedforward inverting amplifier according to claim 5, characterized in that, The reference voltage is half of the power supply voltage.

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