Driving circuit and display panel

Abstract

The present invention proposes a driving circuit and a display panel, wherein the driving circuit includes a signal output module, a clock signal compensation module and a gate driving module; the signal output module is connected to the input end of the clock signal compensation module, the output end of the clock signal compensation module is connected to the input end of the gate driving module, and the output end of the gate driving module is connected to a scanning line. The clock signal is compensated by setting a clock signal compensation module, and the compensation degree of the clock signal corresponding to the pixel row with a longer data signal transmission path is greater, that is, the gate voltage of the transistor corresponding to the pixel row with a longer data signal transmission path is greater, and the opening degree of the transistor is greater, thereby improving the charging condition of the pixel row, offsetting the influence of parasitic capacitance and line resistance, ensuring the consistency of charging of each pixel row, and avoiding the problem of uneven brightness.

Description

Technical Field

[0001] The present invention relates to the field of display, and in particular to a driving circuit and a display panel. Background Art

[0002] In a liquid crystal display, a scan signal is output to a transistor through a scan line. When the transistor is turned on, a data signal is output to the transistor through a data line, thereby charging the corresponding pixel. However, due to the parasitic capacitance between the data line and the scan line, and the line resistance of the data line itself, the charging condition of the pixel row farther away from the data signal transmission path is worse, resulting in uneven brightness display. Summary of the invention

[0003] The main purpose of the present invention is to provide a driving circuit and a display panel, aiming to solve the problem of uneven brightness display in the prior art.

[0004] To achieve the above object, the present invention provides a driving circuit, which includes a signal output module, a clock signal compensation module and a gate driving module; the signal output module is connected to the input end of the clock signal compensation module, the output end of the clock signal compensation module is connected to the input end of the gate driving module, and the output end of the gate driving module is connected to the scan line; wherein:

[0005] The signal output module is used to output the clock signal to the clock signal compensation module;

[0006] The clock signal compensation module is used to compensate the voltage value of the clock signal to obtain a compensated clock signal, and output the compensated clock signal to the gate driving module, wherein the compensation value of the clock signal corresponding to the gate driving module is positively correlated with the length of the data signal transmission path of the corresponding pixel row;

[0007] The gate driving module is used to output a scanning signal to the scanning line based on the compensation clock signal.

[0008] Optionally, the clock signal compensation module includes a superposition unit and a compensation signal unit; a first input end of the superposition unit is connected to a clock signal output end of the signal output module, a second input end of the superposition unit is connected to an output end of the compensation signal unit, and an output end of the superposition unit is connected to an input end of the gate driving module; wherein:

[0009] The compensation signal unit is used to output a compensation voltage to the superposition unit, wherein the compensation voltage corresponding to the gate driving module is positively correlated with the length of the data signal transmission path corresponding to the pixel row;

[0010] The superposition unit is used to superimpose the clock signal and the compensation voltage to obtain the compensated clock signal, and output the compensated clock signal to the gate driving module.

[0011] Optionally, the compensation signal unit includes a charging subunit and a load subunit; the input end of the charging subunit is connected to the maximum compensation voltage output end and the frame start pulse signal output end of the signal output module, the output end of the charging subunit is connected to the second input end of the superposition unit, and the load subunit is connected to the second input end of the superposition unit; wherein:

[0012] The signal output unit is used to output a maximum compensation voltage and a frame start pulse signal to the charging subunit;

[0013] The charging subunit is used to output the maximum compensation voltage to the second input terminal of the superposition unit when the frame start pulse signal is at a high level;

[0014] The load subunit is used to continuously reduce the voltage of the second input terminal of the superposition unit after the charging subunit stops outputting the maximum compensation voltage.

[0015] Optionally, the charging subunit includes a first switch tube; wherein:

[0016] The source of the first switch tube is connected to the maximum compensation voltage output end of the signal output module, the gate of the first switch tube is connected to the frame start pulse signal output end of the signal output module, and the drain of the first switch tube is respectively connected to the second input end of the superposition unit and the load sub-unit.

[0017] Optionally, the load subunit includes a first capacitor and a first resistor; wherein:

[0018] The first end of the first resistor is connected to the second input end of the superposition unit, the first end of the first resistor is also grounded through the first capacitor, and the second end of the first resistor is grounded.

[0019] Optionally, the time for the first capacitor to discharge from the maximum compensation voltage to a voltage of 0V is a frame scanning time of a display panel.

[0020] Optionally, the superposition unit includes a first operational amplifier, a second resistor, a third resistor, a fourth resistor and a fifth resistor; wherein:

[0021] The non-inverting input terminal of the first operational amplifier is connected to the clock signal output terminal of the signal output module through the second resistor, the non-inverting input terminal of the first operational amplifier is also connected to the output terminal of the compensation signal unit through the third resistor, the inverting input terminal of the first operational amplifier is grounded through the fourth resistor, the inverting input terminal of the first operational amplifier is also connected to the output terminal of the first operational amplifier through the fifth resistor, and the output terminal of the first operational amplifier is connected to the input terminal of the gate driving module.

[0022] Optionally, the second resistor has a resistance value equal to that of the third resistor, and the fourth resistor has a resistance value equal to that of the fifth resistor.

[0023] In addition, to achieve the above objective, the present invention further provides a display panel, which includes a pixel array, scan lines, and the driving circuit as described above.

[0024] Optionally, the display panel further includes a source driving module and a data line; wherein:

[0025] The input end of the source driving module is connected to the signal output module, the output end of the source driving module is connected to the data line, and the data line is connected to the pixel array.

[0026] The present invention proposes a driving circuit and a display panel, wherein the driving circuit comprises a signal output module, a clock signal compensation module and a gate driving module; the signal output module is connected to the input end of the clock signal compensation module, the output end of the clock signal compensation module is connected to the input end of the gate driving module, and the output end of the gate driving module is connected to a scan line; wherein: the signal output module is used to output a clock signal to the clock signal compensation module; the clock signal compensation module is used to compensate the voltage value of the clock signal to obtain a compensated clock signal, and output the compensated clock signal to the gate driving module, wherein the compensation value of the clock signal corresponding to the gate driving module is positively correlated with the length of the data signal transmission path of the corresponding pixel row; the gate driving module is used to output a scan signal to the scan line based on the compensated clock signal. The clock signal is compensated by setting up a clock signal compensation module, and the pixel row with a longer data signal transmission path has a greater degree of compensation for the corresponding clock signal, that is, the pixel row with a longer data signal transmission path has a greater gate voltage for the corresponding transistor, and the transistor is more open. This improves the charging condition of the pixel row, offsets the influence of parasitic capacitance and line resistance, ensures the consistency of charging of each pixel row, and avoids the problem of uneven brightness. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0028] Figure 1 A functional module diagram of an embodiment of a driving circuit of the present invention;

[0029] Figure 2 The driving circuit of the present invention is applied in Figure 2 Circuit structure diagram in the embodiment;

[0030] Figure 3 A waveform diagram of a compensation clock signal in a driving circuit of the present invention;

[0031] Figure 4 It is a waveform diagram of a frame start pulse signal and a compensation clock signal in a driving circuit of the present invention;

[0032] Figure 5 It is the voltage and current curve of the transistor;

[0033] Figure 6 It is a structural schematic diagram of a superposition unit in a driving circuit of the present invention;

[0034] Figure 7 It is a schematic structural diagram of the display panel of the present invention.

[0035] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings.

[0036] Description of Figure Numbers:

[0037] Label name Label name 100 Signal output module R1~R5 The first resistor to the fifth resistor 200 Clock signal compensation module C1 First capacitor 210 Superposition unit Q1 First Op Amp 220 Compensation signal unit 222 Load subunit 221 Charging subunit 300 Gate drive module DETAILED DESCRIPTION

[0038] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0041] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0042] The present invention provides a driving circuit, which is applied to a display panel. Figure 1 , Figure 1 This is a functional module diagram of an embodiment of a driving circuit of the present invention. In this embodiment, the driving circuit includes a signal output module 100, a clock signal compensation module 200 and a gate driving module 300; the signal output module 100 is connected to the input end of the clock signal compensation module 200, the output end of the clock signal compensation module 200 is connected to the input end of the gate driving module 300, and the output end of the gate driving module 300 is connected to the scan line GATE; wherein:

[0043] The signal output module 100 is used to output a clock signal to the clock signal compensation module 200;

[0044] The clock signal compensation module 200 is used to compensate the voltage value of the clock signal to obtain a compensated clock signal, and output the compensated clock signal to the gate driving module 300, wherein the compensation value of the clock signal corresponding to the gate driving module 300 is positively correlated with the length of the data signal transmission path of the corresponding pixel row;

[0045] The gate driving module 300 is used to output a scanning signal to the scanning line based on the compensation clock signal.

[0046] The signal output module 100 is a device that provides related signals in the display panel; it is understandable that the devices that output related signals vary based on the specific settings of the display panel. For example, the clock signal can be output by T-con or by an integrated driver IC. The same is true for other types of signals; in this embodiment and subsequent embodiments, T-con is used as an example for the signal output module 100 to output various types of signals.

[0047] The display panel includes a pixel array, and the pixel units in the pixel array are connected to the data lines and the scan lines respectively; the pixel row described in this embodiment indicates a set of pixel units connected to the same scan line, and the pixel column indicates a set of pixel units connected to the same data line.

[0048] The gate driving module 300 is used to output a scan signal to the scan line, so that the transistor of the pixel unit on the scan line is turned on, and then the pixel unit is charged based on the data signal on the data line.

[0049] It can be understood that the scanning signal output by the gate driving module 300 is obtained from the clock signal; generally, the transistor whose output end is connected to the scanning line in the gate driving module 300 is turned on when the gate is at a high level, and when the clock signal is at a high level, the clock signal is output to the scanning line through the transistor to realize the output of the scanning signal. Therefore, the size of the clock signal determines the size of the scanning signal; the specific structure of the gate driving module 300 can be set based on actual needs and is not limited here.

[0050] The data signal is transmitted to each pixel column through the data line. There is parasitic capacitance between the data line and the scan line, and the data line itself has line resistance. Therefore, the longer the transmission path of the data signal, the greater the delay loading of the charging response of the corresponding pixel unit, the worse the charging condition of the pixel unit, and the smaller the corresponding brightness displayed; the transmission path of the data signal refers to the length of the data line connected between the pixel unit and the data driving module. It can be understood that the transmission paths corresponding to the pixel units of the same pixel row are the same. Therefore, it can also indicate the length of the data line connected between the pixel row and the data driving module.

[0051] In order to ensure the uniformity of the picture brightness, it is necessary to make greater compensation for pixel rows with longer transmission paths, and smaller compensation for pixel rows with shorter transmission paths, so that the charging conditions of the pixel units in each pixel row after compensation are consistent, achieving uniform picture brightness.

[0052] It can be seen from the display panel structure that the driving circuit includes multiple gate driving modules 300, each gate driving module 300 is connected to a scanning line, that is, corresponds to a pixel row. Therefore, for the compensation value of the clock signal of the gate driving module 300, the smaller the transmission path corresponding to the pixel row, the smaller the compensation value, and the larger the transmission path corresponding to the pixel row, the larger the compensation value, so that the voltage value V0 of the obtained compensation scanning signal is larger, that is, the compensation value of the clock signal corresponding to the gate driving module 300 is positively correlated with the length of the data signal transmission path corresponding to the pixel row.

[0053] It can be understood that the clock signal is output as a scanning signal and acts on the gate of the transistor in the pixel unit. The larger the scanning signal, the greater the degree of transistor opening and the greater the charging efficiency. When the data signal is determined, although the pixel unit with a larger transmission path has a larger loading, its scanning signal increases under the influence of the compensation value, thereby improving the charging efficiency. The pixel unit with a smaller transmission path has a smaller loading, but its scanning signal decreases under the influence of the compensation value, thereby reducing the charging efficiency. The charging is balanced by affecting the charging efficiency through the compensation value, so that the final charging conditions of each pixel unit are consistent, achieving uniform brightness.

[0054] In this embodiment, a clock signal compensation module 200 is provided to compensate for the clock signal, and a pixel row having a longer data signal transmission path has a greater degree of compensation for the corresponding clock signal, that is, a pixel row having a longer data signal transmission path has a greater gate voltage for the corresponding transistor, and a greater degree of transistor opening, thereby improving the charging condition of the pixel row, offsetting the influence of parasitic capacitance and line resistance, ensuring the consistency of charging of each pixel row, and avoiding the problem of uneven brightness.

[0055] Further, see Figure 2 , the clock signal compensation module 200 includes a superposition unit 210 and a compensation signal unit 220; the first input end of the superposition unit 210 is connected to the clock signal output end of the signal output module 100, the second input end of the superposition unit 210 is connected to the output end of the compensation signal unit 220, and the output end of the superposition unit 210 is connected to the input end of the gate driving module 300; wherein:

[0056] The compensation signal unit 220 is used to output a compensation voltage to the superposition unit 210, wherein the compensation voltage corresponding to the gate driving module 300 is positively correlated with the length of the data signal transmission path of the corresponding pixel row;

[0057] The superposition unit 210 is used for superimposing the clock signal and the compensation voltage to obtain the compensated clock signal, and outputting the compensated clock signal to the gate driving module 300 .

[0058] In this embodiment, compensation for the clock signal is achieved by superposition. Different compensation voltages are superimposed on the original output clock signal, so as to adjust the clock signal corresponding to the gate drive module 300 of different pixel rows; it can be understood that in order to avoid affecting the display effect, the uncompensated clock signal is taken as the minimum value of the clock signal, that is, the compensation voltage is a positive value, the larger the compensation voltage is, the larger the voltage value of the compensated clock signal obtained after superimposing it on the clock signal is, and the minimum compensation voltage is 0V.

[0059] It should be noted that, when only brightness uniformity is considered, in addition to positive compensation for pixel rows with larger transmission paths, negative compensation can also be performed on pixel rows with smaller transmission paths, such as reducing the voltage value of the clock signal corresponding to the pixel rows with smaller transmission paths; however, this method has the problem of affecting the picture display, and therefore, the positive compensation method is adopted in this embodiment.

[0060] Further, the compensation signal unit 220 includes a charging subunit 221 and a load subunit 222; the input end of the charging subunit 221 is connected to the maximum compensation voltage output end and the frame start pulse signal output end of the signal output module 100, the output end of the charging subunit 221 is connected to the second input end of the superposition unit 210, and the load subunit 222 is connected to the second input end of the superposition unit 210; wherein:

[0061] The signal output unit is used to output the maximum compensation voltage and the frame start pulse signal to the charging subunit 221;

[0062] The charging subunit 221 is used to output the maximum compensation voltage to the second input terminal of the superposition unit 210 when the frame start pulse signal is at a high level;

[0063] The load subunit 222 is used to continuously reduce the voltage of the second input terminal of the superposition unit 210 after the charging subunit 221 stops outputting the maximum compensation voltage.

[0064] It can be understood that in actual applications, the clock signal is output from T-con to each gate driving module 300, and the clock signal received by each gate driving module 300 is the same at the same time. The gate driving module 300 outputs a scanning signal based on the current clock signal in different scanning periods. Therefore, the clock signal can be continuously compensated for a period of time to achieve the clock signal compensation requirements of each gate driving module 300; generally, see Figure 3 , scanning usually starts from the first row in the pixel array and goes downwards, and the transmission path corresponding to the pixel unit in the first row is the largest, so its corresponding compensation value is also the largest. As the number of scan rows decreases, the corresponding compensation value decreases until the last row, when the compensation value is the smallest; that is, the scanning signal voltage corresponding to the first row is the largest, and the downward scanning signal voltage decreases row by row until the scanning signal voltage corresponding to the last row is the smallest.

[0065] The frame start pulse signal STV is used to indicate the start of a frame; that is, after STV is triggered at a high level, the pixel rows are scanned row by row starting from the first row.

[0066] Therefore, in this embodiment, see Figure 4 When the STV high level is triggered, the charging subunit 221 outputs the maximum compensation voltage to the second input terminal of the superposition unit 210, so that the compensation value corresponding to the first row in the pixel array is the maximum compensation voltage. When the STV high level ends, the charging subunit 221 stops outputting the maximum compensation voltage. At the same time, under the influence of the load subunit 222, the voltage at the second input terminal of the superposition unit 210 gradually decreases over time from the maximum compensation voltage. Therefore, the compensation voltage of each pixel row is gradually reduced relative to the previous row, until the last pixel row is scanned, and the voltage at the second input terminal of the superposition unit 210 reaches the lowest.

[0067] Furthermore, the charging subunit 221 includes a first switch tube; wherein:

[0068] The source of the first switch tube is connected to the maximum compensation voltage output end of the signal output module 100, the gate of the first switch tube is connected to the frame start pulse signal output end of the signal output module 100, and the drain of the first switch tube is respectively connected to the second input end of the superposition unit 210 and the load sub-unit 222.

[0069] In this embodiment, the first switch tube is a TFT (Thin Film Transistor); when STV is at a high level, the first switch tube is turned on, and at this time, the maximum compensation voltage output by the signal output module 100 is transmitted to the second input terminal of the superposition unit 210 through the first switch tube; when STV is at a low level, the first switch tube is turned off and stops outputting the maximum compensation voltage.

[0070] Furthermore, the load subunit 222 includes a first capacitor C1 and a first resistor R1; wherein:

[0071] The first end of the first resistor R1 is connected to the second input end of the superimposing unit 210 , the first end of the first resistor R1 is also grounded through the first capacitor C1 , and the second end of the first resistor R1 is grounded.

[0072] When the charging subunit 221 outputs the maximum compensation voltage, the first capacitor C1 is charged with the maximum compensation voltage, and the voltage of the first capacitor C1 reaches the maximum compensation voltage during the time when STV is at a high level; after the charging subunit 221 stops outputting the maximum compensation voltage, the voltage of the first capacitor C1 is discharged to the ground through the first resistor R1, and as the first capacitor C1 is discharged, the voltage of the first capacitor C1 gradually decreases, that is, the voltage of the second input terminal of the superposition unit 210 gradually decreases; the compensation voltage corresponding to the pixel row decreases row by row.

[0073] Furthermore, the time for the first capacitor C1 to discharge from the maximum compensation voltage to 0V is one frame scanning time of the display panel.

[0074] When the voltage of the first capacitor C1 is 0V, the voltage of the second input terminal of the superposition unit 210 is 0V, that is, the corresponding compensation voltage is 0V at this time; since the parasitic capacitance and line resistance of the pixel row with the smallest transmission path are less affected, they do not need to be compensated and the original clock signal can be used.

[0075] In other embodiments, when the pixel row with the smallest transmission path is scanned, the voltage of the first capacitor C1 may also be greater than 0, so as to compensate the pixel row and ensure the display effect.

[0076] It can be understood that the discharge speed of the first capacitor C1 is related to the resistance value of the first resistor R1; the larger the resistance value of the first resistor R1, the slower the discharge speed, and the smaller the resistance value of the first resistor R1, the faster the discharge speed; therefore, in practical applications, the compensation voltage required for the first row of pixels can be determined based on experiments, thereby determining the maximum compensation voltage, and when determining the scanning time required for a frame, the resistance value of the first resistor R1 needs to make the first capacitor C1 start to discharge from STV to a low level, gradually decrease, and reach 0V when the last row of pixels is scanned.

[0077] It should be noted that in the display panel, the ground line is usually used to output the VGL signal. After adding the first capacitor C1 and the first resistor R1 in this embodiment, the ground line potential may rise, thereby affecting the turn-off current I off ; and since the compensation voltage itself is small, see Figure 5It can be seen from the IV characteristic curve diagram of TFT that the slope of the curve is low in the low voltage section, so a slight increase in VGL will not have a significant impact on the Ioff of the gate TFT. Therefore, the load subunit 222 in this embodiment will not affect the normal use of the TFT.

[0078] Further, see Figure 6 , the superposition unit 210 includes a first operational amplifier Q1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5; wherein:

[0079] The non-inverting input terminal of the first operational amplifier Q1 is connected to the clock signal output terminal of the signal output module 100 through the second resistor R2, the non-inverting input terminal of the first operational amplifier Q1 is also connected to the output terminal of the compensation signal unit 220 through the third resistor R3, the inverting input terminal of the first operational amplifier Q1 is grounded through the fourth resistor R4, the inverting input terminal of the first operational amplifier Q1 is also connected to the output terminal of the first operational amplifier Q1 through the fifth resistor R5, and the output terminal of the first operational amplifier Q1 is connected to the input terminal of the gate driving module 300.

[0080] The superposition unit 210 in this embodiment is configured as an adder circuit; the clock signal output by the signal output module 100 is input to the non-inverting input terminal of the first operational amplifier Q1 through the second resistor R2, and the compensation voltage output by the compensation signal unit 220 is input to the non-inverting input terminal of the first operational amplifier Q1 through the third resistor R3; according to the principle of the adder circuit, when the resistance values ​​of the second resistor R2 and the third resistor R3 are equal, the voltage value V0 of the compensation clock signal output by the first operational amplifier Q1 is:

[0081]

[0082] Among them, V i1 is the voltage of the clock signal, V i2 is the compensation voltage.

[0083] When the second resistor R2 has the same resistance as the third resistor R3, and the fourth resistor R4 has the same resistance as the fifth resistor R5, the voltage value V0 of the compensation clock signal output by the first operational amplifier Q1 is:

[0084] V0=V i1 +V i2

[0085] The superposition of the clock signal and the compensation voltage is realized.

[0086] Combine the following Figure 2 and Figure 4 The overall principle of the driving circuit of the present invention is described as follows:

[0087] When STV triggers a high level, the first switch tube is turned on, and the maximum compensation voltage is output to the second input terminal of the superposition unit 210. The first input terminal of the superposition unit 210 receives the clock signal, and outputs the compensation clock signal obtained by adding the clock signal to the maximum compensation voltage. At this time, the first pixel row starts to scan, and the scanning signal is output based on the current compensation clock signal; at the same time, the first capacitor C1 is charged by the maximum compensation voltage;

[0088] After STV is converted to a low level, the first switch tube is turned off, stops outputting the compensation voltage, the first capacitor C1 starts to discharge through the first resistor R1, the voltage at the second input end of the superposition unit 210 gradually decreases, and the pixel rows are scanned row by row based on the gradually decreasing compensation clock signal;

[0089] The first capacitor C1 is discharged, and the voltage at the second input terminal of the superposition unit 210 is 0. At this time, the last row of pixels is scanned based on the clock signal, completing a frame scanning operation.

[0090] The present invention also protects a display panel, see Figure 7 The display panel includes a pixel array, a scanning line GATE and a driving circuit. The structure of the driving circuit can refer to the above embodiment and will not be described here. As a matter of course, since the display panel of this embodiment adopts the technical solution of the above driving circuit, the display panel has all the beneficial effects of the above driving circuit.

[0091] Furthermore, the display panel further includes a source driving module and a data line DATA; wherein:

[0092] The input end of the source driving module is connected to the signal output module 100 , the output end of the source driving module is connected to the data line, and the data line is connected to the pixel array.

[0093] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "includes a..." does not exclude the presence of other identical elements in the process, method, article or system including the element. The serial numbers of the above-mentioned embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments.

[0094] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A driving circuit, characterized in that: The driving circuit includes a signal output module, a clock signal compensation module and a gate driving module; the signal output module is connected to the input end of the clock signal compensation module, the output end of the clock signal compensation module is connected to the input end of the gate driving module, and the output end of the gate driving module is connected to the scan line; wherein: The signal output module is used to output the clock signal to the clock signal compensation module; The clock signal compensation module is used to compensate the voltage value of the clock signal to obtain a compensated clock signal, and output the compensated clock signal to the gate driving module, wherein the compensation value of the clock signal corresponding to the gate driving module is positively correlated with the length of the data signal transmission path of the corresponding pixel row; The gate driving module is used to output a scanning signal to the scanning line based on the compensation clock signal; The clock signal compensation module includes a superposition unit and a compensation signal unit; the first input end of the superposition unit is connected to the clock signal output end of the signal output module, the second input end of the superposition unit is connected to the output end of the compensation signal unit, and the output end of the superposition unit is connected to the input end of the gate driving module; wherein: The compensation signal unit is used to output a compensation voltage to the superposition unit, wherein the compensation voltage corresponding to the gate driving module is positively correlated with the length of the data signal transmission path corresponding to the pixel row; The superposition unit is used for superimposing the clock signal and the compensation voltage to obtain the compensated clock signal, and outputting the compensated clock signal to the gate driving module; The compensation signal unit includes a charging subunit and a load subunit; the input end of the charging subunit is connected to the maximum compensation voltage output end and the frame start pulse signal output end of the signal output module, the output end of the charging subunit is connected to the second input end of the superposition unit, and the load subunit is connected to the second input end of the superposition unit; wherein: The signal output unit is used to output a maximum compensation voltage and a frame start pulse signal to the charging subunit; The charging subunit is used to output the maximum compensation voltage to the second input terminal of the superposition unit when the frame start pulse signal is at a high level; The load subunit is used to continuously reduce the voltage of the second input terminal of the superposition unit after the charging subunit stops outputting the maximum compensation voltage.

2. The driving circuit according to claim 1, characterized in that: The charging subunit includes a first switch tube; wherein: The source of the first switch tube is connected to the maximum compensation voltage output end of the signal output module, the gate of the first switch tube is connected to the frame start pulse signal output end of the signal output module, and the drain of the first switch tube is respectively connected to the second input end of the superposition unit and the load sub-unit.

3. The driving circuit according to claim 1, wherein: The load subunit includes a first capacitor and a first resistor; wherein: The first end of the first resistor is connected to the second input end of the superposition unit, the first end of the first resistor is also grounded through the first capacitor, and the second end of the first resistor is grounded.

4. The driving circuit according to claim 3, characterized in that: The time for the first capacitor to discharge from the maximum compensation voltage to 0V is one frame scanning time of the display panel.

5. The driving circuit according to claim 1, characterized in that: The superposition unit includes a first operational amplifier, a second resistor, a third resistor, a fourth resistor and a fifth resistor; wherein: The non-inverting input terminal of the first operational amplifier is connected to the clock signal output terminal of the signal output module through the second resistor, the non-inverting input terminal of the first operational amplifier is also connected to the output terminal of the compensation signal unit through the third resistor, the inverting input terminal of the first operational amplifier is grounded through the fourth resistor, the inverting input terminal of the first operational amplifier is also connected to the output terminal of the first operational amplifier through the fifth resistor, and the output terminal of the first operational amplifier is connected to the input terminal of the gate driving module.

6. The driving circuit according to claim 5, characterized in that: The second resistor has the same resistance as the third resistor, and the fourth resistor has the same resistance as the fifth resistor.

7. A display panel, characterized in that: The display panel comprises a pixel array, scan lines and a driving circuit as claimed in any one of claims 1 to 6.

8. The display panel according to claim 7, wherein: The display panel also includes a source driving module and a data line; wherein: The input end of the source driving module is connected to the signal output module, the output end of the source driving module is connected to the data line, and the data line is connected to the pixel array.

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