Gold-Silver Alloy Bumps Substituting for Pure Gold Bump Encapsulated Flip Chips and Preparation Method Thereof

Abstract

The present invention discloses a gold-silver alloy bump for replacing a pure gold bump in flip-chip packaging and a preparation method thereof, belonging to the technical field of electroplating gold-silver alloys. The gold-silver alloy bump is composed of two layers of gold-silver alloy layers, namely a connection layer and a protective layer; the content of gold in the connection layer is 20-50 wt%; the thickness of the protective layer is much smaller than that of the connection layer, and the content of gold is above 60 wt%; the average grain size of the grains in the gold-silver alloy layer is 0.10-0.30 μm. The gold-silver alloy bump provided by the present invention has hardness, roughness and anti-sulfuration performance comparable to those of a pure gold bump, can meet the technical requirements of flip-chip packaging, and can greatly reduce costs at the same time. The method for the gold-silver alloy bump provided by the present invention can obtain the double-layer gold-silver alloy bump of the present invention by only changing the current density through the same equipment and plating solution, simplifies the preparation process, improves the production efficiency, and reduces the production cost.

Description

[0001] Divisional Application

[0002] This invention is a divisional application of a Chinese patent application for invention with the application date of January 10, 2024, application number 202410033246.2, and title "A Gold-Silver Alloy Bump and Its Preparation Method and Application". Technical Field

[0003] This invention belongs to the technical field of electroplating gold-silver alloys, and relates to a gold-silver alloy bump for replacing pure gold bumps in flip-chip packaging and its preparation method. Background Art

[0004] Flip-chip packaging technology interconnects components directly downward to a substrate, carrier, or circuit board through bumps on the chip. Flip chips avoid redundant packaging processes and have advantages such as reduced size, high-frequency operation, low parasitic effects, and high I / O density. Flip-chip packaging technology is applicable to various chips such as liquid crystal displays, image sensors, memories, microprocessors, and microwave radio frequencies, and specific application products include mobile phones, TVs, computers, tablets, and cameras, etc.

[0005] For the bumps used in flip chips, to ensure chip performance, based on the excellent properties of gold, pure gold is usually used for preparation. Silver, as another precious metal, also has good electrical conductivity and thermal conductivity, and its price is much lower than that of gold; however, when using pure silver to prepare bumps, problems such as silver needles, silver migration, and easy oxidation and sulfidation occur, which cannot meet the chip performance requirements. If silver can partially replace gold, the cost of gold bumps can be greatly reduced; and gold-silver alloy bumps have lower resistance and higher thermal conductivity compared to pure gold bumps, which helps to improve the heat dissipation performance of the chip and increase the electrical interconnection density. However, when using electroplating technology to prepare gold-silver alloy bumps to replace gold bumps, the following technical problems need to be solved.

[0006] First, the hardness of the gold-silver alloy bumps after annealing should match the annealing hardness of the pure gold bumps. In Chip-on-Film (COF) packaging, since the bumps need to be directly pressed through the solder layer and the copper circuit on the polyimide film, the hardness of the bumps cannot be too high. Generally, the hardness after annealing is required to be 45 - 75 HV. Otherwise, the bumps may cause the rupture of the conductive circuit. In Chip-on-Glass (COG) packaging, the bumps are connected to the copper circuit on the glass substrate through the anisotropic conductive film, and the bumps should have sufficient hardness to promote the pressing of the anisotropic conductive film. Generally, the hardness of the bumps is required to be between 75 - 105 HV. Secondly, compared with gold, the surface of silver is easily sulfided in the air. Once sulfide is formed, the connectivity with the solder or the anisotropic conductive film is not very good, which may affect the electrical connection between silver and the copper circuit. Therefore, it is necessary to solve the anti-sulfidation performance of the gold-silver alloy bumps. Finally, the surface roughness of the bumps after electroplating cannot be too high. Generally, the roughness Ra is required to be less than 100 nm. Otherwise, it may affect the electrical interconnection with the copper circuit.

[0007] The invention patent with the publication number CN104099653B discloses a semiconductor structure and its manufacturing method, and specifically discloses an electroplated silver alloy electroplating solution for preparing silver alloy bumps. The electroplating solution contains potassium silver cyanide, and / or potassium gold cyanide and potassium palladium cyanide. The pH of the electroplating solution is controlled in the range of 6 to 8, and the plating solution also contains a small amount of oxalate. As is well known, silver ions are photosensitive substances. If a stabilizer for silver ions is not added, silver metal will precipitate quickly from the electroplating solution, that is, the electroplating solution is unstable.

[0008] The invention patent also discloses three structures using silver alloy bumps to replace pure gold bumps. The first one is to directly use the silver alloy bump body to replace the gold bump. Since there is no antioxidant or anti-sulfidation protection on the silver alloy or part of the surface, reliability problems may occur due to the oxidation or sulfidation of silver in the follow-up. Especially, this patent emphasizes that the silver alloy bump is mainly composed of silver, and the atomic ratio of gold should be controlled below 25%. The second one is a laminated structure. First, the silver alloy bump body is prepared, and then a gold bump structure with a certain thickness is prepared on the top surface of the silver alloy bump. The metal for preparing the top surface, such as pure gold, requires a second electroplating solution and its device, increasing the process complexity and equipment cost. The third one is a surrounding structure. First, the silver alloy bump is prepared, and then a metal surrounding layer is formed on the top surface and the side surface of the silver alloy bump by electroplating or electroless plating. Compared with pure gold, the silver alloy is easy to oxidize or sulfide. Therefore, the first or second structure is used. For the third structure, although the problem of silver alloy oxidation or sulfidation is solved by the gold surrounding structure, this process requires two photoresist exposure and development operations, and at the same time requires two different electroplating solutions, increasing the process complexity and cost.

[0009] The invention patent with the publication number CN101225536B discloses a gold-silver alloy electroplating solution. The electroplating solution consists of potassium gold cyanide with a gold content of 1-30 g / L, potassium silver cyanide with a silver content of 1-200 ppm, potassium pyrophosphate of 30-100 g / L, boric acid of 20-50 g / L, and 0.05-150 g / L of ethylenediamine, ethylenediaminetetraacetic acid, diethylenetriamine, triethylenetetramine, tetraethylenepentamine or pentaethylenehexamine. The electroplated gold-silver alloy contains 0.3-2.0 wt% of silver, and the hardness of the gold-silver alloy is 150-200 HV. This patent is mainly for connector applications and is not suitable for preparing flip-chip bumps.

[0010] The invention patent with the publication number CH412508 discloses an electroplating solution for preparing gold-silver alloy. In addition to potassium gold cyanide and potassium silver cyanide, the electroplating solution contains 60 g / L of potassium cyanide. A large amount of free cyanide may cause plating penetration or swelling of the photoresist, damaging the structure of the bumps. At the same time, the presence of a large amount of free cyanide is also not conducive to environmental protection. Summary of the Invention

[0011] The primary objective of the present invention is to provide a gold-silver alloy bump to replace the pure gold bump for flip-chip packaging. Through painstaking research, the inventors designed the structure of the gold-silver alloy bump, optimized the gold-silver ratio, and regulated the grain size in the gold-silver alloy, enabling the obtained gold-silver alloy bump to retain the excellent electrical and thermal conductivity of the gold-silver alloy while meeting the technical requirements of flip-chip packaging in terms of hardness, anti-sulfuration, surface roughness, etc., thus replacing the pure gold bump and significantly reducing the bump cost. This objective is achieved through the following specific technical solutions.

[0012] The gold-silver alloy bump for replacing the pure gold bump in flip-chip packaging is characterized in that the gold-silver alloy bump consists of two gold-silver alloy layers, namely a connection layer and a protective layer; the gold content of the connection layer is 20-50 wt%; the gold content of the protective layer is above 60 wt%; the average grain diameter of the grains in the gold-silver alloy layer is 0.10-0.30 μm. The overall shape and size of the gold-silver alloy bump are the same as those of the existing pure gold bump used for flip-chip packaging. To measure the grain size in the gold-silver alloy layer, the EBSD (Electron Back Scattered Diffraction) method can be used, or other feasible methods can also be adopted.

[0013] The inventor discovered through extensive exploration that the annealing hardness and roughness of the gold-silver alloy bumps are closely related to the gold content and grain size in the gold-silver alloy. When the gold content is 20-50 wt% and the average grain diameter is 0.10-0.30 μm, the annealing hardness of the gold-silver alloy bumps is between 45-105 HV, and the coating roughness Ra is less than 100 nm, which can meet the requirements for the hardness and roughness of the bumps in flip-chip packaging. For the anti-sulfuration performance of the gold-silver alloy bumps, the gold content in the gold-silver alloy needs to be above 60 wt% to meet the requirements of flip-chip packaging. Therefore, the inventor created the above gold-silver alloy bumps composed of two layers of gold-silver alloy. The connecting layer is connected to the substrate, carrier or circuit board. Its specific gold content and grain size make the hardness and roughness of the bumps meet the requirements; the protective layer increases the gold content to above 60 wt%, making the overall anti-sulfuration performance of the bumps meet the requirements. At the same time, the thickness of the protective layer is much smaller than that of the connecting layer, and has almost no impact on the overall hardness and roughness.

[0014] Further, the gold content in the gold-silver alloy of the connecting layer is 20-40 wt%, so that its hardness is 45-75 HV, meeting the requirements of COF packaging.

[0015] Further, the gold content in the gold-silver alloy of the connecting layer is 30-50 wt%, so that its hardness is 75-105 HV, meeting the requirements of COG packaging.

[0016] Further, the thickness of the connecting layer is 7-20 μm, and the thickness of the protective layer is 10-500 nm.

[0017] Another object of the present invention is to provide a method for preparing the above gold-silver alloy bumps. By optimizing the composition of the electroplating solution, different gold contents can be obtained by only changing the current density through the same electroplating solution. Thus, the double-layer gold-silver alloy bumps of the present invention can be obtained in the same equipment without changing the plating solution, simplifying the preparation process, improving production efficiency, and reducing production costs. This object is achieved by the following specific technical solutions.

[0018] The method for preparing the above gold-silver alloy bumps is characterized by including the following steps:

[0019] S1 Pretreat the chip to be packaged and prepare the electroplating solution. The electroplating solution includes the following components: potassium gold cyanide (molecular formula KAu(CN)2), potassium silver cyanide (molecular formula KAg(CN)2), potassium pyrophosphate and hydantoin, and the pH value is 8-10;

[0020] S2 Place the chip to be packaged in the electroplating solution of step S1 and electroplate with a low current density to prepare the connecting layer of the gold-silver alloy bumps.

[0021] S3 uses the same electroplating solution and equipment, and electroplates at a high current density to prepare a protective layer for the gold-silver alloy bumps;

[0022] S4 removes the auxiliary materials of the chip to be encapsulated;

[0023] S5 anneals the gold-silver alloy bumps.

[0024] Further, the low current density in step S2 is 0.3 - 0.6 A / dm 2 (ASD), and the electroplating time is 30 - 60 min.

[0025] Further, the high current density in step S3 is 1.1 - 1.3 ASD, and the electroplating time is 20 - 40 s.

[0026] Further, removing the auxiliary materials of the chip to be encapsulated in step S4 includes using a degluing solution to remove the photoresist of the chip to be encapsulated, using an etching solution to remove the gold seed layer on the silicon substrate of the chip to be encapsulated, and removing the titanium-tungsten layer on the silicon substrate of the chip to be encapsulated; the degluing solution is N-methylpyrrolidone, the etching solution is a thiourea solution, and the substance for removing the titanium-tungsten layer is an H2O2 solution. Compared with the commonly used iodine / potassium iodide etching solution, the thiourea solution will not etch the gold-silver alloy bumps while removing the gold seed layer.

[0027] Further, the annealing temperature in step S5 is 270 - 300 °C, and the annealing time is 5 - 60 min.

[0028] The present invention has the following beneficial technical effects: The gold-silver alloy bumps provided by the present invention have hardness, roughness and anti-sulfuration performance equivalent to those of pure gold bumps, can meet the technical requirements of flip-chip packaging, and can significantly reduce costs at the same time. The method for preparing the gold-silver alloy bumps provided by the present invention can obtain the double-layer structure gold-silver alloy bumps of the present invention by using the same equipment and plating solution and only changing the circuit density, simplifies the preparation process, improves production efficiency, and reduces production costs. Description of the Drawings

[0029] Figure 1 is a graph showing the relationship between the gold content and the annealing hardness in the gold-silver alloy.

[0030] Figure 2 is a graph showing the relationship between the gold content and the coating roughness in the gold-silver alloy.

[0031] Figure 3 and Figure 4 is a photo showing the pre-compatibility of the electroplating solution and the photoresist.

[0032] Figure 5 and Figure 6 is a scanning electron microscope photo of the gold-silver alloy bumps after removing the photoresist.

[0033] Figure 7 It is a diagram showing the analysis results of the EDSB crystal structure of Example 1 and Example 2.

[0034] Figure 8 It is a diagram showing the anti-sulfuration performance of gold-silver alloys with different gold contents.

[0035] Figure 9 It is a schematic flow diagram of the method for preparing gold-silver alloy bumps of the present invention. Detailed implementation manners

[0036] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the specification. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0037] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance, quantity or position.

[0038] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0039] The inventors systematically studied the relationship between the gold content and the annealing hardness of gold-silver alloys. As Figure 1 shown, it can be seen that when the gold content in the gold-silver alloy is 20-50 wt%, the annealing hardness is in the range of 45-105 HV, meeting the requirements for the bump hardness in flip-chip packaging.

[0040] The inventors systematically studied the relationship between the gold content and the roughness of gold-silver alloys. As Figure 2As shown, it can be seen that when the gold content in the gold-silver alloy is 20 - 50 wt%, the roughness is below 100 nm, meeting the requirements for roughness in flip-chip packaging.

[0041] As Figure 1 and Figure 2 shown, not all ratios of gold-silver alloy can meet the requirements for hardness and roughness in flip-chip packaging. When the gold weight content is above 50%, the hardness of the annealed gold-silver alloy may exceed 105 HV; at the same time, when the gold weight content is below 20% or above 50%, the surface roughness Ra of the coating is higher than 100 nm. Therefore, the gold weight content in the compliant gold-silver alloy bumps should be between 20% - 50%. In Figure 1 , the operating ranges of gold-silver alloys with low hardness (45 - 75 HV) and high hardness (75 - 105 HV) are further divided, which are used for the packaging of COF and COG respectively. It can be seen that the gold weight content for electroplating compliant low-hardness gold-silver alloys should be operated between 20% - 40%, and the gold weight content for electroplating compliant high-hardness gold-silver alloys should be operated between 30% - 50%. Since the annealing hardness is affected by the annealing temperature and annealing time, for gold-silver alloy bumps with a gold content between 30% - 40%, the annealing hardness can be adjusted through annealing conditions to meet the packaging requirements of COF or COG.

[0042] The process of the method for preparing gold-silver alloy bumps of the present invention is as Figure 9 shown. The structure of the chip to be packaged includes a silicon substrate transistor layer 101, an aluminum electrode 102, a passivation layer 103, a TiW adhesion layer 104, a gold seed layer 105, and a photoresist 106. The chip to be packaged is placed in the electroplating solution for the first low-current density and long-time electroplating to obtain a connecting layer gold-silver alloy layer 107, and then the second high-current density and short-time electroplating is carried out to obtain a protective layer gold-silver alloy layer 108. The composition and concentration of the electroplating solution: potassium gold cyanide 6 - 10 g / L, potassium silver cyanide 4 - 7 g / L, potassium pyrophosphate 50 - 70 g / L, hydantoin 20 - 40 g / L, pH value 8 - 10. The thickness of the connecting layer gold-silver alloy layer 107 is 7 - 20 μm, and the gold content is 20 - 50 wt%; the thickness of the protective layer gold-silver alloy layer 108 is 10 - 500 nm, and the gold content is above 60 wt%. The average equivalent circle diameter of the grains is detected by the EBSD method to be 0.10 - 0.30 μm. After electroplating, the photoresist 106 on the chip to be packaged is removed using the de-gumming solution NMP, the gold seed layer 105 on the silicon substrate of the chip to be packaged is removed using the etching solution, and the TiW layer 104 on the silicon substrate of the chip to be packaged is removed using the H2O2 solution. Finally, the gold-silver alloy bumps are annealed, the annealing temperature is 270 - 300 °C, and the annealing time is 5 - 60 min.

[0043] Example 1

[0044] To prepare a low-hardness gold-silver alloy bump, the following steps are included.

[0045] S1 Pretreat the chip to be encapsulated, and prepare an electroplating solution, including the following components: potassium aurocyanide 6 g / L, potassium silver cyanide 7 g / L, potassium pyrophosphate 60 g / L, hydantoin 30 g / L, pH value 9, temperature 30 °C.

[0046] S2 Place the chip to be encapsulated in the electroplating solution of step S1, and perform electroplating with a low current density to prepare a gold-silver alloy connection layer of the gold-silver alloy bump. The current density is 0.4 ASD, electroplating for 45 minutes, the electroplating height is 10 μm, the gold content is 30 wt%, and the roughness Ra is 65 nm.

[0047] S3 Use the same electroplating solution and equipment, and perform electroplating with a high current density to prepare a gold-silver alloy protective layer of the gold-silver alloy bump. The current density is 1.2 ASD, the electroplating time is 30 seconds, the thickness of gold and silver in this layer is about 200 nm, the gold content is 67 wt%, and the overall roughness of the gold-silver alloy bump is 74 nm.

[0048] S4 Use a stripping solution to remove the photoresist on the chip to be encapsulated;

[0049] S5 Use an etching solution to remove the gold seed layer on the silicon substrate of the chip to be encapsulated;

[0050] S6 Remove the TiW layer on the silicon substrate of the chip to be encapsulated;

[0051] S7 Anneal the gold-silver alloy bump, the annealing temperature is 290 °C, the annealing time is 30 min, and the hardness of the gold-silver alloy bump after annealing is 65 HV.

[0052] The pH of the gold bump electroplating solution for pure gold generally operates between 5-7, while the gold-silver alloy electroplating solution used in the present invention operates between 8-10. When the pH is high, the photoresist may cause swelling of the photoresist or reduce the adhesion between the photoresist and the substrate, resulting in plating through, thus affecting the manufacturing accuracy of the circuit. As Figure 3 (magnification is 200) and Figure 4 (magnification is 500) show, the width of the gold-silver alloy bump is 20 μm, the width of the photoresist (JSRTHB-126N) between the bumps is 8 μm, the electroplating height is 10 μm, and no plating through or swelling of the photoresist is observed when using the gold-silver electroplating solution of the present invention. Figure 5 and Figure 6 Show the gold-silver alloy bump prepared by using the present invention. After removing the photoresist with NMP, the surface of the gold-silver alloy bump is flat, the crystallization is uniform, and no occurrence of coarse crystallization causes local roughness to be too high.

[0053] Example 2

[0054] To prepare a gold-silver alloy bump with high hardness, the following steps are included.

[0055] S1 Pretreat the chip to be encapsulated and prepare an electroplating solution, which includes the following components: potassium aurocyanide 10 g / L, potassium silver cyanide 4 g / L, potassium pyrophosphate 60 g / L, hydantoin 30 g / L, pH value 9, and temperature 30 °C.

[0056] S2 Place the chip to be encapsulated in the electroplating solution of step S1 and perform electroplating with a low current density to prepare a connection layer of the gold-silver alloy bump. The current density is 0.5 ASD, the electroplating time is 36 minutes, the electroplating height is 10 μm, the gold content is 42 wt%, and the roughness Ra is 71 nm.

[0057] S3 Use the same electroplating solution and equipment and perform electroplating with a high current density to prepare a protective layer of the gold-silver alloy bump. The current density is 1.2 ASD, the electroplating time is 20 seconds, the thickness of gold and silver in this layer is about 150 nm, the gold content is 72 wt%, and the overall roughness of the gold-silver alloy bump is 82 nm.

[0058] S4 Use a stripping solution to remove the photoresist on the chip to be encapsulated;

[0059] S5 Use an etching solution to remove the gold seed layer on the silicon substrate of the chip to be encapsulated;

[0060] S6 Remove the TiW layer on the silicon substrate of the chip to be encapsulated;

[0061] S7 Anneal the gold-silver alloy bump, the annealing temperature is 290 °C, the annealing time is 30 min, and the hardness of the gold-silver alloy bump after annealing is 95 HV.

[0062] Example 3

[0063] Detect the grain size of the gold-silver alloy bumps obtained in Example 1 and Example 2.

[0064] Use EBSD to perform microstructure analysis on the gold-silver alloy coatings of the gold-silver alloy bumps obtained in Example 1 and Example 2, as Figure 7 shown. EDSB crystal structure analysis: a1 and a2 are the IPF diagrams and grain distribution diagrams before annealing in Example 1. b1 and b2 are the IPF diagrams and grain distribution diagrams after annealing in Example 1. c1 and c2 are the IPF diagrams and grain distribution diagrams before annealing in Example 2. d1 and d2 are the IPF diagrams and grain distribution diagrams after annealing in Example 2.

[0065] For the gold-silver alloy of Example 1, the median of the equivalent circle diameter of the grains before annealing is 0.23 μm, and the equivalent circle diameter of the grains corresponding to ±2 standard deviations (data range of 2.5% - 97.5%) is 0.14 - 0.69 μm; after annealing, the median of the equivalent circle diameter of the grains is 0.28 μm, and the equivalent circle diameter of the grains corresponding to ±2 standard deviations is 0.14 - 0.89 μm. For the gold-silver alloy of Example 2, the median of the equivalent circle diameter of the grains before annealing is 0.18 μm, and the equivalent circle diameter of the grains corresponding to ±2 standard deviations is 0.14 - 0.34 μm; after annealing, the median of the equivalent circle diameter of the grains is 0.27 μm, and the equivalent circle diameter of the grains corresponding to ±2 standard deviations is 0.14 - 1.75 μm. From the above data, it can be seen that by increasing the gold content in the coating, the overall size of the grains becomes smaller, which corresponds to the conclusion that increasing the gold content in the coating increases the hardness of the coating; comparing the grain sizes before and after annealing, a larger proportion of the grains in the annealed coating have larger sizes. Comparing with Patent CN104099653B, the average diameter of the grains is 0.7 - 0.8 μm, and the standard deviation is 0.2 - 0.4 μm. It can be seen that the method of the present invention can be used to prepare a gold-silver alloy with smaller grains and more uniform distribution. In addition, from the grain distribution described in CN104099653B ( Figure 2 ), it can be seen that a larger proportion of the grains have larger sizes, while in the present invention, a larger proportion of the grains have smaller sizes, and there are significant differences between the two.

[0066] Example 4

[0067] Test the anti-sulfidation and anti-oxidation properties of gold-silver alloy bumps with different gold contents.

[0068] Compared with pure gold, the anti-sulfidation or anti-oxidation ability of the silver coating is not as good as that of the gold coating. Therefore, the anti-sulfidation or anti-oxidation ability of gold-silver alloys with different gold contents was evaluated. A 1% sodium sulfide solution was prepared. After the electroplated gold-silver alloy was placed in this solution for 30 minutes, it was then washed with water and dried. The anti-sulfidation ability of the coating was evaluated by comparing the colors of the specimen before and after soaking; in the same 1% sodium sulfide solution, the electroplated gold-silver alloy was placed for 1 minute, then directly placed in the air for 10 minutes without rinsing, and then washed with water and dried. The anti-oxidation ability of the coating was evaluated by comparing the colors of the specimen before and after soaking. As Figure 8As shown, the antioxidant and anti-sulfidation abilities of the pure silver coating are both poor, and the color change of the coating is obvious after soaking in the NaS solution. The anti-sulfidation ability of the gold-silver coating with a gold content of more than 30wt% is improved a lot. After soaking in the NaS solution for 30 minutes, the color of the coating hardly changes. However, for the antioxidant ability of the plating solution, that is, soaking in the NaS solution for 1 minute and then oxidizing in the air for 10 minutes, for the coating with a gold content of less than 60%, the coating still changes color somewhat, indicating that the antioxidant ability is still insufficient. For the coating with a gold content of more than 60%, it is very close to the color of pure gold, and the antioxidant and anti-sulfidation abilities of the coating have been significantly improved.

[0069] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limitations of the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention without departing from the principles and purposes of the present invention. The protection scope of the present invention is defined by the claims and their equivalent technical solutions.

Claims

1. A gold-silver alloy bump replacing a pure gold bump for flip chip packaging, characterized in that, The gold-silver alloy bump is composed of two gold-silver alloy layers, namely a connection layer and a protection layer; the gold content of the connection layer is 20-50 wt%; the gold content of the protection layer is more than 60 wt%; the average grain size of the grains in the gold-silver alloy layer is 0.10-0.30 μm.

2. The gold-silver alloy bump according to claim 1, wherein The gold content of the connection layer is 20-40 wt%.

3. The gold-silver alloy bump according to claim 1, wherein, The gold content of the connection layer is 30-50 wt%.

4. The gold-silver alloy bump according to claim 1, characterized in that The thickness of the connection layer is 7-20 μm, and the thickness of the protection layer is 10-500 nm.

5. The preparation method of the gold-silver alloy bump according to any one of claims 1-4, characterized in that, It includes the following steps: S1 Pretreat the chip to be encapsulated and prepare the electroplating solution. The composition and concentration of the electroplating solution are: potassium gold cyanide 6-10 g / L, potassium silver cyanide 4-7 g / L, potassium pyrophosphate 50-70 g / L, hydantoin 20-40 g / L, and the pH value is 8-10. S2 Place the chip to be encapsulated in the electroplating solution of step S1, and perform electroplating with a low current density, where the low current density is 0.3 - 0.6 A / dm 2 , and the electroplating time is 30 - 60 min to prepare a connection layer of a gold-silver alloy bump; S3 uses the same electroplating solution and equipment, and electroplates with a high current density, where the high current density is 1.1 - 1.3 A / dm 2 , the electroplating time is 20 - 40 s, to prepare a protective layer for the gold-silver alloy bumps; S4 Remove the auxiliary materials of the chip to be encapsulated. S5 Anneal the gold-silver alloy bump.

6. The preparation method according to claim 5, wherein In step S4, removing the auxiliary materials of the chip to be encapsulated includes using a degluing solution to remove the photoresist of the chip to be encapsulated, using an etching solution to remove the gold seed layer on the silicon substrate of the chip to be encapsulated, and removing the titanium-tungsten layer on the silicon substrate of the chip to be encapsulated; the degluing solution is N-methylpyrrolidone, the etching solution is a thiourea solution, and the substance for removing the titanium-tungsten layer is an H2O2 solution.

7. The preparation method according to claim 5, wherein The annealing temperature in step S5 is 270-300 °C, and the annealing time is 5-60 min.

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