Multi-channel successive approximation type analog-to-digital converter system, integrated circuit, chip and device

Abstract

The present disclosure relates to a multi-channel successive approximation type analog-to-digital converter system, an integrated circuit, a chip, and a device. The system includes: a multi-stage ring oscillator circuit and a plurality of successive approximation type analog-to-digital converters; the multi-stage ring oscillator circuit is configured to generate a plurality of clock signals with different phases and output the plurality of clock signals with different phases to the plurality of successive approximation type analog-to-digital converters; the plurality of successive approximation type analog-to-digital converters commonly input the same reference voltage, and each successive approximation type analog-to-digital converter is configured to convert an input analog signal into a digital signal based on the reference voltage under the control of the input clock signal, wherein different successive approximation type analog-to-digital converters input clock signals with different phases so that different successive approximation type analog-to-digital converters perform analog-to-digital conversion at different times. Thereby, the disturbance effect of the capacitor switching on the reference voltage in each SAR ADC can be minimized, thus effectively improving the analog-to-digital conversion performance of the multi-channel SAR ADC.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technologies, and particularly to a multi-channel successive approximation analog-to-digital converter system, an integrated circuit, a chip, and a device. Background Art

[0002] The successive approximation analog-to-digital converter (SAR ADC) is widely used due to its simple structure, low power consumption, and process-friendly characteristics. For example, Figure 1 the basic circuit structure of the single-channel SAR ADC mainly includes a sample-and-hold circuit (S / H), a digital-to-analog converter (DAC) of the analog-to-digital converter, a comparator, a successive approximation register (SAR Logic), and other parts. Among them, the sample-and-hold circuit samples and holds the input analog signal Vin. The comparator compares Vin with the voltage signal Vdac generated by the DAC. The comparison result is digitally latched by SAR Logic and controls the DAC to flip to generate a new reference voltage signal, and then compares it with Vin again. SAR Logic generally uses a binary search algorithm to control the voltage signal generated by the DAC based on the comparison result of the comparator. As Figure 2 shows the basic working principle of the SAR ADC. Vref is the reference voltage provided externally to the DAC. The voltage signal Vdac output by the DAC controlled by SAR Logic for the first time is Vref / 2, the second time is Vref / 2 ± Vref / 4, the third time is Vref / 2 ± Vref / 4 ± Vref / 8, the fourth time is Vref / 2 ± Vref / 4 ± Vref / 8 ± Vref / 16, and N-bit comparisons are performed in sequence. During this process, the voltage signal Vdac established by the DAC gradually approaches Vin, or in other words, it is judged bit by bit whether Vin is less than or greater than Vdac. If Vin > Vdac at the nth time, the comparator outputs a logic high level or "1", and the nth bit of SAR Logic is 1. Conversely, if Vin < Vdac, the comparator inputs a logic low level or "0", and the nth bit of SAR Logic is 0, and so on until the least significant bit of SAR Logic is compared. After the above operations are completed, the conversion of the analog signal Vin to the digital signal Dout is completed, and the conversion result can be latched in the SAR Logic register. Among them, the DAC generally uses a capacitive DAC at present, which can provide better matching than a resistive DAC. The capacitor in the DAC requires Vref to provide energy during the capacitor flipping process when generating a new voltage signal Vdac each time. Among them, Vref can be provided externally by the chip, and a large capacitor of the uF level can be used outside the chip to stabilize the voltage.

[0003] Multi-channel SAR ADCs are widely used because they can perform analog-to-digital conversion on multiple signals simultaneously. Generally, multiple-channel SAR ADCs share a common reference voltage Vref to effectively save resources and facilitate functions such as gain calibration. For example, Figure 3 shows a block diagram of the structure of a multi-channel SAR ADC, including multiple SAR ADCs. Each SAR ADC can adopt Figure 1 the shown circuit structure. The multiple SAR ADCs output the converted digital signals outward through a serial interface or a parallel interface. Among them, the same reference voltage Vref is input into the multiple SAR ADCs to perform analog-to-digital conversion on multiple input signals (Vin1 to Vini). In a multi-channel SAR ADC, when the SAR ADCs of each channel work simultaneously, the capacitor switching of the DAC in the SAR ADC will impact Vref, causing jitter of Vref and thus affecting the analog-to-digital conversion performance of the SAR ADCs of each channel. Summary of the Invention

[0004] In view of this, the present disclosure proposes a multi-channel successive approximation analog-to-digital converter system, integrated circuit, chip, and device, which can control the SAR ADCs of different channels to perform analog-to-digital conversion at different times, so as to minimize the disturbance effect of the capacitor switching of the DAC in each channel of the SAR ADCs on the reference voltage as much as possible, thereby effectively improving the analog-to-digital conversion performance of the multi-channel SAR ADC.

[0005] According to one aspect of the present disclosure, there is provided a multi-channel successive approximation analog-to-digital converter system, including: a multi-stage ring oscillator circuit and multiple successive approximation analog-to-digital converters; the multi-stage ring oscillator circuit is configured to generate multiple clock signals with different phases and output the multiple clock signals with different phases to the multiple successive approximation analog-to-digital converters; the multiple successive approximation analog-to-digital converters commonly input the same reference voltage, and each successive approximation analog-to-digital converter is configured to, under the control of the input clock signal, convert the input analog signal into a digital signal based on the reference voltage, wherein different successive approximation analog-to-digital converters input clock signals with different phases, so that different successive approximation analog-to-digital converters perform analog-to-digital conversion at different times.

[0006] In a possible implementation, the multi-stage ring oscillator circuit includes: n inverters connected end to end for generating n initial clock signals with different phases; and a plurality of logic gate circuits for generating m clock signals with different phases according to the n initial clock signals with different phases; where n is an odd number greater than 1, m includes 2n, and the plurality of logic gate circuits include n NOT gates and m AND gates; the n NOT gates are used for generating n inverted signals with different phases according to the n initial clock signals with different phases; the m AND gates are used for generating m clock signals with different phases according to the n initial clock signals with different phases and the n inverted signals with different phases.

[0007] In a possible implementation, each successive approximation analog-to-digital converter includes: a sample-and-hold circuit, a comparator, a successive approximation logic circuit, and a digital-to-analog converter; where the different clock signals generated by the multi-stage ring oscillator circuit are input to the comparators in different successive approximation analog-to-digital converters to control the comparators in different successive approximation analog-to-digital converters to perform comparisons at different times; where the sample-and-hold circuit is used for sampling and holding an input analog signal and outputting a sampled signal to the comparator; the digital-to-analog converter is used for generating a reference signal according to the reference voltage and a control signal output by the successive approximation logic circuit and outputting the reference signal to the comparator; the control signal is used for controlling the digital-to-analog converter to perform capacitor flipping to generate different reference signals; the comparator is used for comparing the sampled signal with the reference signal under the control of an input clock signal and outputting a comparison result to the successive approximation logic circuit; the successive approximation logic circuit is used for generating the control signal based on the comparison result and outputting a digital signal corresponding to the analog signal.

[0008] In a possible implementation, the comparator is used for comparing the sampled signal and the reference signal during the positive pulse width of the input clock signal, ending the comparison at the falling edge of the positive pulse of the clock signal, and outputting the comparison result to the successive approximation logic circuit.

[0009] In a possible implementation, the digital-to-analog converter includes a capacitor array and switches connected to each capacitor in the capacitor array, and an output end of the capacitor array is connected to the comparator to output a reference signal to the comparator; the reference voltage is input to each capacitor in the capacitor array through corresponding switches; the control signal generated by the successive approximation logic circuit is used for controlling the flipping of the switches connected to the capacitor array to control the flipping of the capacitors in the capacitor array to generate different reference signals.

[0010] In a possible implementation, the system further includes: a reference voltage input circuit configured to input the same reference voltage to the digital-to-analog converters in the plurality of successive approximation analog-to-digital converters. The reference voltage input circuit includes positive and negative voltage input terminals, and a plurality of sub-voltage input circuits connected to the positive and negative voltage input terminals; the positive and negative voltage input terminals include a positive voltage input terminal and a negative voltage input terminal; wherein each sub-voltage input circuit includes: a decoupling capacitor, two first resistors, and two second resistors; both ends of the decoupling capacitor are respectively connected to the first end of a first resistor, the second end of each first resistor is respectively connected to the first end of a second resistor and the analog-to-digital converter, the first end of each second resistor is further connected to the digital-to-analog converter, and the second ends of the two second resistors are respectively connected to the positive and negative input terminals, so that the reference voltage provided by each sub-voltage input circuit to the connected digital-to-analog converter is between the voltage value of the second resistor and the voltage value of the first resistor.

[0011] In a possible implementation, the system further includes: a serial interface or a parallel interface connected to the plurality of successive approximation analog-to-digital converters, configured to output digital signals generated by the respective successive approximation analog-to-digital converters.

[0012] According to another aspect of the present disclosure, there is provided an integrated circuit including: the multi-channel successive approximation analog-to-digital converter system according to any one of the above.

[0013] According to another aspect of the present disclosure, there is provided a chip including: the multi-channel successive approximation analog-to-digital converter system according to any one of the above.

[0014] According to another aspect of the present disclosure, there is provided an electronic device including: the integrated circuit as described above, and / or, the chip as described above.

[0015] According to various aspects of the present disclosure, by generating a plurality of clock signals with different phases through a multi-stage ring oscillator circuit for different SAR ADCs, it is possible to control different SAR ADCs to perform analog-to-digital conversion according to the same reference voltage at different times, and the impact time of the capacitor flips in each SAR ADC on the reference voltage can be staggered, and the disturbance effect on the reference voltage can be minimized as much as possible, so that the interference generated by any SAR ADC during analog-to-digital conversion to other SAR ADCs can be effectively reduced, which is beneficial to improving the analog-to-digital conversion performance of the multi-channel SAR ADC.

[0016] According to the following detailed description of the exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present disclosure will become clear. Description of the Drawings

[0017] The accompanying drawings included in and forming a part of the specification illustrate exemplary embodiments, features, and aspects of the present disclosure, and are used to explain the principles of the present disclosure together with the specification.

[0018] Figure 1 Schematic diagram showing the basic circuit structure of a single-channel SAR ADC in the related art.

[0019] Figure 2 Schematic diagram showing the basic working principle of a SAR ADC in the related art.

[0020] Figure 3 Block diagram showing the hardware structure of a multi-channel SAR ADC in the related art.

[0021] Figure 4 Schematic diagram showing the crosstalk of the reference voltage caused by the capacitor switching in a multi-channel SAR ADC in the related art.

[0022] Figure 5 Schematic diagram showing the structure of a multi-channel successive approximation analog-to-digital converter system according to an embodiment of the present disclosure.

[0023] Figure 6 Schematic diagram showing the structure of a multi-stage ring oscillator circuit 11 according to an embodiment of the present disclosure.

[0024] Figure 7 Schematic diagram showing the waveform of the clock signal output by the multi-stage ring oscillator circuit 11 according to an embodiment of the present disclosure.

[0025] Figure 8 Schematic diagram showing the structure of a successive approximation analog-to-digital converter according to an embodiment of the present disclosure.

[0026] Figure 9 Schematic diagram showing the reference voltage input circuit in a multi-channel SAR ADC according to an embodiment of the present disclosure.

[0027] Figure 10 Schematic diagram showing the influence of different Rdeq on the establishment of the reference voltage according to an embodiment of the present disclosure.

[0028] Figure 11 Schematic diagram showing a reference voltage input circuit according to an embodiment of the present disclosure.

[0029] Figure 12 Schematic diagram showing the time-domain response of the reference voltage at different Rd according to an embodiment of the present disclosure.

[0030] Figure 13 Schematic diagram showing the structure of a multi-channel successive approximation analog-to-digital converter system according to an embodiment of the present disclosure. Detailed implementation manners

[0031] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. Like reference numerals in the drawings denote functionally identical or similar elements. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0032] In the description of the present disclosure, it should be understood that the orientation or positional relationships indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present disclosure.

[0033] In addition, the terms "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, "a plurality" means two or more unless otherwise specifically defined.

[0034] In the present disclosure, unless otherwise clearly specified and defined, the terms "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral body; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0035] The special term "exemplary" herein means "serving as an example, embodiment, or illustration". Any embodiment described as "exemplary" herein need not be construed as superior to or better than other embodiments.

[0036] In addition, for a better illustration of the present disclosure, numerous specific details are given in the following specific embodiments. Those skilled in the art should understand that the present disclosure can be implemented without some specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0037] As described above, when multiple-channel SAR ADCs work simultaneously, the capacitor switching in the DACs of each channel's SAR ADC will impact the reference voltage Vref, causing jitter in Vref and thus affecting the analog-to-digital conversion performance of each channel's SAR ADC. Therefore, in one possible implementation, since each channel's SAR ADC can work independently, an internal clock can be set in each channel's SAR ADC to control the comparison process of the comparators in each channel, so as to stagger the capacitor switching times of the DACs in each SAR ADC. For example, taking a 6-channel SAR ADC as an example, each channel's SAR ADC can be set with an internal clock to control the comparison time of the comparator, thereby reducing the crosstalk of each channel's SAR ADC to the reference voltage Vref.

[0038] And a 6-channel SAR ADC requires 6 internal clocks to generate 6 clock signals (clk1~clk6). If each SAR ADC uses an oscillator (as the internal clock) to generate a clock with a fixed frequency and there is no strong correlation between the 6-channel SAR ADCs, there may still be interference between the multiple-channel SAR ADCs. For example, as Figure 4 shown, at the critical moment when the comparator in one path of the SAR ADC is making a comparison (i.e., the high-level interval in CLK1_CMP), the DACs in another path or the other 5 paths of the SAR ADCs may be performing capacitor switching (i.e., the low-level intervals in CLK2_CMP to CLK6_CMP), which will also cause a large jitter in the reference voltage Vref, affecting the comparison process of the comparator in one path of the SAR ADC and greatly affecting the analog-to-digital conversion performance of this path of the SAR ADC. That is to say, if there is no correlation between multiple-channel SAR ADCs, then when one path of the SAR ADC is working, it will be affected by the other SAR ADCs.

[0039] In view of this, the embodiments of the present disclosure propose a successive approximation analog-to-digital converter system. Through a multi-stage ring oscillator circuit, multiple clock signals with different phases and correlated with each other can be generated. Furthermore, by controlling the clock phases input to each channel's SAR ADC, the impact time of the capacitor switching of each channel's SAR ADC on the reference voltage Vref can be staggered, and the disturbance effect on the reference voltage Vref can be minimized as much as possible to improve the analog-to-digital conversion performance of the multi-channel SAR ADC.

[0040] Figure 5 Fig. shows a schematic structural diagram of a multi-channel successive approximation analog-to-digital converter system according to an embodiment of the present disclosure. As Figure 5 shown, the system includes:

[0041] A multi-stage ring oscillator circuit 11 and a plurality of successive approximation analog-to-digital converters (SAR ADC1, SAR ADC2, …, SAR ADCi);

[0042] The multi-stage ring oscillator circuit 11 is configured to generate a plurality of clock signals (clk1, clk2, …, clki) with different phases and output the plurality of clock signals with different phases to the plurality of successive approximation analog-to-digital converters (SAR ADC1, SAR ADC2, …, SAR ADCi);

[0043] The plurality of successive approximation analog-to-digital converters commonly input the same reference voltage Vref. Each successive approximation analog-to-digital converter is configured to convert the input analog signals (vin1, vin2, …, vini) into digital signals (Dout1, Dout2, …, Douti) based on the reference voltage Vref under the control of the input clock signals (clk1, clk2, …, clki). Among them, different successive approximation analog-to-digital converters input clock signals with different phases so that different successive approximation analog-to-digital converters perform analog-to-digital conversion at different times.

[0044] In a possible implementation manner, taking the example of providing 6 clock signals to a 6-channel SAR DAC, the embodiments of the present disclosure provide Figure 6 A multi-stage ring oscillator circuit 11 as shown in Figure 6 As shown, the multi-stage ring oscillator circuit 11 includes:

[0045] n inverters connected end to end (such as 3 inverters 111, 112, 113) for generating n initial clock signals with different phases (such as CLKA, CLKB, CLKC); and,

[0046] A plurality of logic gate circuits, the plurality of logic gate circuits including n NOT gates (such as 3 NOT gates 114, 115, 116) and m AND gates (such as 6 AND gates 121, 122, 123, 124, 125, 126) for generating m clock signals with different phases (such as CLK1 to CLK6) according to the n initial clock signals with different phases; where n is an odd number greater than 1 and m includes 2n;

[0047] Among them, n NOT gates are used to generate n inverted signals with different phases according to n initial clock signals with different phases. For example, the output terminal of inverter 111 is connected to NOT gate 114, so that NOT gate 114 generates an inverted signal CLKA_B according to the initial clock signal CLKA output by inverter 111; the output terminal of inverter 112 is connected to NOT gate 115, so that NOT gate 115 generates an inverted signal CLKB_B according to the initial clock signal CLKB output by inverter 112, and the output terminal of inverter 113 is connected to NOT gate 116, so that NOT gate 116 generates an inverted signal CLKC_B according to the initial clock signal CLKC output by inverter 113;

[0048] Among them, m AND gates are used to generate m clock signals with different phases according to n initial clock signals with different phases and n inverted signals with different phases. For example, the output terminal of inverter 111 and the output terminal of NOT gate 116 are respectively connected to the two input terminals of AND gate 121, so that AND gate 121 generates a clock signal CLK1 according to the initial clock signal CLKA output by inverter 111 and the inverted signal CLKC_B output by NOT gate 116; the output terminal of inverter 111 and the output terminal of NOT gate 115 are respectively connected to the two input terminals of AND gate 122, so that AND gate 122 generates a clock signal CLK2 according to the initial clock signal CLKA output by inverter 111 and the inverted signal CLKB_B output by NOT gate 115; the output terminal of inverter 113 and the output terminal of NOT gate 115 are respectively connected to the two input terminals of AND gate 123, so that AND gate 123 generates a clock signal CLK3 according to the initial clock signal CLKC output by inverter 113 and the inverted signal CLKB_B output by NOT gate 115; the output terminal of inverter 113 and the output terminal of NOT gate 114 are respectively connected to the two input terminals of AND gate 124, so that AND gate 124 generates a clock signal CLK4 according to the initial clock signal CLKC output by inverter 113 and the inverted signal CLKA_B output by NOT gate 114; the output terminal of inverter 112 and the output terminal of NOT gate 114 are respectively connected to the two input terminals of AND gate 125, so that AND gate 125 generates a clock signal CLK5 according to the initial clock signal CLKB output by inverter 112 and the inverted signal CLKA_B output by NOT gate 114; the output terminal of inverter 112 and the output terminal of NOT gate 116 are respectively connected to the two input terminals of AND gate 126, so that AND gate 126 generates an initial signal CLK6 according to the initial clock signal CLKB output by inverter 112 and the inverted signal CLKC_B output by NOT gate 116.

[0049] Such as Figure 7Schematic diagram of the waveform of the clock signal output by the multi-stage ring oscillator circuit 11 shown. Through the logical gate combination of the above 3 NOT gates and 6 AND gates, the 3 initial clock signals CLKA, CLKB, and CLKC with different phases output by the 3 inverters connected end to end can be converted into 6 clock signals CLK1 to CLK6 with different phases and interrelated. In other words, a multi-stage ring oscillator circuit can be used to provide clock signals for 6-channel SAR ADCs, as Figure 6 The multi-stage ring oscillator circuit 11 shown can generate three-phase initial clock signals CLKA, CLKB, and CLKC, and then 6 clock signals CLK1 to CLK6 with a phase difference of 60° can be formed through the logical gate combination. It should be understood that each channel SAR ADC can select a clock signal of one phase, that is, different SAR ADCs can select clock signals of different phases, and of course, the same clock signal can also be selected. Thus, the relative time for the comparators in each SAR ADC to make comparisons can be controlled.

[0050] It should be noted that although the above multi-stage ring oscillator circuit 11 is introduced by taking Figure 6 as an example, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, those skilled in the art can flexibly set the number of inverters, NOT gates, and AND gates in the multi-stage ring oscillator circuit 11 according to the number of SAR ADCs in the actual application scenario. For example, a multi-stage ring oscillator circuit including 5 inverters can be used to generate 10 clock signals with different phases and interrelated (that is, 10 clock signals with a phase difference of 36°); of course, inspired by the embodiments of the present disclosure, those skilled in the art can also use other types of logic gate circuits in combination with the ring oscillator, as long as multiple clock signals with different phases and interrelated can be generated, and the embodiments of the present disclosure do not limit this.

[0051] As Figure 8 shown, each successive approximation analog-to-digital converter includes: a sample and hold circuit (i.e., S / H), a comparator, a successive approximation logic circuit (i.e., SAR Logic), and a digital-to-analog converter DAC; among them, the different clock signals generated by the multi-stage ring oscillator circuit can be input to the comparators in different successive approximation analog-to-digital converters to control the comparators in different successive approximation analog-to-digital converters to make comparisons at different times;

[0052] Among them, the sample and hold circuit is used to sample and hold the input analog signal and output the sampled signal Vin to the comparator;

[0053] The digital-to-analog converter is used to generate a reference signal Vdac according to a reference voltage Vref and a control signal Cont output by a successive approximation logic circuit, and output the reference signal Vdac to a comparator; the control signal Cont is used to control the digital-to-analog converter DAC to perform capacitor flipping to generate different reference signals Vdac;

[0054] The comparator is used to compare a sampled signal Vin with a reference signal Vdac under the control of an input clock signal (such as a clock signal CLKi), and output a comparison result Dcomp to a successive approximation logic circuit (SAR Logic);

[0055] The successive approximation logic circuit (SAR Logic) is used to generate a control signal Cont based on the comparison result Dcomp, and output a digital signal Dout corresponding to an analog signal.

[0056] In practical applications, the embodiments of the present disclosure do not limit the type, structure, etc. of the comparator. For example, the comparator can adopt a preamplifier + latch type comparator, and the embodiments of the present disclosure do not limit this. Among them, the successive approximation logic circuit can include a successive approximation type register to realize the conversion of an analog signal into a digital signal. The embodiments of the present disclosure do not limit the type, circuit structure, etc. of the successive approximation logic circuit, as long as it can realize the functions it needs to achieve.

[0057] In a possible implementation manner, the comparator can be used to compare the sampled signal and the reference signal during the positive pulse width of the input clock signal, end the comparison at the falling edge of the positive pulse of the clock signal, and output the comparison result to the successive approximation logic circuit. This method can be understood as performing a comparison operation during the positive pulse of the clock signal (i.e., the high level period), ending the comparison operation and outputting the comparison result to the successive approximation logic circuit when the positive pulse ends and enters the negative pulse (i.e., from high level to low level). For example, for a comparator of the preamplifier + latch type, the positive pulse width time of the clock signal is the time for the preamplifier (equivalent to comparison) to perform preamplification. When entering the falling edge of the positive pulse, the preamplifier ends the comparison, latches the comparison result in the latch, and sends the comparison result to the successive approximation logic circuit. It should be understood that since the phases of different clock signals entering the positive pulse are different, the above method can make the comparison time of the comparators in different channel SAR ADCs different, thereby reducing the impact of capacitor flipping in the digital-to-analog converter on the reference voltage in any channel SAR ADC, which is beneficial to improving the analog-to-digital conversion performance of each channel SAR ADC.

[0058] As described above, the digital-to-analog converter can adopt a capacitive DAC. In a possible implementation manner, the digital-to-analog converter includes a capacitor array (such as Figure 8The DAC shown includes a capacitor array composed of 1C, 2C, 4C, and 8C, as well as switches connected to each capacitor in the capacitor array. The output terminal of the capacitor array is connected to a comparator to output a reference signal Vdac to the comparator; the reference voltage Vref (i.e., the reference voltage generated between the positive and negative input terminals VREFP and VREFN) is input to each capacitor in the capacitor array through corresponding switches respectively;

[0059] The control signals generated by the successive approximation logic circuit are used to control the flipping of each switch connected to the capacitor array, so as to control the flipping of the capacitors in the capacitor array to generate different reference signals. Among them, controlling the flipping of each switch, that is, controlling the opening and closing of each switch. For example, by controlling Figure 8 the flipping of the corresponding switches of the capacitor array shown, the reference signal Vdac output by the capacitor array in the digital-to-analog converter can include voltage values such as Vref / 2, Vref / 2 ± Vref / 4, Vref / 2 ± Vref / 4 ± Vref / 8, etc.

[0060] For example, assume that the clock signal CLKi generated by the multi-stage ring oscillator circuit 11 is used as the synchronization clock for the operation of a SAR ADC. The internal working process of the SAR ADC can be simplified as follows: CLKi controls the comparator to start comparing. Taking the preamplifier + latch type comparator as an example, the preamplifier performs preamplification during the positive pulse width time of CLKi, ends the preamplification at the falling edge of CLKi and latches the comparison result in the latch. After obtaining the comparison result Dcomp, the result is latched in the SAR logic to output a digital signal. At the same time, according to this comparison result, the corresponding capacitors in the capacitor array in the DAC are controlled to flip. Since the lower end of the capacitor array is connected to the input terminal VREFP or VREFN of the reference voltage through a switch, this process will cause an impact on VREFP / VREFN, which may affect other channel SAR ADCs. At the same time, the reference voltage on the DAC will also change accordingly. After the reference voltage is restored and established to a certain extent, the next positive pulse of CLKi starts the second comparison, and so on until the comparison ends.

[0061] According to the embodiments of the present disclosure, by generating multiple clock signals with different phases by the multi-stage ring oscillator circuit 11 for different SAR ADCs, it is possible to control different SAR ADCs to perform analog-to-digital conversion according to the same reference voltage at different times, and the impact time of the capacitor flipping on the reference voltage in each SAR ADC can be staggered, and the disturbance influence on the reference voltage can be minimized as much as possible. Thus, the interference generated by any SAR ADC during analog-to-digital conversion to other SAR ADCs can be effectively reduced, which is beneficial to improving the analog-to-digital conversion performance of the multi-channel SAR ADC.

[0062] In actual situations, when a certain channel SAR ADC is working, in order to reduce the impact of capacitor switching on the reference voltage, which may affect other channel SAR ADCs, such as Figure 9 In the schematic diagram of the reference voltage input circuit of the multi-channel SAR ADC shown, decoupling capacitors (Cdecap1, Cdecap2, …, Cdecapi) at the pF level can be added between the positive and negative voltage input terminals VREFP and VREFN. Among them, the voltage between VREFP1 and VREFN1 is the reference voltage provided to capacitor DAC1, the voltage between VREFP2 and VREFN2 is the reference voltage provided to capacitor DAC2, and so on. The voltage between VREFPi and VREFNi is the reference voltage provided to capacitor DACi. In this way, most of the charge extracted by capacitor switching in each DAC is provided by the parallel decoupling capacitors, and at the same time, the off-chip Vref charges the decoupling capacitors to reduce the impact of capacitor switching in the DAC on the reference voltage.

[0063] However, because there is still a wire connection from the off-chip Vref to the DAC, the resulting inductance (such as Figure 9 the parasitic inductance L shown) and Cdecap will resonate. This oscillation will have a great impact on the performance of the SAR ADC. Therefore, a resistor Rdeq can be connected between the positive and negative voltage input terminals and the decoupling capacitors to reduce the Q value of the circuit, thereby reducing the disturbance on Vref. That is, connecting a relatively large resistor Rdeq in the Vref path can effectively reduce the Q value and avoid resonance, making Vref not easily oscillate, that is, the oscillation amplitude of Vref can be weakened. However, for high-speed SAR ADCs, a larger Rdeq means a larger RC constant (that is, a lower response speed), which will cause the reference voltage on Cdecap to take a long time to recover to the normal reference voltage value. If the comparator makes a comparison at this time, there will be a settling error, which greatly affects the performance of the SAR ADC. That is, the larger the Rdeq, the longer the recovery time of Vref after drawing current, which is very unfriendly to the DAC to establish the reference signal Vdac. If the circuit redundancy is insufficient, it will cause the performance of the SAR ADC to decline. As Figure 10 shown, without Rdeq (Rdeq = 0Ω), Vref will oscillate, and as Rdeq increases (from 5Ω, 10Ω, 15Ω, 20Ω, 25Ω, 30Ω), the recovery time of the reference voltage on Cdecap becomes longer.

[0064] In short, although a larger Rdeq resistor can suppress the oscillation on VREF, Vref recovers more slowly. Therefore, the above system of the embodiments of the present disclosure may further include Figure 11 the reference voltage input circuit shown, which is used to input the same reference voltage to the digital-to-analog converters in multiple successive approximation analog-to-digital converters;

[0065] Among them, the reference voltage input circuit includes positive and negative voltage input terminals, and a plurality of sub-voltage input circuits connected to the positive and negative voltage input terminals; the positive and negative voltage input terminals include a positive voltage input terminal VREFP and a negative voltage input terminal VREFN;

[0066] Among them, each sub-voltage input circuit includes: a decoupling capacitor Cdecap, two first resistors Rd, and two second resistors Rdeq; both ends of the decoupling capacitor Cdecap are respectively connected to the first end of a first resistor Rd, the second end of each first resistor Rd is respectively connected to the first end of a second resistor Rdeq and an analog-to-digital converter (i.e., a capacitive DAC), the first end of each second resistor Rdeq is also connected to a digital-to-analog converter (i.e., a capacitive DAC), and the second ends of the two second resistors Rdeq are respectively connected to the positive and negative input terminals (VREFP and VREFN), so that the reference voltage Vref provided by each sub-voltage input circuit to the connected digital-to-analog converter DAC is between the voltage value of the second resistor Rdeq and the voltage value of the first resistor Rd.

[0067] The above-mentioned reference voltage input circuit proposed by the embodiments of the present disclosure can accelerate the recovery and establishment of the reference voltage Vref. Compared with Figure 9 the reference voltage input circuit shown Figure 11 The shown reference voltage input circuit can make the reference voltage provided to the capacitive DAC be between the voltage value of Rdeq and the voltage value of Rd by connecting two resistors Rd in series above and below the decoupling capacitor Cdecap, and Rd and Cdecap can form a zero point to broaden the impedance at VREFP / VREFN, so that the reference voltages between VREFP1 and VREFN1, between VREFP2 and VREFN2, and between VREFPi and VREFNi after the DAC switches the capacitor can be established faster, thereby reducing the establishment error of the reference signal generated by the DAC, and further reducing the comparison error of the comparator, which is beneficial to improving the analog-to-digital conversion performance of each channel SAR ADC. Among them, Figure 11 the inductor L shown represents the parasitic inductance on the circuit board.

[0068] Figure 12It shows the recovery of the reference voltage Vref after the DAC capacitor flip impacts the reference voltage Vref when Rdeq = 10Ω and different sizes of Rd are adopted (i.e., Rd = 0Ω, 5Ω, 10Ω, 15Ω, 20Ω, 25Ω, 30Ω). It can be seen that, compared with not using the first resistor Rd (i.e., Rd is 0), connecting two first resistors Rd in series at both ends of the decoupling capacitor can effectively improve the recovery and establishment speed of the reference voltage. Moreover, by selecting an appropriate value of the Rd resistor, the signal establishment process of Vref can be effectively accelerated, and Vref does not oscillate. The faster the establishment of Vref input into each channel of the SAR ADC, the smaller the establishment error of the comparator during comparison in each channel of the SAR ADC, which also reduces the crosstalk influence between channels, thereby improving the analog-to-digital conversion performance of the SAR ADC.

[0069] In a possible implementation manner, to facilitate the system to send the digital signals generated by each channel to the outside, as Figure 13 shown, the system may further include: a serial interface or a parallel interface connected to multiple successive approximation analog-to-digital converters, for outputting the digital signals generated by each successive approximation analog-to-digital converter. Among them, those skilled in the art can adopt the serial interface or the parallel interface known in the art, and the embodiments of the present disclosure do not limit this. In this way, the digital signals generated by the successive approximation analog-to-digital converter of any channel can be efficiently input to the outside.

[0070] The above embodiments of the present disclosure propose two ways to reduce the crosstalk influence of the multi-channel SAR ADC. One is to use a multi-stage ring oscillator circuit with a selectable multi-phase clock to provide clock signals with different phases, and a multi-stage ring oscillator circuit can save power consumption and area, and can also control the analog-to-digital conversion process of each channel of the SAR ADC in terms of timing. The other is to add a first resistor on the input path for applying the reference voltage and connect a second resistor in series at both ends of the decoupling capacitor to accelerate the establishment of the reference voltage. The series resistor structure is simple and the effect is obvious, and it can also reduce the crosstalk influence between multi-channel SAR ADCs, thus being beneficial to improving the analog-to-digital conversion performance of the multi-channel SAR ADC.

[0071] Based on the above multi-channel successive approximation analog-to-digital converter system provided by the embodiments of the present disclosure, the embodiments of the present disclosure further provide an integrated circuit, including: the multi-channel successive approximation analog-to-digital converter system in any of the above embodiments. It should be understood that other electronic components may also be included in this integrated circuit, and the embodiments of the present disclosure do not limit this.

[0072] An embodiment of the present disclosure also provides a chip, including: the multi-channel successive approximation analog-to-digital converter system in any of the above embodiments. It should be understood that other electronic components, modules, units, etc. may also be included in the chip, and the embodiments of the present disclosure do not limit this.

[0073] An embodiment of the present disclosure also provides an electronic device, characterized by including: the above integrated circuit, and / or, the above chip. It should be understood that other hardware, etc. may also be included in the electronic device, and the embodiments of the present disclosure do not limit this.

[0074] The embodiments of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to technologies in the market, or to enable other ordinary skill in the art in the technical field to understand the disclosed embodiments.

Claims

1. A multi-channel successive approximation analog-to-digital converter system, characterized in that: Including: A multi-stage ring oscillator circuit and a plurality of successive approximation analog-to-digital converters; The multi-stage ring oscillator circuit is used to generate a plurality of clock signals with different phases and correlated with each other, and output the plurality of clock signals with different phases and correlated with each other to the plurality of successive approximation analog-to-digital converters; The plurality of successive approximation analog-to-digital converters commonly input the same reference voltage. Each successive approximation analog-to-digital converter is used to convert an input analog signal into a digital signal based on the reference voltage under the control of the input clock signal. Among them, different successive approximation analog-to-digital converters input clock signals with different phases, so that different successive approximation analog-to-digital converters perform analog-to-digital conversion at different times; Wherein, the multi-stage ring oscillator circuit includes: n inverters connected end to end, which are used to generate n initial clock signals with different phases; and, A plurality of logic gate circuits, which are used to generate m clock signals with different phases and correlated with each other according to the n initial clock signals with different phases; Wherein, n = 3, m = 6, the plurality of logic gate circuits include n NOT gates and m AND gates; the n NOT gates are used to generate n inverted signals with different phases according to the n initial clock signals with different phases; the m AND gates are used to generate m clock signals with different phases and correlated with each other according to the n initial clock signals with different phases and the n inverted signals with different phases; Wherein, the output end of each inverter is respectively connected to the input end of a NOT gate, so that each NOT gate generates an inverted signal according to the initial clock signal output by each inverter; the output end of any one inverter and the output ends of n - 1 NOT gates other than the one NOT gate connected to this inverter are respectively connected to the input ends of n - 1 AND gates among the m AND gates, so that the n - 1 AND gates generate n - 1 clock signals with different phases and correlated with each other according to the initial clock signal output by this one inverter and the inverted signals output by the n - 1 NOT gates other than the one NOT gate connected to this inverter.

2. The system according to claim 1, wherein Each successive approximation analog-to-digital converter includes: a sample and hold circuit, a comparator, a successive approximation logic circuit, and a digital-to-analog converter; wherein, the different clock signals generated by the multi-stage ring oscillator circuit are input to the comparators in different successive approximation analog-to-digital converters to control the comparators in different successive approximation analog-to-digital converters to perform comparison at different times; Wherein, the sample and hold circuit is used to sample and hold the input analog signal, and output the sampled signal to the comparator; The digital-to-analog converter is used to generate a reference signal according to the reference voltage and the control signal output by the successive approximation logic circuit, and output the reference signal to the comparator; the control signal is used to control the digital-to-analog converter to perform capacitor flipping to generate different reference signals; The comparator is used to compare the sampled signal with the reference signal under the control of the input clock signal, and output the comparison result to the successive approximation logic circuit; The successive approximation logic circuit is configured to generate the control signal based on the comparison result and output the digital signal corresponding to the analog signal.

3. The system according to claim 2, characterized in that The comparator is configured to compare the sampled signal and the reference signal during the positive pulse width of the input clock signal, end the comparison at the falling edge of the positive pulse of the clock signal, and output the comparison result to the successive approximation logic circuit.

4. The system according to claim 2, characterized in that The digital-to-analog converter includes a capacitor array and switches connected to each capacitor in the capacitor array. The output terminal of the capacitor array is connected to the comparator to output a reference signal to the comparator. The reference voltage is input to each capacitor in the capacitor array through corresponding switches. The control signal generated by the successive approximation logic circuit is used to control the flipping of each switch connected to the capacitor array, so as to control the flipping of the capacitors in the capacitor array to generate different reference signals.

5. The system according to any one of claims 1 to 4, characterized in that, The system further includes: a reference voltage input circuit for inputting the same reference voltage to the digital-to-analog converter in the plurality of successive approximation analog-to-digital converters. The reference voltage input circuit includes positive and negative voltage input terminals and a plurality of sub-voltage input circuits connected to the positive and negative voltage input terminals. The positive and negative voltage input terminals include a positive voltage input terminal and a negative voltage input terminal. Wherein, each sub-voltage input circuit includes: a decoupling capacitor, two first resistors, and two second resistors. Two ends of the decoupling capacitor are respectively connected to the first end of a first resistor. The second end of each first resistor is respectively connected to the first end of a second resistor and the analog-to-digital converter. The first end of each second resistor is also connected to the digital-to-analog converter. The second ends of the two second resistors are respectively connected to the positive and negative input terminals, so that the reference voltage provided by each sub-voltage input circuit to the connected digital-to-analog converter is between the voltage value of the second resistor and the voltage value of the first resistor.

6. The system according to claim 1, wherein The system further includes: a serial interface or a parallel interface connected to the plurality of successive approximation analog-to-digital converters for outputting the digital signals generated by each successive approximation analog-to-digital converter.

7. An integrated circuit, characterized in that: Comprising: The system according to any one of claims 1 to 6.

8. A chip, characterized in that, Comprising: The system according to any one of claims 1 to 6.

9. An electronic device, characterized in that, Comprising: The integrated circuit according to claim 7, and / or, the chip according to claim 8.

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