Electronic packaging component and packaging substrate and manufacturing method thereof

Abstract

An electronic package and its packaging substrate and manufacturing method, the manufacturing method includes respectively pressing coreless circuit structures on two opposite surfaces of a carrier to set electronic components on each of the circuit structures, and then forming a build-up layer structure on each of the circuit structures to cover the electronic components, and then removing the carrier to obtain multiple electronic packages. The circuit structures are pressed on opposite sides of the carrier at the same time to offset the warping caused by the stress in the circuit structures to improve the yield.

Description

Technical Field

[0001] The invention relates to a semiconductor packaging process, and in particular to an electronic packaging component capable of preventing warping during the process, a packaging substrate and a manufacturing method thereof. Background Art

[0002] With the rapid development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in shape, and their functions are developing in the direction of high performance, high functionality and high speed. Therefore, in order to meet the needs of high integration and miniaturization of semiconductor devices, packaging substrates with high-density and fine-pitch circuits are often used in the packaging process.

[0003] like Figure 1 As shown, a package substrate 1 of a conventional coreless embodiment includes a plurality of stacked dielectric layers 11 and a circuit layer 12 disposed on each of the dielectric layers 11 .

[0004] As the functional requirements increase, the number of the circuit layers 12 also increases, so the overall planar packaging area of ​​the packaging substrate 10 also increases.

[0005] However, in the existing method of manufacturing the packaging substrate 1, the dielectric layer 11 is prone to warpage due to the excessively large packaging area. The warping direction F shown in the figure makes the packaging substrate 1 take on a smiley face shape, causing the circuit layer 12 to stretch or shrink, making the circuit layer 12 prone to breakage, thereby causing problems such as poor electrical reliability and low process yield.

[0006] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Summary of the invention

[0007] In view of the above-mentioned defects of the prior art, the present invention provides an electronic package and a package substrate and a manufacturing method thereof, which can at least partially solve the problems of the prior art.

[0008] The packaging substrate of the present invention includes: a core-layer-free circuit structure, which includes at least one first insulating layer and a first circuit layer arranged on the first insulating layer; and a build-up structure, which is arranged on the circuit structure, wherein the build-up structure includes at least one second insulating layer formed on the first insulating layer and a second circuit layer arranged on the second insulating layer and electrically connected to the first circuit layer, and the material forming the second insulating layer is Ajinomoto build-up film, which is different from the material forming the first insulating layer.

[0009] In the aforementioned packaging substrate, the circuit structure has a first side and a second side opposite to each other, so that the build-up layer structure is disposed on the first side and / or the second side.

[0010] The present invention also provides a method for manufacturing a packaging substrate, including: providing a carrier and a plurality of core-layer-free circuit structures, wherein the carrier has a first surface and a second surface relative to each other, wherein each of the circuit structures includes at least a first insulating layer and a first circuit layer formed on the first insulating layer; pressing the circuit structures on the first surface and the second surface of the carrier respectively, wherein the circuit structure is pressed on the carrier through a peeling layer, and the first circuit layer is embedded in the peeling layer; forming a build-up structure on each of the circuit structures, and the build-up structure includes at least a second insulating layer formed on the first insulating layer and a second circuit layer formed on the second insulating layer, so that the second circuit layer is electrically connected to the first circuit layer, wherein the material forming the second insulating layer is an Ajinomoto build-up film, which is different from the material forming the first insulating layer; and removing the carrier to obtain a plurality of packaging substrates.

[0011] In the above-mentioned manufacturing method, the circuit structure has a first side and a second side opposite to each other, so that the circuit structure is combined with the carrier with its second side, and a metal layer is combined with the first side of the circuit structure. For example, it also includes removing the metal layer first and then manufacturing the build-up structure.

[0012] In the aforementioned manufacturing method, the circuit structure has a first side and a second side opposite to each other, so that the build-up structure is disposed on the first side; and further comprises forming another build-up structure on the second side after removing the carrier.

[0013] The present invention further provides an electronic package, comprising: the aforementioned package substrate; and an electronic component, which is arranged on the circuit structure and embedded in the second insulating layer of the build-up structure, so that the electronic component is electrically connected to the first circuit layer or the second circuit layer.

[0014] In the aforementioned electronic package, the electronic component is electrically connected to the first circuit layer through a plurality of conductive bumps.

[0015] The present invention further provides a method for manufacturing an electronic package, comprising: providing a carrier and a plurality of core-layer-free circuit structures, wherein the carrier has a first surface and a second surface opposite to each other, wherein each of the circuit structures comprises at least one first insulating layer and a first circuit layer formed on the first insulating layer; laminating the circuit structures on the first surface and the second surface of the carrier respectively, wherein the circuit structure is laminating on the carrier through a peeling layer, and the first circuit layer is embedded in the peeling layer; arranging an electronic component on each of the circuit structures; forming a build-up structure on each of the circuit structures, and the build-up structure comprises at least one second insulating layer formed on the first insulating layer to cover the electronic component and a second circuit layer formed on the second insulating layer, so that the second circuit layer is electrically connected to the first circuit layer, wherein the material forming the second insulating layer is Ajinomoto build-up film (Ajinomoto build-up film) The first insulating layer is formed of a material different from that of the first insulating layer; and the carrier is removed to obtain a plurality of electronic packages, wherein the electronic components are embedded in the second insulating layer of the build-up structure and are electrically connected to the first circuit layer or the second circuit layer.

[0016] In the aforementioned manufacturing method, the electronic component is electrically connected to the first circuit layer through a plurality of conductive bumps.

[0017] As can be seen from the above, the electronic package and its packaging substrate and manufacturing method of the present invention mainly press the circuit structure on the opposite sides of the carrier at the same time to offset the warping caused by the stress in the first insulating layer, so that the outermost first insulating layer of the circuit structure remains flat. Therefore, in the subsequent process, it can ensure that the second circuit layer or electronic component is effectively aligned and connected to the first circuit layer, so as to improve the yield of the packaging substrate or electronic package.

[0018] Furthermore, the carrier is pressed into the peeling layer, which can effectively prevent the carrier from infiltrating chemicals, copper foil floating, copper foil wrinkling or other problems during the process.

[0019] In addition, since the warping of the first insulating layer of the circuit structure on opposite sides of the carrier can offset each other, compared with the prior art, the first circuit layer of the circuit structure will not be broken, which is conducive to meeting the requirements of electrical reliability and process yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A cross-sectional view of a conventional packaging substrate.

[0021] FIG. 2A to FIG. 2D It is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate of the present invention.

[0022] Figure 2E for Figure 2D A cross-sectional schematic diagram of the subsequent process.

[0023] FIG. 3A to FIG. 3D It is a cross-sectional schematic diagram of the method for manufacturing the electronic package of the present invention.

[0024] Figure 3E for Figure 3D A cross-sectional schematic diagram of the subsequent process.

[0025] Figure 4 for Figure 3D A cross-sectional schematic diagram of another embodiment of the present invention.

[0026] The reference numerals are as follows:

[0027] 1,2 Package substrate

[0028] 11 Dielectric layer

[0029] 12 Circuit layer

[0030] 20 Metal Layer

[0031] 21 Line structure

[0032] 21a First side

[0033] 21b Second side

[0034] 210 First insulation layer

[0035] 211 First circuit layer

[0036] 22,23 Layered Structure

[0037] 220,230 Second insulation layer

[0038] 221,231 Second circuit layer

[0039] 3,4 Electronic packaging

[0040] 30 Electronic components

[0041] 30a Active surface

[0042] 30b Non-active surface

[0043] 300 Electrode Pads

[0044] 31 Conductive bump

[0045] 40 Paste layer

[0046] 9 Bearing

[0047] 9a First surface

[0048] 9b Second surface

[0049] 92 peeling layer

[0050] F Warping direction

[0051] S Cutting path DETAILED DESCRIPTION

[0052] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0053] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be produced by the present invention, should still fall within the scope of the technical contents disclosed in the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0054] FIG. 2A to FIG. 2D It is a cross-sectional schematic diagram of a method for manufacturing a package substrate 2 of the present invention.

[0055] like Figure 2A As shown, a carrier 9 and a plurality of circuit structures 21 are provided, wherein the carrier 9 has a first surface 9a and a second surface 9b opposite to each other.

[0056] In this embodiment, the carrier 9 is a temporary carrier plate, and the plate body thereof can be a metal plate such as copper foil or other plate materials.

[0057] Furthermore, each of the circuit structures 21 is coreless, defines a first side 21a and a second side 21b opposite to each other, and includes at least one first insulating layer 210 and a first circuit layer 211 formed on the first insulating layer 210. For example, the first insulating layer 210 is a dielectric layer, such as polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials.

[0058] In addition, the circuit structure 21 is manufactured on a metal layer 20 of a carrier board (such as a copper foil substrate) having a metal layer 20, so that the metal layer 20 is combined with the first side 21a of the circuit structure 21, and then the carrier board is removed to obtain the circuit structure 21 having the metal layer 20. For example, the first circuit layer 211 is manufactured by electroplating metal (such as copper material) or other methods using a build-up process.

[0059] It should be understood that, by using the build-up method, the plurality of circuit structures 21 can add multiple layers of the first insulating layer 210 as required to manufacture multiple layers of first circuit layers 211 .

[0060] In addition, if the circuit structure 21 is made on the carrier board, after removing the carrier board, the circuit structure 21 will be warped due to uneven force distribution, as shown in the warping direction F of the left and right sides, making the circuit structure 21 look like a smiling face or a crying face.

[0061] like Figure 2B As shown, a plurality of circuit structures 21 are symmetrically formed on the first surface 9 a and the second surface 9 b of the carrier 9 by lamination, and the second side 21 b of the circuit structure 21 is lamination-bonded to the carrier 9 via a release layer 92 .

[0062] In this embodiment, the peeling layer 92 is a dielectric layer, and the peeling layer 92 covers the first circuit layer 211 of the second side 21b, so that the first circuit layer 211 of the second side 21b is embedded in the peeling layer 92, and the metal layer 20 of the first side 21a of the circuit structure 21 faces outward.

[0063] like Figure 2C As shown, a build-up structure 22 is formed on the first side 21 a of each circuit structure 21 .

[0064] In this embodiment, the build-up structure 22 includes at least one second insulating layer 220 formed on the first insulating layer 210 and a second circuit layer 221 formed on the second insulating layer 220, so that the second circuit layer 221 is electrically connected to the first circuit layer 211. For example, the build-up structure 22 is manufactured by a build-up method.

[0065] Furthermore, the material forming the second insulating layer 220 is different from the material forming the first insulating layer 210. For example, the material forming the second insulating layer 220 is Ajinomoto build-up film (ABF), and the material forming the first insulating layer 210 is prepreg (PP).

[0066] In addition, the metal layer 20 may be removed first, and then the build-up structure 22 may be fabricated. Alternatively, the metal layer 20 may be used to fabricate the second circuit layer 221 .

[0067] like Figure 2D As shown, along Figure 2C The cutting path S shown is used for performing a singulation process and removing the carrier 9 to obtain a plurality of package substrates 2 , which expose the second side 21 b of the circuit structure 21 .

[0068] In this embodiment, another build-up layer structure 23 may be formed on the second side 21b of the circuit structure 21 by using a build-up layer method, such as Figure 2E For example, the build-up structure 23 includes at least one second insulating layer 230 formed on the first insulating layer 210 and a second circuit layer 231 formed on the second insulating layer 230 , so that the second circuit layer 231 is electrically connected to the first circuit layer 211 .

[0069] Furthermore, the material forming the second insulating layer 230 is different from the material forming the first insulating layer 210. For example, the material forming the second insulating layer 230 is Ajinomoto build-up film (ABF), while the material forming the first insulating layer 210 is prepreg (PP). It should be understood that the structures of the multiple build-up structures 22 and 23 are substantially the same.

[0070] Therefore, the manufacturing method of the present invention simultaneously presses multiple circuit structures 21 on opposite sides of the carrier 9 to offset the warping caused by the stress in the first insulating layer 210, so that the outermost first insulating layer 210 of the circuit structure 21 remains flat. Therefore, in the subsequent process of the build-up structure 22, it can ensure that the second circuit layer 221 is effectively aligned and connected to the first circuit layer 211, so as to improve the yield of the packaging substrate 2.

[0071] Furthermore, the carrier 9 is pressed into the peeling layer 92 (ie, the intermediate layer covers the copper foil), so as to effectively prevent the carrier 9 from infiltrating chemicals, copper foil floating, copper foil wrinkling or other problems during the process.

[0072] In addition, since the warping of the first insulating layer 210 of the circuit structure 21 on opposite sides of the carrier 9 can offset each other, the first circuit layer 211 of the circuit structure 21 will not be broken, which is conducive to meeting the requirements of electrical reliability and process yield.

[0073] FIG. 3A to FIG. 3D Schematic cross-sectional view of the manufacturing method of the electronic package 3 of the present invention. In this embodiment, the manufacturing method of the package substrate 2 is used, so the same parts will not be repeated below.

[0074] like Figure 3AAs shown, continue as Figure 2B Process shown.

[0075] like Figure 3B As shown, the metal layer 20 is removed, and then at least one electronic component 30 is disposed on the first side 21 a of the plurality of circuit structures 21 , so that the electronic component 30 is electrically connected to the first circuit layer 211 .

[0076] In the present embodiment, the electronic component 30 is an active component, a passive component or a combination of the two, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor or an inductor. For example, if the electronic component 30 is a semiconductor chip, it has an active surface 30a and an inactive surface 30b opposite to each other, and the active surface 30a has a plurality of electrode pads 300, which are electrically connected to the first circuit layer 211 through a plurality of conductive bumps 31 with the active surface 30a facing downward (such as a flip chip method); or, the electronic component 30 can also be electrically connected to the first circuit layer 211 by a plurality of welding wires (not shown) in a wire bonding manner; or, the electronic component 30 can directly contact the first circuit layer 211. However, the method for electrically connecting the electronic component 30 to the first circuit layer 211 is not limited to the above.

[0077] like Figure 3C As shown, a build-up structure 22 is formed on the first side 21 a of each circuit structure 21 , so that the electronic component 30 is embedded in the build-up structure 22 .

[0078] In this embodiment, the build-up structure 22 covers the electronic component 30 with one of the second insulating layers 220 .

[0079] like Figure 3D As shown, along Figure 3C The cutting path S shown is used for performing a singulation process and removing the carrier 9 to obtain a plurality of electronic packages 3 including package substrates 2 and electronic components 30 .

[0080] In this embodiment, another build-up layer structure 23 may be formed on the second side 21b of the circuit structure 21 by using a build-up layer method, such as Figure 3E shown.

[0081] In another embodiment, the electronic component 30 may be embedded in a manner such that the active surface 30a faces upward. Figure 4 The electronic package 4 shown is such that the electronic component 30 is bonded to the first side 21 a of the circuit structure 21 with its inactive surface 30 b through the adhesive layer 40 , so that the second circuit layer 221 of the build-up structure 22 is electrically connected to the electrode pad 300 of the electronic component 30 .

[0082] Therefore, the manufacturing method of the present invention simultaneously presses multiple circuit structures 21 on opposite sides of the carrier 9 to offset the warping caused by the stress in the first insulating layer 210, so that the outermost first insulating layer 210 of the circuit structure 21 remains flat. Therefore, when the electronic component 30 is subsequently set, it can ensure that the conductive bump 31 is effectively aligned and connected to the first circuit layer 211, so as to improve the yield of the electronic package 3.

[0083] Furthermore, even if the embedding method of the electronic component 30 adopts the method in which the active surface 30a faces upward, such as Figure 4 As shown, the electronic component 30 can still be evenly disposed on the first side 21 a of the circuit structure 21 , so that the second circuit layer 221 of the build-up structure 22 can be effectively aligned with the electrode pad 300 connected to the electronic component 30 , thereby improving the yield of the electronic package 4 .

[0084] In addition, the carrier 9 is pressed into the peeling layer 92 (ie, the intermediate layer covers the copper foil) to effectively prevent the carrier 9 from infiltrating chemicals, copper foil floating, copper foil wrinkling or other problems during the process.

[0085] In addition, since the warping of the first insulating layer 210 of the circuit structure 21 on opposite sides of the carrier 9 can offset each other, the first circuit layer 211 of the circuit structure 21 will not be broken, which is conducive to meeting the requirements of electrical reliability and process yield.

[0086] The present invention also provides a package substrate 2 , comprising: a core-less circuit structure 21 having a first side 21 a and a second side 21 b opposite to each other, and build-up layer structures 22 , 23 disposed on the circuit structure 21 .

[0087] The circuit structure 21 includes at least a first insulating layer 210 and a first circuit layer 211 disposed on the first insulating layer 210 .

[0088] The build-up structures 22, 23 are disposed on the circuit structure 21, wherein the build-up structures 22, 23 include at least one second insulating layer 220, 230 formed on the first insulating layer 210 and a second circuit layer 221, 231 disposed on the second insulating layer 220, 230 and electrically connected to the first circuit layer 211, and the material forming the second insulating layer 220, 230 is Ajinomoto build-up film, which is different from the material forming the first insulating layer 210.

[0089] In one embodiment, the build-up structures 22 , 23 are disposed on the first side 21 a and / or the second side 21 b .

[0090] The present invention further provides an electronic package 3 , 4 , comprising: a package substrate 2 and at least one electronic component 30 .

[0091] The electronic component 30 is disposed on the circuit structure 21 and embedded in the second insulating layer 220 of the build-up structure 22 , so that the electronic component 30 is electrically connected to the first circuit layer 210 or the second circuit layer 220 .

[0092] In one embodiment, the electronic component 30 is electrically connected to the first circuit layer 210 via a plurality of conductive bumps 31 .

[0093] In summary, the electronic package and its packaging substrate and manufacturing method of the present invention simultaneously press the circuit structure on the opposite sides of the carrier to offset the warping caused by the stress in the first insulating layer, so that the outermost first insulating layer of the circuit structure remains flat. Therefore, in the subsequent process, it can ensure that the second circuit layer or electronic component is effectively aligned and connected to the first circuit layer, so as to improve the yield of the packaging substrate or electronic package.

[0094] Furthermore, the carrier is pressed into the peeling layer, which can effectively prevent the carrier from infiltrating chemicals, copper foil floating, copper foil wrinkling or other problems during the process.

[0095] In addition, since the warping of the first insulating layer of the circuit structure on the two opposite sides of the carrier can offset each other, the first circuit layer of the circuit structure will not be broken, which is conducive to meeting the requirements of electrical reliability and process yield.

[0096] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Those skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. A method for manufacturing a packaging substrate, comprising: A carrier and a plurality of core-less circuit structures are provided, wherein the carrier has a first surface and a second surface opposite to each other, and each of the circuit structures comprises at least a first insulating layer and a first circuit layer formed on the first insulating layer, and wherein the circuit structure has a first side and a second side opposite to each other, and a metal layer is combined on the first side of the circuit structure; The circuit structure is pressed on the first surface and the second surface of the carrier respectively, wherein the circuit structure is pressed on the carrier through a peeling layer, and the first circuit layer is embedded in the peeling layer; forming a build-up structure on each of the circuit structures, wherein the build-up structure comprises at least one second insulating layer formed on the first insulating layer and a second circuit layer formed on the second insulating layer, so that the second circuit layer is electrically connected to the first circuit layer, wherein the material forming the second insulating layer is a Ajinomoto build-up film, which is different from the material forming the first insulating layer, and wherein the second circuit layer is made of the metal layer; and The carrier is removed to obtain a plurality of the packaging substrates.

2. The method for manufacturing a packaging substrate according to claim 1, wherein: The circuit structure is combined on the carrier with its second side.

3. The method for manufacturing a packaging substrate according to claim 1, wherein: The method further includes forming another build-up layer structure on the second side after removing the carrier.

4. A method for manufacturing an electronic package, comprising: A carrier and a plurality of core-less circuit structures are provided, wherein the carrier has a first surface and a second surface opposite to each other, and each of the circuit structures comprises at least a first insulating layer and a first circuit layer formed on the first insulating layer, and wherein the circuit structure has a first side and a second side opposite to each other, and a metal layer is combined on the first side of the circuit structure; The circuit structure is pressed on the first surface and the second surface of the carrier respectively, wherein the circuit structure is pressed on the carrier through a peeling layer, and the first circuit layer is embedded in the peeling layer; removing the metal layer; Disposing an electronic component on the first side of each of the circuit structures; Forming a build-up layer structure on each of the circuit structures, wherein the build-up layer structure includes at least one second insulating layer formed on the first insulating layer to cover the electronic component and a second circuit layer formed on the second insulating layer, and the second circuit layer is electrically connected to the first circuit layer, wherein the material forming the second insulating layer is a Mikoto build-up layer film, which is different from the material forming the first insulating layer; and The carrier is removed to obtain a plurality of electronic packages, wherein the electronic components are embedded in the second insulating layer of the build-up structure and are electrically connected to the first circuit layer or the second circuit layer.

5. The method for manufacturing an electronic package as claimed in claim 4, wherein: The electronic element is electrically connected to the first circuit layer through a plurality of conductive bumps.

Images