Silicon carbide MOSFET with shielding region and its manufacturing method

Abstract

The present invention discloses a silicon carbide MOSFET with a shielding region and a manufacturing method thereof, the method comprising: forming a lower trench in a silicon carbide epitaxial layer; forming a lower trench filling region in the lower trench by a variable doping epitaxial process, forming a well region on the epitaxial layer; forming a source region in the well region; forming an upper trench in the silicon carbide epitaxial layer; forming a gate dielectric layer and a gate electrode in the upper trench; forming an isolation dielectric layer on the gate electrode; forming a source electrode on and at both ends of the isolation dielectric layer, and forming a drain electrode at the bottom of the substrate. The present invention skillfully combines the variable doping epitaxial process with the etching process, and forms a shielding region at the bottom of the upper trench without using an ion implantation process, which can not only achieve effective protection of the gate dielectric and improve the reliability of the device, but also avoid lattice damage caused by the two-step ion implantation process, thereby further improving the long-term reliability of the device.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a silicon carbide MOSFET with a shielding region and a manufacturing method thereof. Background Art

[0002] The development of the power electronics industry has put forward increasing requirements for the voltage resistance and current capacity of switching devices. The manufacturing process of traditional silicon material devices is mature, but the performance of the material itself limits the application of silicon devices in extreme working environments. Silicon carbide (SiC) material has become one of the most important semiconductor materials for making high-power devices that can adapt to extreme environments due to its higher thermal conductivity, larger bandgap width, and higher critical breakdown electric field strength.

[0003] Among SiC power devices, metal oxide semiconductor field effect transistors (MOSFETs) are widely used due to their advantages such as simple gate drive and fast switching speed. Due to the parasitic junction field effect transistor (JFET) structure and the difficulty in improving channel mobility, planar gate SiC MOSFET devices have large on-resistance and low integration. Trench gate SiC MOSFET devices form channels on the sidewalls of the trench, which not only improves the channel mobility, but also eliminates the JFET effect, significantly reducing the on-resistance of the device.

[0004] However, there are still several problems in the actual production of trench SiC MOSFET devices. One is that in the off state, the gate dielectric layer at the corner of the trench needs to withstand a large electric field strength, which affects the reliability of the device. Second, compared with planar SiC MOSFET devices, the process of trench SiC MOSFET devices is more complicated. In order to solve the problem of excessive gate dielectric electric field, the current common solution is to form a shielding area at the bottom of the trench through ion implantation, such as Figure 2 This will not only cause serious lattice damage to the device, thus damaging long-term reliability, but also cause lateral expansion, significantly affecting the conduction characteristics of the device. Summary of the invention

[0005] In view of the above-mentioned deficiencies of the trench SiC MOSFET device, the present invention provides a silicon carbide MOSFET with a shielding region and a method for manufacturing the same.

[0006] A method for manufacturing a silicon carbide MOSFET with a shielding region comprises the following steps:

[0007] Step 1, forming a silicon carbide epitaxial layer on a silicon carbide substrate;

[0008] Step 2, etching the silicon carbide epitaxial layer to form a lower trench; the width of the lower trench is in the range of 0.5µm to 3µm, the depth of the lower trench is in the range of 0.5µm to 3µm, and the spacing between adjacent lower trenches is in the range of 1.5µm to 5.0µm;

[0009] Step 3, forming a lower trench filling region in the lower trench by a variable doping epitaxial process, and forming a well region on the lower trench filling region and the silicon carbide epitaxial layer, wherein the concentration of the lower trench filling region is 2 to 400 times the concentration of the well region;

[0010] Step 4, forming a source region in the well region;

[0011] Step 5, etching to form an upper trench penetrating the source region, the well region and extending into the lower trench filling region, the lower trench filling region at the bottom of the upper trench being used as a shielding region; the width of the upper trench is greater than the width of the lower trench, the difference between the two is not less than 0.1 μm, the depth of the upper trench is greater than the depth of the well region, the difference between the two is not less than 0.1 μm, and the depth of the shielding region ranges from 0.2 μm to 2.0 μm;

[0012] Step 6: forming a gate dielectric layer at the bottom and sidewalls of the upper trench, and forming a gate electrode wrapped by the gate dielectric layer;

[0013] Step 7: forming an isolation dielectric layer on the gate dielectric layer, the gate electrode, and a portion of the source region;

[0014] Step 8: Form source electrodes on both sides and on the isolation dielectric layer, and form a drain electrode at the bottom of the silicon carbide substrate.

[0015] The present invention also discloses a silicon carbide MOSFET with a shielding region, which is manufactured by the above-mentioned method for manufacturing the silicon carbide MOSFET with a shielding region, comprising:

[0016] drain electrode;

[0017] a silicon carbide substrate located on the drain electrode;

[0018] a silicon carbide epitaxial layer located on the silicon carbide substrate;

[0019] a shielding region located within the silicon carbide epitaxial layer;

[0020] an upper trench located above the shielding area;

[0021] a gate dielectric located on the sidewall and bottom of the upper trench;

[0022] A gate electrode located in the upper trench and surrounded on three sides by the gate dielectric;

[0023] Well regions located in the silicon carbide epitaxial layer and on both sides of the upper trench;

[0024] a source region located in the well region;

[0025] an isolation dielectric layer located on the silicon carbide epitaxial layer and completely covering the gate electrode;

[0026] The source electrodes are located on both sides and on the isolation dielectric layer.

[0027] The present invention adopts the above technical solution and has the following beneficial effects:

[0028] (1) The present invention adopts a process scheme of etching + variable doping epitaxy + etching. The first etching is used to form the lower trench. The variable doping epitaxy process is used to form a lower trench filling area with a higher concentration that completely fills the lower trench and a well area with a lower concentration located above the lower trench. The second etching is used to form a shielding area and a gate structure. By cleverly combining the variable doping epitaxy process with the etching process, the concentration distribution of the shielding area can be accurately controlled by the epitaxy process, and the size of the shielding area can be accurately controlled by adjusting the depth of the upper trench and the lower trench, leaving sufficient process margin for actual production.

[0029] (2) The present invention forms a well region and a shielding region by combining a variable doping epitaxial process with an etching process, which can not only meet the threshold voltage requirements for the well region process parameters, but also set a shielding region with significant protection effect at the bottom of the gate dielectric, thereby effectively reducing the peak electric field borne by the gate dielectric layer without introducing lattice damage, thereby improving device reliability. Forming a shielding region through this scheme can avoid the lateral expansion phenomenon caused by the ion implantation process, thereby minimizing the impact of the shielding region on the conduction characteristics. The manufacturing method provided by the present invention is simple, and by avoiding the expensive ion implantation process as much as possible, the process cost is greatly reduced, and it can be used for the commercial production of trench silicon carbide MOSFET devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a process flow chart of a method for manufacturing a silicon carbide MOSFET with a shielding region described in Example 1.

[0031] Figure 2 The schematic diagram of the structure of an existing silicon carbide MOSFET having a shielding area at the bottom of a trench.

[0032] Figure 3~Figure 11 This is a specific flow chart of a method for manufacturing a silicon carbide MOSFET with a shielding region described in Example 1.

[0033] Fig.12 This is a process flow chart of a method for manufacturing a silicon carbide MOSFET with a shielding region described in Example 2.

[0034] Figure 13~Figure 21This is a specific flow chart of a method for manufacturing a silicon carbide MOSFET with a shielding region described in Example 2.

[0035] Fig. 22 This is a process flow chart of a method for manufacturing a silicon carbide MOSFET with a shielding region described in Example 3.

[0036] Figure 23~Figure 31 A specific flow chart of a method for manufacturing a silicon carbide MOSFET with a shielding region as described in Example 3

[0037] Explanation of the accompanying drawings: 1. drain electrode; 2. silicon carbide substrate; 3. silicon carbide epitaxial layer; 4. lower trench; 4-1. lower trench on the left; 4-2. lower trench on the right; 5. shielding area; 5-1. lower trench filling area; 6. well area; 7. source area; 8. upper trench; 9. gate electrode; 9-1. first gate electrode; 9-2. second gate electrode; 10. gate dielectric layer; 11. isolation dielectric layer; 12. source electrode; 13. left shielding area; 13-1. lower trench filling area on the left; 14. right shielding area; 14-1. lower trench filling area on the right. DETAILED DESCRIPTION

[0038] The present invention is further described below in conjunction with examples. The examples are only used to illustrate the present invention and do not constitute a limitation on the scope of the claims. Other alternative means that can be thought of by those skilled in the art are all within the scope of the claims of the present invention.

[0039] In addition, in the description of the present invention, it should be noted that the terms "central", "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. Example 1

[0040] As attached Figure 1 As shown, a method for manufacturing a silicon carbide MOSFET with a shielding region in this embodiment is as follows: Figure 3~Figure 11 The specific process steps are described, including the following steps:

[0041] Step 1: forming a silicon carbide epitaxial layer 3 on a silicon carbide substrate 2; Figure 3 , Figure 4As shown, a silicon carbide epitaxial layer 3 is formed on a silicon carbide substrate 2 by an epitaxial process, and both the silicon carbide substrate 2 and the silicon carbide epitaxial layer 3 are of the first conductivity type; the thickness of the silicon carbide epitaxial layer 3 ranges from 5µm to 100µm, and the doping concentration of the silicon carbide epitaxial layer 3 is 1e15cm -3 ~ 1e17cm -3 The material of the silicon carbide substrate 2 can be 3C-SiC, 4H-SiC, 6H-SiC or 15R-SiC. The thickness of the silicon carbide substrate 2 ranges from 10µm to 1000µm, and the doping concentration is 1e19cm -3 ~5e20cm -3 The material of the silicon carbide epitaxial layer 3 may be 3C-SiC, 4H-SiC, 6H-SiC or 15R-SiC.

[0042] Step 2: etching the silicon carbide epitaxial layer 3 to form a lower trench 4; Figure 5 As shown, the silicon carbide epitaxial layer 3 is etched by a reactive ion etching process or an inductively coupled plasma etching process through a photolithography process, a chemical vapor deposition process and an etching process. The etching gas can be one or more combinations of gases such as SF6, HBr, Cl2, O2, Ar, etc., to remove part of the silicon carbide epitaxial layer 3 to form a lower groove 4. The width of the lower groove 4 ranges from 0.5µm to 3µm, the depth of the lower groove 4 ranges from 0.5µm to 3µm, and the spacing between adjacent lower grooves 4 ranges from 1.5µm to 5.0µm. The etching angle of the lower groove is not less than 85 degrees.

[0043] Step 3, through the variable doping epitaxial process, a lower trench filling region 5-1 with a relatively high concentration is formed in the lower trench 4, and a well region 6 with a relatively low concentration is formed on the lower trench filling region 5-1 and the silicon carbide epitaxial layer 3, wherein the concentration of the lower trench filling region is 2 to 400 times that of the well region; Figure 6 As shown, a lower trench filling region 5-1 and a well region 6 are formed by a variable doping epitaxial process, wherein the lower trench filling region 5-1 is located in the lower trench 4, the well region 6 is located on the lower trench filling region 5-1 and the silicon carbide epitaxial layer 3, the conductivity type of the lower trench filling region 5-1 and the well region 6 is the second conductivity type, the depth range of the well region 6 is 0.5µm~2.5µm, and the doping concentration of the well region 6 is 5e16cm -3 ~5e17cm -3 , the doping concentration of the lower trench filling region 5-1 is 1e18cm -3 ~2e19cm -3 The variable doping epitaxial growth is achieved by controlling parameters such as gas flow rate and pressure. The doping concentration of the lower trench filling area 5-1 is relatively high, and the doping concentration of the well area 6 is relatively low. After step 3 is completed, the lower trench is filled.

[0044] Step 4: forming a source region 7 in the well region 6; Figure 7 As shown, a source region 7 is formed in the well region 6 by photolithography, chemical vapor deposition and ion implantation. The source region 7 is of the first conductivity type, has a depth range of 0.2µm to 0.5µm, and a doping concentration of 1e19cm -3 ~1e20cm -3 , the difference in depth between the source region and the well region is 0.2µm~1.0µm. The ion implantation process steps are as follows: a patterned mask layer is prepared on the surface of the well region 6, then impurities are implanted, and after removing the mask, annealing is performed at 1400℃~2200℃ for 2min~30min.

[0045] Step 5, etching to form an upper trench 8 penetrating the source region 7, the well region 6 and extending into the lower trench filling region 5-1, the lower trench filling region 5-1 at the bottom of the upper trench 8 is used as a shielding region 5, and the depth of the shielding region 5 ranges from 0.2μm to 2.0μm; Figure 8 As shown, the well region 6 and the silicon carbide epitaxial layer 3 are etched by reactive ion etching or inductively coupled plasma etching through photolithography, chemical vapor deposition and etching processes to form an upper groove 8. The etching gas can be one or more combinations of gases such as SF6, HBr, Cl2, O2, Ar, etc. The width of the upper groove 8 is greater than the width of the lower groove 4, and the difference between the two is not less than 0.1μm. The depth of the upper groove 8 is greater than the depth of the well region 6, and the difference between the two is not less than 0.1μm. After the upper groove 8 is formed, a high-temperature annealing process can be used to passivate the groove. The gas used can be one or more combinations of gases such as SiH4, H2, Ar, etc., and the annealing temperature is 1400℃~1800℃. The width of the upper groove ranges from 0.6µm to 4µm, the depth ranges from 0.7µm to 3µm, and the spacing between adjacent upper grooves ranges from 1.0µm to 4.5µm. The etching angle of the upper groove is not less than 85 degrees. The lower trench and the upper trench may be distributed continuously or discontinuously in the depth direction of the device.

[0046] Step 6: forming a gate dielectric layer 10 at the bottom and sidewall of the upper trench 8, and forming a gate electrode 9 wrapped by the gate dielectric layer 10; Fig. 9 As shown, a gate dielectric layer 10 is formed in the upper groove 8 by thermal oxidation or oxidation process and chemical vapor deposition process. The thickness of the gate dielectric layer ranges from 30nm to 100nm, and the material of the gate dielectric layer 10 is SiO2, Si3N4 or Al2O3. Then, the quality of the gate dielectric layer 10 is improved by a high-temperature annealing process. The annealing gas can be one or more of NO, N2O, H2, NH3 and the like. The annealing temperature is 900°C to 1300°C. Subsequently, a gate electrode 9 is formed by a chemical vapor deposition process. The material of the gate electrode 9 is polycrystalline silicon. Low-resistance treatment is performed and the polycrystalline silicon surface is flattened by a CMP process. The gate electrode material can be polycrystalline silicon, amorphous silicon or amorphous silicon, and the doping impurities can be Al, N, P, B and other impurities.

[0047] Step 7: forming an isolation dielectric layer 11 on the gate dielectric layer 10, the gate electrode 9, and a portion of the source region 7; Fig.10 As shown, an isolation dielectric layer 11 is formed by chemical vapor deposition, photolithography and etching processes. The material of the isolation dielectric layer 11 is silicon nitride with a thickness ranging from 1µm to 10µm to form a source window. In other embodiments of the present invention, the material of the isolation dielectric layer 11 is silicon dioxide, or nitride, or a composite of silicon dioxide and nitride.

[0048] Step 8: forming a source electrode 12 on both sides and on the isolation dielectric layer 11, and forming a drain electrode 1 at the bottom of the silicon carbide substrate 2; Fig.11 As shown, metal is evaporated through the source window formed by S7, and the metal is selected from Ti / Al alloy, and then annealed at 300°C~1100°C to form a source ohmic contact. A drain ohmic contact is formed on the bottom layer of the silicon carbide substrate 2, a source electrode 12 is formed on the surface of the source ohmic contact layer, and a drain electrode 1 is formed on the surface of the drain ohmic contact layer. In other embodiments of the present invention, the source electrode 12 and the drain electrode 1 are formed into a metal layer by evaporation, sputtering or electroplating, and then annealed at 300°C~1100°C to complete the electrode preparation. The metal can be one or more materials such as Al, Ti, Ag, Ni, Pt, etc.

[0049] In this embodiment, the first conductivity type is N type or P type, the second conductivity type is P type or N type, the doping ion type of the first conductivity type can be one of nitrogen ions, phosphorus ions, and arsenic ions, and the doping ion type of the second conductivity type can be one of aluminum ions and boron ions.

[0050] like Fig.11 As shown, a silicon carbide MOSFET with a shielding region in this embodiment includes:

[0051] Drain electrode 1;

[0052] a silicon carbide substrate 2 located on the drain electrode 1;

[0053] A silicon carbide epitaxial layer 3 located on the silicon carbide substrate 2;

[0054] A shielding region 5 located in the silicon carbide epitaxial layer 3;

[0055] an upper groove 8 located above the shielding area 5;

[0056] A gate dielectric 10 located on the sidewall and bottom of the upper trench 8;

[0057] A gate electrode 9 located in the upper trench 8 and surrounded on three sides by the gate dielectric 10;

[0058] Well regions 6 located in the silicon carbide epitaxial layer 3 and on both sides of the upper trench 8;

[0059] a source region 7 located in the well region 6;

[0060] An isolation dielectric layer 11 located on the silicon carbide epitaxial layer 3 and completely covering the gate electrode 10;

[0061] The source electrodes 12 are located on both sides and on the isolation dielectric layer 11 . Example 2

[0062] As attached Fig.12 As shown, a method for manufacturing a silicon carbide MOSFET with a shielding region in this embodiment is as follows: Figure 13~Figure 21 The specific process steps are described, including the following steps:

[0063] Step 1: Fig.13 , Fig.14 As shown, a silicon carbide epitaxial layer 3 is formed on a silicon carbide substrate 2; the specific steps refer to step 1 of embodiment 1;

[0064] Step 2: Fig.15 As shown, a lower trench 4 is formed by etching on the silicon carbide epitaxial layer 3; the specific steps refer to step 2 of embodiment 1.

[0065] Step 3: Fig.16 As shown, a lower trench filling region 5-1 is formed in the lower trench 4, and a well region 6 is formed on the lower trench filling region 5-1 and the silicon carbide epitaxial layer 3; the specific steps refer to step 3 of embodiment 1.

[0066] Step 4: Fig.17 As shown, a source region 7 is formed in the well region 6; the specific steps refer to step 4 of embodiment 1.

[0067] Step 5: Fig.18 As shown, an upper trench 8 is formed by etching 7 which penetrates the source region 7, the well region 6 and extends into the lower trench filling region 5-1. The lower trench filling region 5-1 at the bottom of the upper trench 8 serves as a shielding region 5. The depth range of the shielding region 5 is 0.2μm~2.0μm. For specific steps, refer to step 5 of Example 1.

[0068] Step 6: forming a gate dielectric layer 10 at the bottom and sidewall of the upper trench 8, and forming a first gate electrode 9-1 and a second gate electrode 9-2 wrapped by the gate dielectric layer 10; Fig.19As shown, a gate dielectric layer 10 is formed in the upper groove 8 by oxidation process and chemical vapor deposition process, and the material of the gate dielectric layer 10 is SiO2. Then, the quality of the gate dielectric layer 10 is improved by high-temperature annealing process, and the annealing gas can be one or more gases such as NO, N2O, H2, NH3, etc., and the annealing temperature is 900°C~1300°C. Subsequently, a first gate electrode 9-1 and a second gate electrode 9-2 are formed by chemical vapor deposition process, photolithography process and etching process, and the material of the first gate electrode 9-1 and the second gate electrode 9-2 is polysilicon, and low resistance treatment is performed and the polysilicon surface is flattened by CMP process.

[0069] Step 7, forming an isolation dielectric layer 11 on the gate dielectric layer 10, the first gate electrode 9-1, the second gate electrode 9-2, and a portion of the source region 7; Fig. 20 As shown, an isolation dielectric layer 11 is formed by chemical vapor deposition, photolithography and etching processes. The material of the isolation dielectric layer 11 is silicon nitride with a thickness ranging from 1µm to 10µm to form a source window;

[0070] Step 8: Fig.21 As shown, source electrodes 12 are formed on both sides and on the isolation dielectric layer 11, and a drain electrode 1 is formed at the bottom of the silicon carbide substrate 2; the specific steps refer to step 8 of embodiment 1.

[0071] Compared with Embodiment 1, this embodiment adopts a split gate structure, namely, a first gate electrode 9-1 and a second gate electrode 9-2 are wrapped on three sides by a gate dielectric layer 10; the split gate structure can effectively reduce the gate capacitance of the device, thereby reducing switching losses. Example 3

[0072] As attached Fig. 22 As shown, a method for manufacturing a silicon carbide MOSFET with a shielding region in this embodiment is as follows: Figure 23~Figure 31 The specific process steps are described, including the following steps:

[0073] Step 1: Fig.23 , Fig.24 As shown, a silicon carbide epitaxial layer 3 is formed on a silicon carbide substrate 2; the specific steps refer to step 1 of embodiment 1;

[0074] Step 2, etching the silicon carbide epitaxial layer 3 to form a left lower trench 4-1 and a right lower trench 4-2; Fig.25As shown, the silicon carbide epitaxial layer 3 is inductively coupled plasma etched by photolithography, chemical vapor deposition and etching processes. The etching gas can be one or more combinations of gases such as SF6, HBr, Cl2, O2, Ar, etc., to remove part of the silicon carbide epitaxial layer 3 to form a left lower groove 4-1 and a right lower groove 4-2. The width of the left lower groove 4-1 and the right lower groove 4-2 ranges from 0.2µm to 1µm, the depth of the left lower groove 4-1 and the right lower groove 4-2 ranges from 0.5µm to 3µm, and the spacing between the left lower groove 4-1 and the right lower groove 4-2 ranges from 0.2µm to 2.0µm; the spacing between adjacent left lower grooves 4-1 ranges from 1.5µm to 5.0µm, and the spacing between adjacent right lower grooves 4-2 ranges from 1.5µm to 5.0µm.

[0075] Step 3: By using a variable doping epitaxial process, a left lower trench filling region 13-1 is formed in the left lower trench 4-1, a right lower trench filling region 14-1 is formed in the right lower trench 4-2, and a well region 6 is formed on the left lower trench filling region 13-1, the right lower trench filling region 14-1 and the silicon carbide epitaxial layer 3; Figure 6 As shown, the left lower trench filling region 13-1, the right lower trench filling region 14-1 and the well region 6 are formed by a variable doping epitaxial process, the left lower trench filling region 13-1, the right lower trench filling region 14-1 and the well region 6 are of the second conductivity type, the depth range of the well region 6 is 0.5µm~2.5µm, and the doping concentration of the well region 6 is 5e16cm -3 ~5e17cm -3 The doping concentration of the left lower trench filling region 13-1 and the right lower trench filling region 14-1 is 1e18cm -3 ~2e19cm -3 ;

[0076] Step 4: Fig. 27 As shown, a source region 7 is formed in the well region 6; the specific steps refer to step 4 of embodiment 1.

[0077] Step 5: Fig.28 As shown, an upper trench 8 is formed by etching 7 which penetrates the source region 7 and the well region 6 and extends into the left lower trench filling region 13-1 and the right lower trench filling region 14-1. The left lower trench filling region 13-1 and the right lower trench filling region 14-1 at the bottom of the upper trench 8 serve as the left shielding region 13 and the right shielding region 14 respectively. The depth range of the left shielding region 13 and the right shielding region 14 is 0.2μm~2.0μm. For specific steps, refer to step 5 of embodiment 1.

[0078] Step 6: Fig.29As shown, a gate dielectric layer 10 is formed at the bottom and sidewall of the upper trench 8, and a gate electrode 9 wrapped by the gate dielectric layer 10 is formed; the specific steps refer to step 6 of embodiment 1.

[0079] Step 7: Fig.30 As shown, an isolation dielectric layer 11 is formed on the gate dielectric layer 10, the gate electrode 9, and a portion of the source region 7; the specific steps refer to step 7 of embodiment 1;

[0080] Step 8: Fig.31 As shown, source electrodes 12 are formed on both sides and on the isolation dielectric layer 11, and a drain electrode 1 is formed at the bottom of the silicon carbide substrate 2; the specific steps refer to step 8 of embodiment 1.

[0081] Compared with Example 1, in this embodiment, a left shielding area 13 is formed in the left lower trench 4-1, and a right shielding area 14 is formed in the right lower trench 4-2 through etching + variable doping epitaxy + etching process. Dividing the shielding area into a left shielding area and a right shielding area can reduce the influence of the shielding area on the current density and improve the forward conduction characteristics.

[0082] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A method for manufacturing a silicon carbide MOSFET with a shielding region, characterized in that: The following steps are involved: Step 1, forming a silicon carbide epitaxial layer on a silicon carbide substrate; Step 2, etching the silicon carbide epitaxial layer to form a lower trench; the width of the lower trench is in the range of 0.5µm to 3µm, the depth of the lower trench is in the range of 0.5µm to 3µm, and the spacing between adjacent lower trenches is in the range of 1.5µm to 5.0µm; Step 3, forming a lower trench filling region in the lower trench by a variable doping epitaxial process, and forming a well region on the lower trench filling region and the silicon carbide epitaxial layer, wherein the concentration of the lower trench filling region is 2 to 400 times the concentration of the well region; Step 4, forming a source region in the well region; Step 5, etching to form an upper trench penetrating the source region, the well region and extending into the lower trench filling region, the lower trench filling region at the bottom of the upper trench being used as a shielding region; the width of the upper trench is greater than the width of the lower trench, the difference between the two is not less than 0.1 μm, the depth of the upper trench is greater than the depth of the well region, the difference between the two is not less than 0.1 μm, and the depth of the shielding region ranges from 0.2 μm to 2.0 μm; Step 6: forming a gate dielectric layer at the bottom and sidewalls of the upper trench, and forming a gate electrode wrapped by the gate dielectric layer; Step 7: forming an isolation dielectric layer on the gate dielectric layer, the gate electrode, and a portion of the source region; Step 8: Form source electrodes on both sides and on the isolation dielectric layer, and form a drain electrode at the bottom of the silicon carbide substrate.

2. The method for manufacturing a silicon carbide MOSFET with a shielding region according to claim 1, characterized in that: Variable doping epitaxial growth is achieved by controlling gas flow and pressure parameters; after step 3 is completed, the lower trench is filled.

3. The method for manufacturing a silicon carbide MOSFET with a shielding region according to claim 1, characterized in that: The conductivity type of the shielding area and the well area is the second conductivity type, the depth of the well area ranges from 0.5µm to 2.5µm, and the doping concentration of the well area is 5e16cm -3 ~5e17cm -3 , the doping concentration in the shielding region is 1e18cm -3 ~2e19cm -3 .

4. The method for manufacturing a silicon carbide MOSFET with a shielding region according to claim 1, characterized in that: The source region depth ranges from 0.2µm to 0.5µm, and the doping concentration is 1e19cm -3 ~1e20cm -3 The depth difference between the source region and the well region is 0.2µm~1.0µm.

5. The method for manufacturing a silicon carbide MOSFET with a shielding region according to claim 1, characterized in that: The width of the upper groove ranges from 0.6µm to 4µm, the depth ranges from 0.7µm to 3µm, and the spacing between adjacent upper grooves ranges from 1.0µm to 4.5µm.

6. The method for manufacturing a silicon carbide MOSFET with a shielding region according to claim 1, characterized in that: The lower trench and the upper trench are distributed continuously or discontinuously in the depth direction of the device.

7. A silicon carbide MOSFET with a shielding region, manufactured by the method for manufacturing a silicon carbide MOSFET with a shielding region according to any one of claims 1 to 6, characterized in that: include: drain electrode; a silicon carbide substrate located on the drain electrode; a silicon carbide epitaxial layer located on the silicon carbide substrate; a shielding region located within the silicon carbide epitaxial layer; an upper trench located above the shielding area; a gate dielectric located on the sidewall and bottom of the upper trench; A gate electrode located in the upper trench and surrounded on three sides by the gate dielectric; Well regions located in the silicon carbide epitaxial layer and on both sides of the upper trench; a source region located in the well region; an isolation dielectric layer located on the silicon carbide epitaxial layer and completely covering the gate electrode; The source electrodes are located on both sides and on the isolation dielectric layer.

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