A high-count rate adaptive gain amplification readout circuit and use method

Abstract

The present invention relates to an adaptive gain amplification readout circuit under high counting rate and a method for using the circuit, including an integral voltage unit, a switch circuit, a switch control module and a trigger control module; the switch circuit includes a gain adjustment switch and a discharge switch connected in parallel; the integral voltage unit is used to output the obtained external detector signal as an integral voltage signal; the trigger control module generates a discharge signal and a reset signal based on the integral voltage signal, and the discharge signal acts on the discharge switch to ensure that the voltage discharge of the integral voltage signal is completed to the output baseline potential after being sampled by an external ADC; the switch control module is used to control the gain adjustment switch to the corresponding gear according to the integral voltage signal, wherein the reset signal acts on the gain adjustment switch through the switch control module to return to the high gain gear. The present invention can be widely used in the detector signal readout in nuclear physics and nuclear astrophysics.

Description

Technical Field

[0001] The invention relates to an adaptive gain amplification readout circuit under high counting rate and a use method thereof, and relates to the technical field of radiation measurement. Background Art

[0002] With the completion of HIAF (Intense Heavy Ion Accelerator Facility), radioactive beam physics will be pushed to expand to heavier nuclear regions closer to the drip line, and more abundant scientific treasures will be discovered. In order to meet the needs of cutting-edge science, a new generation of radioactive secondary beam separation line (HIAF FRagment Separator, HFRS) will be built on HIAF.

[0003] The prerequisite for conducting radioactive nuclear beam physics experiments is to reliably identify different nuclides. Due to the high-energy and high-current characteristics of HFRS, the development of beamline particle identification detectors has brought great technical challenges, requiring the realization of particle identification of Z=1-92 (input signal dynamic range 2fC~15pC), and achieving high counting rate (~1MHz) and multi-channel (~1000 channels) requirements.

[0004] Existing front-end readout ASIC chips cannot meet the requirements of large dynamic range and high counting rate at the same time. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, in view of the above problems, the purpose of the present invention is to provide an adaptive gain amplification readout circuit at high counting rate, which effectively solves the problem of low noise and large dynamic input charge signal readout at high counting rate, and can measure the detector output signal with large dynamic range and high counting rate.

[0006] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is:

[0007] In a first aspect, the present invention provides an adaptive gain amplification readout circuit at a high count rate, the amplification readout circuit comprising an integration voltage unit, a switch circuit, a switch control module and a trigger control module; the switch circuit comprises a gain adjustment switch and a discharge switch connected in parallel;

[0008] The integral voltage unit is used to output the obtained external detector signal as an integral voltage signal;

[0009] The trigger control module generates a discharge signal and a reset signal based on the integrated voltage signal, wherein the discharge signal acts on the discharge switch to ensure that the integrated voltage signal is sampled by the external ADC and the voltage is discharged to the output baseline potential;

[0010] The switch control module is used to control the gain adjustment switch to a corresponding gear position according to the integrated voltage signal, wherein the reset signal acts on the gain adjustment switch through the switch control module to return to a high gain gear position.

[0011] In some possible embodiments, the integral voltage unit includes an amplifier and a capacitor connected in parallel, the input charge of the external detector enters the integral voltage unit and is accumulated on the capacitor, and the accumulated charge generates an integral voltage signal at the output end of the amplifier through the capacitor.

[0012] In some possible embodiments, the discharge switch includes two Bleed switches connected in series, and the discharge signal controls the two Bleed switches to have two states:

[0013] In the signal integration stage, the two Bleed switches are in a disconnected maximum resistance state;

[0014] During the discharge phase, the two Bleeds are closed for discharge.

[0015] In some possible embodiments, the gain switch circuit includes three switch branches connected in parallel, wherein:

[0016] The first switch subcircuit includes a first switch, a first capacitor and a first switch connected in series;

[0017] The second switch subcircuit includes a second switch, a second capacitor and a second switch connected in series;

[0018] The third switch subcircuit includes a third switch, a third capacitor, and a third switch connected in series.

[0019] In some possible embodiments, the gear design is divided into four gears:

[0020] First gear: the first switch, the second switch, and the third switch are all disconnected, and the corresponding input charge read is 2.2fC-210fC. This gear is also a high gain gear;

[0021] Second gear: The first switch is closed, and the corresponding input charge read is 210fC-1.26pC;

[0022] The third gear: the first switch and the second switch are closed, and the corresponding input charge read is 1.26pC-6.3pC;

[0023] Fourth gear: the first switch, the second switch and the third switch are all closed, and the corresponding read input charge is 6.3pC-16.5pC.

[0024] In some possible embodiments, the trigger control module includes a threshold comparator, a monostable long delay, a monostable short delay, an RC delay unit, a first OR gate and a short delay module, the threshold voltage signal is inputted into the positive input terminal of the threshold comparator, the integrated voltage signal is inputted into the reverse input terminal of the threshold comparator, the output terminal of the threshold comparator is sequentially connected to the monostable long delay, the monostable short delay and the RC delay unit, the RC delay unit is also connected to the short delay module through the OR gate, wherein: the integrated voltage signal generates a high-level trigger signal through the monostable long delay and the monostable short delay, the high-level trigger signal and the external input reset signal form the discharge signal through the first OR gate, and the discharge signal generates a delay through the short delay module to form the reset signal.

[0025] In some possible embodiments, the switch control module includes a high-speed comparator, a first to a third latch, a delay circuit and a second OR gate, the positive and negative input terminals of the high-speed comparator are respectively connected to the integrated voltage signal and the set threshold voltage signal, the output terminal of the high-speed comparator is connected in parallel to the input terminals of the first latch, the second latch and the third latch, the output terminals of the first latch, the second latch and the third latch are respectively connected to the first switch, the second switch and the third switch, the first latch, the second latch and the third latch are all connected through the delay circuit and the second OR gate, and the first latch, the second latch, the third latch and the second OR gate all input the reset signal.

[0026] In some possible embodiments, the first latch, the second latch and the third latch are all implemented using RS triggers. Initially, the R end of the RS trigger of the first latch receives the low level of the external reset signal input, so that the first latch is in the start state, and the second latch and the third latch are in the off state.

[0027] Some possible embodiments further include a buffer, and the output end of the integration voltage unit is connected to an external ADC through the buffer to improve the driving capability of the output voltage signal of the integration voltage unit.

[0028] In a second aspect, the present invention further provides a method for using an adaptive gain amplification readout circuit at a high count rate, the method comprising:

[0029] The signal output by the detector outputs an integrated voltage signal through the integrated voltage unit;

[0030] The integrated voltage signal generates a discharge signal and a reset signal through the trigger control module;

[0031] The integrated voltage signal is input to the switch control module, and the switch control module controls the gain adjustment switch of the multi-gear switching according to the comparison result between the integrated voltage signal and the set threshold voltage, so as to switch the appropriate gear under different input charge conditions;

[0032] The discharge signal acts on the discharge switch to restore the circuit to the output baseline potential after ensuring that the output signal is read by the off-chip ADC;

[0033] The reset signal returns the gain adjustment switch to the high gain position through the switch control module, waiting for the next measurement.

[0034] The present invention adopts the above technical solution, and has the following characteristics:

[0035] 1. The front-end readout circuit with multi-level conversion gain automatic switching based on 180nm CMOS process proposed in the present invention can effectively solve the front-end signal readout requirements of high counting rate (1 MHz / channel) and large dynamic range (2.2fC-16.5pC).

[0036] 2. The present invention completes the adaptive charge measurement of each gear signal with the best accuracy within the full dynamic range through the automatic gain switching circuit controlled by the integral voltage unit, the switch control module and the trigger control module.

[0037] In summary, the present invention can be widely used in detector signal readout in nuclear physics and nuclear astrophysics. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Throughout the accompanying drawings, the same reference numerals are used to represent the same components. In the accompanying drawings:

[0039] FIG. 1 is a schematic diagram of a high count rate adaptive gain amplification readout circuit according to some embodiments of the present invention.

[0040] FIG. 2 is a schematic diagram of a trigger control module circuit according to some embodiments of the present invention.

[0041] FIG. 3 is a schematic diagram of a switch control module circuit according to some embodiments of the present invention.

[0042] FIG. 4 is a timing diagram of signals and logic operations according to some embodiments of the present invention.

[0043] FIG. 5 is a chip output voltage waveform diagram according to some embodiments of the present invention.

[0044] FIG. 6 is a simulation diagram of output tran at 16.5 pC charge and 1 MHz count rate according to some embodiments of the present invention.

[0045] FIG. 7 is a linear simulation diagram of 2.2fC-16.5pC charge input-voltage output in automatic mode according to some embodiments of the present invention.

[0046] FIG. 8 is a diagram showing the relationship between the detector body capacitance Cd and the equivalent noise charge ENC according to some embodiments of the present invention. DETAILED DESCRIPTION

[0047] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0048] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0049] For ease of description, spatially relative terms may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figures, such as "inside", "outside", "inner side", "outer side", "below", "above", etc. Such spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures.

[0050] Since the existing front-end readout ASIC chip cannot take into account the requirements of large dynamic range and high counting rate at the same time. The present invention provides an adaptive gain amplification readout circuit and a method of use at high counting rate, including the amplification readout circuit including an integral voltage unit, a switch circuit, a switch control module and a trigger control module; the switch circuit includes a gain adjustment switch and a discharge switch connected in parallel; the integral voltage unit is used to output the obtained external detector signal as an integral voltage signal; the trigger control module generates a discharge signal and a reset signal based on the integral voltage signal, and the discharge signal acts on the discharge switch to ensure that the voltage discharge of the integral voltage signal is completed to the output baseline potential after being sampled by the external ADC; the switch control module is used to control the gain adjustment switch to the corresponding gear according to the integral voltage signal, wherein the reset signal acts on the gain adjustment switch through the switch control module to return to the high gain gear. Therefore, the present invention completes the adaptive charge quantity measurement with the best accuracy of each gear signal in the full dynamic range through the automatic gain switching circuit controlled by the integral voltage unit, the switch control module and the trigger control module.

[0051] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0052] Embodiment 1: Figure 1 As shown, the adaptive gain amplification readout circuit at high count rate provided in this embodiment includes an integral voltage unit, a switching control module Switching Control, a trigger control module Trigger Control and a switch circuit, wherein the switch circuit includes a gain adjustment switch circuit and a discharge switch circuit connected in parallel;

[0053] An integral voltage unit, used to output the obtained detector output signal as an integral voltage signal that meets a set condition;

[0054] The trigger control module Trigger Control is used to generate a discharge signal Bleed and a reset signal Resettri based on the integrated voltage signal output by the integrated voltage unit. These two signals can be used to control the on and off of the switch circuit, wherein the discharge signal Bleed acts on the discharge switch circuit to ensure that the integrated voltage signal output by the integrated voltage unit is sampled by the off-chip ADC so that the circuit discharge is restored to the output baseline potential; the reset signal Resettri acts on the gain adjustment switch circuit to return the entire readout circuit to the high gain gear state.

[0055] The switching control module Switching Control is used to switch the gain adjustment switch circuit to a suitable switch position according to the integrated voltage signal output by the integrated voltage unit.

[0056] In some preferred embodiments of the present invention, the readout circuit further includes a buffer class AB for improving the driving capability of the output voltage signal of the integration voltage unit. The buffer class AB can be implemented by two complementary amplifier circuits, and the output end of the integration voltage unit is connected to an external ADC through the buffer class AB to complete sampling.

[0057] In some preferred embodiments of the present invention, the integral voltage unit includes an amplifier core and a capacitor C0 connected in parallel. After the input charge enters the integral voltage unit, it will accumulate on the capacitor C0. The accumulated charge generates an integral voltage signal at the output end of the amplifier core through the capacitor C0. Furthermore, the capacitor C0 is 300fF.

[0058] In some preferred embodiments of the present invention, the discharge switch circuit includes two switches connected in series, which are controlled by a discharge signal Bleed and have two states: in the signal integration stage, the switch is in a disconnected maximum resistance state, which can reduce noise and stabilize voltage; in the discharge stage, the closed switch can ensure a small RC coefficient, which can greatly increase the discharge speed.

[0059] In some preferred embodiments of the present invention, the gain switch circuit includes three switch branch circuits connected in parallel, wherein: the first switch branch circuit includes a first switch S1, a capacitor C1 and a first switch S1 connected in series; the second switch branch circuit includes a second switch S2, a capacitor C2 and a second switch S2 connected in series; the third switch branch circuit includes a third switch S3, a capacitor C3 and a third switch S3 connected in series, wherein the capacitor C1 is 1.5pF, the capacitor C2 is 7.2pF, and the capacitor C3 is 15pF.

[0060] Furthermore, the present invention generates different feedback capacitances by connecting capacitor C0 in parallel with capacitors C1, C2, and C3 to divide the gears. The relationship between the input charge amount and the feedback capacitance setting corresponding to the gear is: according to the voltage conversion gain conversion (Q=CU), the capacitance C of the feedback capacitance that each gear should have is obtained by dividing the preset input charge amount Q by the voltage swing U of the adaptive gain amplification readout circuit, for example, U can be 700mV, and the capacitance C of the capacitor C0, capacitor C1, capacitor C2, and capacitor C3 are allocated according to the capacitance C of the feedback capacitor.

[0061] Specifically, the gear design of this embodiment is divided into four gears:

[0062] First gear: switch S1, switch S2, and switch S3 are all disconnected, and the corresponding input charge read is 2.2fC-210fC. This gear is also a high-gain gear, which can process small signals.

[0063] Second gear: switch S1 is closed, and the corresponding input charge read is 210fC-1.26pC;

[0064] The third gear: switches S1 and S2 are closed, and the corresponding input charge read is 1.26pC-6.3pC;

[0065] Fourth gear: switches S1, S2, and S3 are all closed, and the corresponding input charge read is 6.3pC-16.5pC.

[0066] In some preferred embodiments of the present invention, as shown in FIG2 , the trigger control module Trigger Control includes a threshold comparator Dis, a monostable long delay Monostable_A, a monostable short delay Monostable_B, an RC delay unit Delay, an OR gate Or, and a short delay module Delay, which are used to generate a discharge signal Bleed and a reset signal Resettri. Among them, the positive input terminal of the threshold comparator Dis is the threshold voltage signal V ref The inverting input end of the threshold comparator Dis is the integrated voltage signal V1 output by the integrated voltage unit. The output end of the threshold comparator Dis is connected to the monostable long delay Monostable_A, the monostable short delay Monostable_B and the RC delay unit Delay in sequence. The RC delay unit Delay is also connected to the short delay module Delay through the OR gate Or. The integrated voltage signal V1 output by the integrated voltage unit generates a high level trigger of about 50nS after a set time, for example, 600nS, through the monostable long delay Monostable_A and the monostable short delay Monostable_B. This trigger and the external input reset signal Reset form a discharge signal Bleed through the OR gate Or. The discharge signal Bleed generates a delayed reset signal Resettri through the short delay module Delay.

[0067] In some preferred embodiments of the present invention, as shown in FIG3 , the switching control module Switching Control includes a high-speed comparator Dis, a latch, a delay circuit and an OR gate Or. Among them, the positive and negative input terminals of the high-speed comparator Dis are respectively connected to the integral voltage signal V1 output by the integral voltage unit and the threshold voltage Switchref, the output terminal of the high-speed comparator Dis is connected in parallel to the input terminals of the latches Latch_A, Latch_B and Latch_C, the output terminals of the latches Latch_A, Latch_B and Latch_C are respectively connected to the switch S1, the switch S2 and the switch S3, the latches Latch_A, Latch_B and Latch_C are connected through the delay circuit Delay_A (Delay_B) and the OR gate Or, and the latches Latch_A, Latch_B, Latch_C and the OR gate Or are all input with the reset signal Resettri. Among them, the switching control module Switching Control is used to compare the integrated voltage signal V1 with the threshold voltage Switchref. The output signal when the threshold is crossed enters the gear switching logic and outputs the control signal of the switch (S1, S2, S3). In the design, it is necessary to balance the speed of charge redistribution and the speed of the comparator. The threshold level is determined by the output swing and the gear dynamic setting. The gear gain is distinguished by the capacitance of the feedback capacitor. The smaller the feedback capacitor, the greater the gain. The gear design of this embodiment is divided into four gears. The first gear is S1, S2, and S3 are all disconnected, the second gear is S1 closed, the third gear is S1 and S2 closed, and the fourth gear is S1, S2, and S3 are all closed.

[0068] Furthermore, the latches are all composed of RS triggers. Initially, the R terminal of the RS trigger of latch Latch_A receives the low level of the reset signal Resettri signal input, so that latch Latch_A is in the starting state, and the other latches LatchB and latch LatchC are in the closed state. When the Q terminal is 1, the high level output is triggered. When the S terminal is 1, the circuit is in the reset state and cannot respond to the high level of the Q terminal.

[0069] The working principle of the adaptive gain amplification readout circuit under high counting rate of the present invention is as follows: Figure 1As shown, the signal output by the detector is integrated by the integral voltage unit and then output as a voltage signal. After threshold comparison and monostable delay, the signal sends out a discharge signal Bleed and a reset signal Resettri. At the same time, the integrated voltage signal passes through the switch control module Switching Control to send out a multi-gear switching switch signal (S1, S2, S3), which is used to switch the appropriate gear under different input charge conditions. Among them, the discharge signal Bleed acts on the discharge switch circuit to restore the circuit to the output baseline potential after ensuring that the output signal is read by the ADC outside the chip. The reset signal Resettri returns the circuit to the initial state, that is, the high gain gear state, through the switch control module SwitchingControl, and repeats this process in the next measurement.

[0070] The working process of the adaptive gain amplification readout circuit under high counting rate provided by the present invention is as follows:

[0071] The output signal of the detector outputs an integrated voltage signal with a rise time less than 10ns through an integrated voltage unit;

[0072] The integrated voltage signal is compared with the threshold value of the trigger control module Trigger Control and the monostable delay, and then a discharge signal Bleed and a reset signal Resettri are sent out.

[0073] At the same time, the integrated voltage signal sends out a multi-gear switching switch signal through the switching control module Switching Control, which is used to switch the appropriate gear under different input charge conditions. By comparing with the threshold, when the charge exceeds the current gear, the control switch of the feedback capacitor is triggered by the logic of the switching control module Switching Control to close and enter the next gear.

[0074] The bleed signal Bleed ensures that the output signal works after being read by the off-chip ADC;

[0075] The reset signal Resettri returns the circuit to the initial state, that is, the state of the high gain gear, through the switching control module Switching Control, waits for the next measurement, and repeats this process in the next measurement.

[0076] The following describes in detail the use of the adaptive gain amplification readout circuit at high count rate of the present invention through specific embodiments.

[0077] This embodiment takes the input signal adaptive third-level gain as an example to analyze the overall working process of the circuit in detail. The third level is when switches S1 and S2 are closed, and the corresponding input charge read out is 1.26pC-6.3pC.

[0078] The comparison result between the integral voltage V1 output by the integral voltage unit and the comparator threshold Switchref of the switching control module Switching Control is used as Figure 3 Input of latch Latch_A in the middle.

[0079] When the integrated voltage V1 output exceeds the threshold Switchref, the Q-end input of latch Latch_A is high level to turn on the S1 switch and enter the second gear. At this time, the Q-end signal of latch Latch_A is low level. After delay, the low level is triggered to the R-end of latch Latch_B through the OR gate Or to turn on latch Latch_B. Here, the delay circuit Delay_A time is determined by the preamplifier bandwidth and the size of the capacitor. The amount of stored charge during the delay circuit Delay_A time completes the process of sharing in the increased feedback capacitor and continuing to accumulate the preamplifier voltage (the sharing speed is determined by the size of the capacitor C2). After the delay circuit Delay_A time, if the preamplifier output voltage is still greater than the comparison threshold, the high level input to the S-end of latch Latch_B triggers the switch S2 to close the signal and enter the fourth gear; similarly, after the delay circuit Delay_B, the comparator will enter a low level, and the output to the S-end of latch Latch_C will not trigger S3 to close, thereby completing the measurement with the third gear retention.

[0080] After the monostable delay, the discharge signal Bleed generated by the trigger control module Trigger Control triggers the Bleed switch to close and discharge the stored charge. After a delay of 40nS, the discharge signal Bleed is used as the reset signal Resettri to trigger the latch of the switching control module Switching Control to give a high level to its R end, disconnecting the switches S1, S2, and S3 signals. After the reset signal Resettri ends, the discharge signal Bleed becomes a low level at the same time, and the charges in all capacitors are discharged. At this point, the readout circuit returns to its initial gear.

[0081] As shown in Figure 4, the overall working timing is shown. Using the Spectre simulation tool, a signal with a frequency of 1MHz and a charge ranging from 2.2fC to 16.5pC is input in the automatic gain switching mode. The transient waveform of the output signal can be obtained through simulation. The integral nonlinearity and noise characteristics of the circuit can be known through analysis.

[0082] Figure 5 The circuit output voltage waveform is amplified according to Figure 5 It can be seen that its rise time (10% ~90%) is 7nS, and the gear switch is closed at M0, M1, and M2 through asynchronous logic control to complete the gear switching to the fourth gear.

[0083] like Figure 6The figure shows the voltage waveform of the signal output through the buffer class AB. It can be seen that at a count rate of 1MHz, the continuous input of 16500fC of charge can also complete the hold, discharge, and reset processes and work normally.

[0084] As shown in FIG7 , a linear graph is drawn after scanning each gear position. The coordinate is the input charge (fC) and the ordinate is the output voltage (mV). The integral nonlinearity of each gear position interval is better than 0.2%.

[0085] As shown in Figure 8, it is a relationship diagram between the detector body capacitance Cd and the equivalent noise charge ENC at a gear (2.2fC-210fC) with higher signal-to-noise ratio requirements. The circuit as a whole can achieve an equivalent noise charge of about 1300 e- at a body capacitance of 20pF.

[0086] Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In the description of this specification, the description of reference terms "a preferred embodiment", "further", "specifically", "in the present embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of this specification. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples without contradiction.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An adaptive gain amplifier readout circuit at high count rate, characterized in that: The amplification readout circuit includes an integral voltage unit, a switch circuit, a switch control module and a trigger control module; the switch circuit includes a gain adjustment switch and a discharge switch connected in parallel; The integral voltage unit is used to output the obtained external detector signal as an integral voltage signal; The trigger control module generates a discharge signal and a reset signal based on the integrated voltage signal, and the discharge signal acts on the discharge switch to ensure that the integrated voltage signal is sampled by the external ADC and the voltage is discharged to the output baseline potential; the trigger control module includes a threshold comparator, a monostable long delay, a monostable short delay, an RC delay unit, a first OR gate and a short delay module, the threshold voltage signal is input to the positive input end of the threshold comparator, the integrated voltage signal is input to the reverse input end of the threshold comparator, the output end of the threshold comparator is connected to the monostable long delay, the monostable short delay and the RC delay unit in sequence, and the RC delay unit is also connected to the short delay module through the first OR gate, wherein: the integrated voltage signal generates a high-level trigger signal through the monostable long delay and the monostable short delay, the high-level trigger signal and the external input reset signal form the discharge signal through the first OR gate, and the discharge signal generates a delay through the short delay module to form the reset signal; The switch control module is used to control the gain adjustment switch to a corresponding gear position according to the integrated voltage signal, wherein the reset signal acts on the gain adjustment switch to return to a high gain gear position through the switch control module, and the switch control module includes a high-speed comparator, first to third latches, a first delay circuit, a second delay circuit and two second OR gates, the positive and negative input ends of the high-speed comparator are respectively connected to the integrated voltage signal and the set threshold voltage signal, the output end of the high-speed comparator is connected in parallel to the input ends of the first latch, the second latch and the third latch, the output ends of the first latch, the second latch and the third latch are respectively connected to the first switch, the second switch and the third switch, the first latch is connected to the second latch through the first delay circuit and one of the second OR gates, the second latch is connected to the third latch through the second delay circuit and another second OR gate, and the first latch, the second latch, the third latch and the two second OR gates are all input with the reset signal; A buffer, wherein the output end of the integration voltage unit is connected to an external ADC through the buffer, so as to improve the driving capability of the output voltage signal of the integration voltage unit.

2. The high count rate adaptive gain amplifier readout circuit according to claim 1, characterized in that: The integral voltage unit includes an amplifier and a capacitor connected in parallel. Input charges of an external detector enter the integral voltage unit and are accumulated on the capacitor. The accumulated charges generate an integral voltage signal at the output end of the amplifier through the capacitor.

3. The high count rate adaptive gain amplifier readout circuit according to claim 1, characterized in that: The discharge switch includes two Bleed switches connected in series, and the discharge signal controls the two Bleed switches to have two states: In the signal integration stage, the two Bleed switches are in a disconnected maximum resistance state; During the discharge phase, the two Bleeds are closed for discharge.

4. The high count rate adaptive gain amplification readout circuit according to claim 3, characterized in that: The gain adjustment switch comprises three switch branches connected in parallel, wherein: The first switch subcircuit includes a first switch, a first capacitor and a first switch connected in series; The second switch subcircuit includes a second switch, a second capacitor and a second switch connected in series; The third switch subcircuit includes a third switch, a third capacitor, and a third switch connected in series.

5. The high count rate adaptive gain amplifier readout circuit according to claim 4, characterized in that: The gear design is divided into four gears: First gear: the first switch, the second switch, and the third switch are all disconnected, and the corresponding input charge read is 2.2fC-210fC. This gear is also a high gain gear; Second gear: The first switch is closed, and the corresponding input charge read is 210fC-1.26pC; The third gear: the first switch and the second switch are closed, and the corresponding input charge read is 1.26pC-6.3pC; Fourth gear: The first switch, the second switch and the third switch are all closed, and the corresponding read input charge is 6.3 pC-16.5pC.

6. The high count rate adaptive gain amplifier readout circuit according to claim 1, characterized in that: The first latch, the second latch and the third latch are all implemented using RS triggers. Initially, the R end of the RS trigger of the first latch receives the low level of the external reset signal input, so that the first latch is in the start state, and the second latch and the third latch are in the close state.

7. A method for using the adaptive gain amplification readout circuit at high count rate according to any one of claims 4 to 6, characterized in that: The method includes: The signal output by the detector outputs an integrated voltage signal through the integrated voltage unit; The integrated voltage signal generates a discharge signal and a reset signal through the trigger control module; The integrated voltage signal is input to the switch control module, and the switch control module controls the gain adjustment switch of the multi-gear switching according to the comparison result between the integrated voltage signal and the set threshold voltage, so as to switch the appropriate gear under different input charge conditions; The discharge signal acts on the discharge switch to restore the circuit to the output baseline potential after ensuring that the output signal is read by the off-chip ADC; The reset signal returns the gain adjustment switch to the high gain position through the switch control module, waiting for the next measurement.

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