A method and system for dynamically allocating storage of multi-core system chips

Abstract

The present invention relates to a method and system for dynamically allocating storage of a multi-core system chip, the system comprising: a plurality of central processing units (CPUs), a system bus matrix, a FLASH bus matrix, a RAM bus matrix, a bus configuration unit, a storage unit, and a scenario decision module; the bus configuration unit is used to configure the system bus matrix, the FLASH bus matrix, and the RAM bus matrix according to bus configuration information; the present invention sets a bus configuration unit at the hardware level to realize dynamic allocation of address space corresponding to each bus port, avoids bus conflicts during kernel operation, and thus fundamentally improves bus performance.

Description

Technical Field

[0001] The present invention belongs to the technical field of memory management, and in particular relates to a method and system for dynamically allocating memory of a multi-core system chip. Background Art

[0002] The central processing unit is a circuit composed of one or a few large-scale integrated circuits. These circuits perform the functions of control components and arithmetic logic components. The central processing unit can complete operations such as fetching instructions, executing instructions, and exchanging information with external memory and logic components. In the system architecture of the chip, the central processing unit will only occupy a small area in the chip. The other parts are memory, clock generation and distribution logic, system bus, and peripherals. In general chip design, the bus architecture of the central processing unit, the correspondence between memory units, processing units, and storage units are fixed and restricted, so that each processing unit has a small number of memory types and quantities, and the central processing unit core can only access a certain amount of memory through the bus, resulting in insufficient memory resources and cannot meet all application scenarios.

[0003] In actual applications, the size of the program run by each CPU and the size of the RAM required will vary with different application scenarios. In the prior art, instruction storage units (PFLASH) and data storage areas (RAM) are often allocated separately and correspondingly for each CPU; and for the situation where the application requirements on each CPU are different, that is, the resource competition for applications located on different cores, especially the storage resource competition, is often solved by dividing the storage resources. This resource division can be understood as a logical division, which is often implemented at the operating system level to allocate more storage resources to applications with more storage requirements; however, this brings a new problem. The memory must be accessed through the port. When different storage resources need to be accessed through the same port, even if an application is allocated more storage space, it is useless. When it uses the storage space, it may still be unable to use the required storage space due to bus conflicts caused by port competition; in fact, bus port resources are quite valuable, and the area saving for bus communication can reduce the chip area;

[0004] The present invention starts from the application scenario and sets a bus configuration unit for the multi-core system to synchronize the use and allocation of storage resources with the configuration of the port, so that the application can actually use the allocated storage space, reducing bus conflicts and bus waiting, and further improving the processing efficiency of the multi-core system chip. Summary of the invention

[0005] In order to solve the above problems in the prior art, the present invention proposes a method and system for dynamically allocating storage of a multi-core system chip, the system comprising:

[0006] Multiple central processing units CPU, system bus matrix, FLASH bus matrix, RAM bus matrix, bus configuration unit, storage unit, scene decision module; the storage unit includes ROM, DFLASH, PFLASH and data storage area RAM; the PFLASH includes one or more sub-PFLASH units; the RAM includes one or more sub-RAM units;

[0007] The system bus matrix is ​​provided with SN S-side ports and MN M-side ports; the S-side ports are used to connect to the storage unit; and the M-side ports are used to connect to the CPU; one side of the FLASH bus matrix is ​​connected to the S-side port of the system bus matrix, and the other side is connected to the PFLASH; one side of the RAM bus matrix is ​​connected to the S-side port of the system bus matrix, and the other side is connected to the RAM;

[0008] The scenario decision unit is set in the operating system kernel; the bus configuration unit is set in the multi-core system chip; the storage space allocated to the application program on each CPU in the current application scenario is monitored in real time; bus configuration information is generated based on the allocated storage space; and the generated bus configuration information is sent to the bus configuration unit;

[0009] The generating bus configuration information based on the allocated storage space is specifically as follows: generating address allocation information according to the allocated storage space; allocating the address range corresponding to the storage space of the storage unit to each CPU, so that the address range allocated to each CPU is continuous and the size of the storage space corresponding to the address range satisfies the allocated storage space; using the address allocation information as the first part of the bus configuration information; generating address division information according to the address allocation information; dividing each continuous address range into one or more sub-storage units, so that the divided address range is adapted to the size of the available storage space of the sub-storage unit, wherein each sub-storage unit corresponds to a sub-PFLASH unit or a sub-RAM unit; thereby, the one or more sub-storage units are allocated to the same or different S-side ports and their corresponding CPUs; using the address range division information and its corresponding sub-storage units as the second part of the bus configuration information;

[0010] The bus configuration unit is used to configure the system bus matrix, the FLASH bus matrix and the RAM bus matrix according to the bus configuration information; send the first part of the bus configuration information to the system bus matrix for configuration, and send the second part of the bus configuration information to the FLASH bus matrix and the RAM bus matrix to realize dynamic allocation of storage units between CPUs;

[0011] The system bus matrix is ​​used to allocate addresses to the S-side ports according to the received bus configuration information; and to map the address space requested by the kernel to the S-side ports according to the address allocation result;

[0012] The FLASH bus matrix and the RAM bus matrix are used to respectively divide the addresses of the PFLASH or RAM according to the received bus configuration information, and map the address space requested by the S-side port to different sub-PFLASH units or sub-RAM units according to the address division results; thereby associating the sub-FLASH units / sub-RAM units to the same or different S-side ports.

[0013] Furthermore, the number of MNs is equal to the number of CPUs.

[0014] Furthermore, SN is equal to 8, and the corresponding S-side ports are S1-S8.

[0015] Furthermore, the number of ports on the other side of the FLASH bus matrix is ​​equal to the number of sub-PFLASH units.

[0016] Furthermore, the number of ports on the other side of the RAM bus matrix is ​​equal to the number of sub-RAM units.

[0017] Furthermore, the bus configuration unit configures the system bus matrix, the PFLASH bus matrix and the RAM bus matrix based on the bus configuration information before the application is run.

[0018] Furthermore, the number of CPUs is equal to 4.

[0019] A multi-core system chip, the chip implements the dynamic allocation system of the multi-core system chip storage.

[0020] A method for dynamically allocating storage in a multi-core system chip, the method being applied to the dynamic allocation system for storage in a multi-core system chip; comprising:

[0021] The multi-core system chip starts and runs the boot program. At the beginning of the boot program, the bus configuration unit is started and initialized. The bus configuration unit reads the initial configuration information to configure the system bus matrix, the FLASH bus matrix and the RAM bus matrix.

[0022] A multi-core system server implements the dynamic allocation system of multi-core system chip storage.

[0023] The beneficial effects of the present invention include:

[0024] (1) The present invention sets a scenario decision unit to discover the difference of actual application scenarios at the operating system level, and converts the difference of the actual scenarios into bus configuration information, dynamically configures the address space size and the corresponding relationship of different bus ports; sets a bus configuration unit at the hardware level to realize the dynamic allocation of the address space corresponding to each bus port, avoids the occurrence of bus conflicts during the operation of the kernel, and fundamentally improves the bus performance through the joint action of software and hardware;

[0025] (2) The number of bus ports is reduced, which can further reduce the complexity of the correspondence between the core and the port, reduce the area of ​​the system bus matrix, and thus reduce the hardware cost;

[0026] (3) With the operating system transparent, the storage unit can be made to work in vote security mode simply by modifying the bus configuration information. This meets the storage security requirements in specific application scenarios without changing the system bus structure and memory controller design. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present application, but do not constitute an improper limitation of the present invention. In the drawings:

[0028] Figure 1 A schematic diagram of a system architecture for dynamically allocating storage in a multi-core system chip according to an embodiment of the present invention.

[0029] Figure 2 A schematic diagram of the dynamic configuration of a system bus matrix, a FLASH bus matrix and a RAM bus matrix in a dynamic allocation system architecture of multi-core system chip storage provided by an embodiment of the present invention.

[0030] Figure 3 A schematic diagram of a system architecture for dynamically allocating storage in a multi-core system chip according to another embodiment of the present invention.

[0031] Figure 4 A schematic diagram of a dynamic allocation method for multi-core system chip storage provided by the present invention.

[0032] Figure 5 The diagram is a schematic diagram of a multi-core system chip storage management system architecture in the prior art. DETAILED DESCRIPTION

[0033] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, wherein the illustrative embodiments and descriptions are only used to explain the present invention but are not intended to limit the present invention.

[0034] The present invention proposes a method and system for dynamically allocating storage in a multi-core system chip, as shown in the attached Figure 1As shown, the dynamic allocation system of the multi-core system chip storage includes: multiple central processing units (CPUs, cores or cores), a system bus matrix, a FLASH bus matrix, a RAM bus matrix, a bus configuration unit, a storage unit, and a scene decision module;

[0035] The storage unit includes ROM, DFLASH, PFLASH and data storage area RAM;

[0036] The system bus matrix is ​​provided with SN S-side ports and MN M-side ports; the S-side ports are used to connect to the storage unit; and the M-side ports are used to connect to the CPU; the S-side ports are also bus ports;

[0037] Preferably: the number of MNs is equal to the number of cores;

[0038] Preferably: SN is equal to 8, and the corresponding S-side ports are S1-S8; MN is equal to 4, and the corresponding M-side ports are M1-M4;

[0039] The PFLASH includes one or more sub-PFLASH units; for example, 8;

[0040] The RAM includes one or more sub-RAM units; for example: 8;

[0041] The bus configuration unit is used to configure the system bus matrix, the FLASH bus matrix and the RAM bus matrix according to the bus configuration information; thereby realizing the dynamic allocation of storage units between CPUs; and is also used to send a DFLASH selection signal to the second selector MUX1 to select DFLASH in response to detecting an access request of the application program to DFLASH; and is also used to read the first initial configuration information and the second initial configuration information in response to detecting the start and end of the boot program; and send a selection signal to the first selector and / or the second selector based on the first initial configuration information and the second initial configuration information;

[0042] Preferably: after the DFLASH access request is completed, a RAM bus matrix gating signal is sent to the second selector MUX1 to restore the gating of the RAM bus matrix;

[0043] The bus configuration unit is also used to respond to a DFLASH access request issued during the application program execution, and send a DFLASH selection signal to the second selector MUX1 to select DFLASH; at this time, since S5 is a shared port, a short port pause may be caused;

[0044] As attached Figure 1 As shown, one side (M side) of the system bus matrix is ​​connected to the CPU, and one side (S side) is connected to the storage unit;

[0045] One side of the FLASH bus matrix is ​​connected to the S-side port of the system bus matrix, and the other side is connected to the PFLASH; that is, the number of ports on the other side is equal to the number of sub-PFLASH units; one side of the RAM bus matrix is ​​connected to the S-side port of the system bus matrix, and the other side is connected to the RAM; that is, the number of ports on the other side is equal to the number of sub-RAM units;

[0046] The system bus matrix is ​​used to allocate addresses to the S-side ports according to the received bus configuration information; and to map the address space requested by the kernel to the S-side ports according to the address allocation result; in order to achieve the allocation result, the M-side port corresponding to the kernel is configured to maintain a corresponding relationship with an S-side port, and the address range of the corresponding kernel can be accessed through the S-side port, that is, the sub-storage unit corresponding to the address range of the kernel can be accessed; as shown in the attached Figure 2 As shown;

[0047] The FLASH bus matrix and the RAM bus matrix are used to divide the addresses of the PFLASH or RAM according to the received bus configuration information, and map the address space requested by the S-side port to different sub-PFLASH units or sub-RAM units according to the address division results; thereby associating the sub-FLASH units / sub-RAM units to the same or different S-side ports; as shown in the attached Figure 2 As shown, specifically: by connecting one or more sub-FLASH units / sub-RAM units corresponding to the address range of a core together to an S-side port, and the one S-side port connected to corresponds to an M-side port, and the M-side port corresponds to the core one by one, the address division is realized from the hardware; that is, the internal connection relationship of the system bus matrix, the FLASH bus matrix and the RAM bus matrix is ​​dynamically configured to support the correspondence of the address range and the dynamic division of the address;

[0048] The scenario decision unit is arranged in the operating system kernel; the bus configuration unit is arranged in the multi-core system chip; the storage space allocated by the application program on each core in the current application scenario is monitored in real time; bus configuration information is generated based on the allocated storage space; the generated bus configuration information is sent to the bus configuration unit; the bus configuration unit configures the system bus matrix, the PFLASH bus matrix and the RAM bus matrix based on the bus configuration information before the application program runs;

[0049] As attached Figure 3As shown, the dynamic allocation system for multi-core system chip storage also includes a first selector and a second selector; the input end of the first selector MUX0 is the ROM and FLASH bus matrix, and the output end is connected to the S-side port S1; the selection signal comes from the bus configuration unit; the input end of the second selector MUX1 is the DFLASH and RAM bus matrix, and the output end is connected to the S-side port S5; the selection signal comes from the bus configuration unit; considering that ROM is only used during BOOT in some applications, in order to avoid idle waste of bus ports, the ROM and FLASH bus matrices are selected and multiplexed through a MUX0. When BOOT, the first selector MUX0 selects RO M is connected to the S-side port S1; when BOOT is finished, the first selector MUX0 is connected to the FLASH bus matrix; similarly, considering that DFLASH is not frequently operated in most application scenarios, an independent S-side port is allocated to DFLASH, which is idle most of the time; DFLASH and RAM bus matrix are selected and multiplexed through a second selector MUX1; when DFLASH is accessed, the second selector MUX1 selects DFLASH; when RAM is accessed, the first selector MUX0 selects the bus matrix; through the above two settings, compared with the traditional design, the S0 and S5 ports can be removed, reducing the hardware overhead of the bus port;

[0050] Alternatively: the output end of the first selector is connected to the S-side port SX1, and the output end of the second selector MUX1 is connected to the S-side port SX2; wherein: the SX1 and SX2 are set to correspond to the non-master CPU; the CPU is divided into a master CPU and a slave CPU; the computing power of the master CPU is stronger than that of the slave CPU;

[0051] Replaceable: Determine the master CPU and slave CPU according to the application scenario of the multi-core system chip, and set the S ports SX1 and SX2 to the S-side ports corresponding to the slave CPU; of course, when selecting SX1 and SX2, the specific DFLASH access timing can also be considered to further determine the corresponding relationship between SX1 and SX2 and the CPU;

[0052] For example, when the multi-core system chip is a car-grade chip, for such an application scenario, the application program's use of non-volatile memory such as DFLASH is generally read when the vehicle is powered on or off, and the port will not be very busy at this time. Therefore, such port reuse is worthwhile.

[0053] The present invention proposes a method and system for dynamically allocating storage in a multi-core system chip, as shown in the attached Figure 4 As shown, the method comprises the following steps:

[0054] Step S1: The multi-core system chip starts and runs the boot program (BOOT program), starts and initializes the configuration bus configuration unit; during the initialization configuration process, the bus configuration unit reads the first initial configuration information to configure the system bus matrix, the FLASH bus matrix and the RAM bus matrix; and after the boot program is completed, reads the second initial configuration information to configure the system bus matrix, the FLASH bus matrix and the RAM bus matrix;

[0055] Specifically, the multi-core system chip starts and runs the boot program, starts and initializes the configuration bus configuration unit at the beginning of the boot program, and the bus configuration unit reads the first initial configuration information to configure the system bus matrix, the FLASH bus matrix and the RAM bus matrix; based on the first initial configuration information, the bus configuration unit sends a first selection signal, so that the first selector MUX0 selects the ROM and connects it to the S-side port S1; the second selector MUX1 selects the DFLASH and connects it to the S-side port S5; after the boot program is completed and the application program runs, based on the second initial configuration information, a second selection signal is sent, so that MUX0 selects the FLASH bus matrix and connects it to the S-side port S1; the second selector MUX1 selects the RAM bus matrix and connects it to the S-side port S5;

[0056] Preferably: the first initial configuration information and the second initial configuration information are stored in a non-volatile storage space in a bus configuration unit;

[0057] Step S2: determining the storage space allocated to each CPU in the current application scenario; and generating bus configuration information based on the allocated kernel storage space, wherein the bus configuration unit dynamically configures the system bus matrix, the FLASH bus matrix and the RAM bus matrix based on the bus configuration information; wherein: the storage space includes PFLASH and the data storage area RRAM;

[0058] Preferably: the scenario decision unit is arranged in the operating system kernel; the storage space allocated to the application on each core in the current application scenario is monitored in real time; bus configuration information is generated based on the allocated storage space; the generated bus configuration information is sent to the bus configuration unit; the bus configuration unit configures the system bus matrix, the PFLASH bus matrix and the RAM bus matrix based on the bus configuration information before the application runs;

[0059] The bus configuration information is generated based on the allocated kernel storage space, specifically as follows: generating address allocation information according to the allocated kernel storage space; making the address range corresponding to the storage space of the storage unit be allocated to each kernel, the kernel address range allocated to each kernel is continuous and the storage space size corresponding to the address range satisfies the allocated kernel storage space; using the address allocation information as the first part of the bus configuration information; generating address division information according to the address allocation information; making each continuous kernel address range be divided into one or more sub-storage units; making the divided address range and the available storage space size of the sub-storage unit adapt to each other; wherein each sub-storage space corresponds to a sub-PFLASH unit or a sub-RAM unit; thereby making the one or more sub-storage spaces be allocated to the same or different S-side ports and their corresponding kernels; using the kernel address range division information and its corresponding sub-storage units as the second part of the bus configuration information;

[0060] The kernel storage space that satisfies the allocation is specifically: greater than or equal to the allocated kernel storage space;

[0061] Preferably: the system bus matrix is ​​configured so that each core corresponds to a fixed S-side port; that is, a one-to-one correspondence is maintained between the M-side port and the S-side port; thereby further reducing the design complexity and hardware overhead of the system bus; further: each M-side port is configured to maintain a corresponding relationship with an S-side port, and the address range of the corresponding core can be accessed through the S-side port, that is, the sub-storage unit corresponding to the address range of the core can be accessed;

[0062] The bus configuration unit is also used to enter the vote safety mode after receiving the vote mode signal; in the vote safety mode, the bus configuration information is generated based on the allocated kernel storage space, specifically: generating address allocation information according to the allocated kernel storage space; so that the address range corresponding to the storage space of the storage unit is allocated to each kernel, the kernel address range allocated to each kernel is continuous and the storage space size corresponding to the address range is twice the allocated kernel storage space; using the address allocation information as the first part of the bus configuration information; generating address division information according to the address allocation information; so that each continuous kernel address range is respectively allocated to 2 groups of sub-storage units, and one or more sub-storage units contained in each group of sub-storage units in the 2 groups of sub-storage units divide the continuous kernel address range; so that the divided kernel address range is adapted to the available storage space size of the sub-storage unit; wherein: each sub-storage space corresponds to a sub-PFLASH unit or a sub-RAM unit; so that every two groups of sub-storage units are allocated to an S-side port and its corresponding kernel as a whole; using the kernel address range division information and its corresponding 2 groups of sub-storage units as the second part of the bus configuration information;

[0063] Preferably: in the vote security mode; when facing a write operation from the kernel, since the kernel address range is allocated twice, the write operation content is written into two independent sub-storage spaces at the same time; the two sub-storage spaces independently respond to the data access request from the kernel, and the independent responses are accessed through different FLASH bus matrix or RAM bus matrix interfaces; the judgment result after judgment is fed back to the allocated S-side port and its corresponding kernel as the only response information; therefore, for the kernel, even for the OS, the vote mode and its voting process are transparent to them, thereby greatly improving the security of the system and the security granularity;

[0064] Preferably: the FLASH controller or the RAM controller performs the decision operation.

[0065] Example 1

[0066] Before the dynamic allocation method of the present invention is adopted, as shown in the attached Figure 5As shown, a PFLASH and data storage area RAM are allocated separately for each CPU; the following table shows that PFLASH0-3 and RAM0-3 are allocated to CPU0-3, the size and address of PFLASH0-3 and RAM0-3, and the S-side port allocation; here, there are 4 sub-PFLASH units and 4 sub-RAM units, and 10 S-side ports, S0-S9, of which: S0 is dedicated to ROM, and S5 is dedicated to DFLASH; S1-S4 are used for PFLASH, and S6-S9 are used for RAM;

[0067] PFLASH0 2MB, 0x0000_0000~0x001F_FFFF, S1 PFLASH1 2MB, 0x0020_0000~0x003F_FFFF, S2 PFLASH2 2MB, 0x0040_0000~0x005F_FFFF, S3 PFLASH3 2MB, 0x0060_0000~0x007F_FFFF, S4 RAM0 256KB, 0x2000_0000~0x2003_FFFF, S6 RAM1 256KB, 0x2004_0000~0x2007_FFFF, S7 RAM2 256KB, 0x2008_0000~0x200B_FFFF, S8 RAM3 256KB, 0x200C_0000~0x200F_FFFF, S9

[0068] Since the size of the program run by each CPU and the amount of RAM required vary with different application scenarios, the size of the storage space allocated by the operating system is also different and changes dynamically, as shown in the following table;

[0069] CPU0 FLASH size = 1MB, RAM size = 128KB, S1 (first half), S6 (first half) CPU1 FLASH size = 3MB, RAM size = 512KB, S1 (second half), S2, S7, S8 CPU2 FLASH size=2MB, RAM size=256KB, S3, S9 CPU4 FLASH size = 2MB, RAM size = 128KB, S4, S6 (first half)

[0070] At this time, CPU0 and CPU1 share PFLASH0 of S-side port S1, and CPU0 and CPU4 share RAM0 of S-side port; if CPU0 and CPU1 access PFLASH0 / RAM0 of the S-side port at the same time, bus conflict and bus waiting will occur, resulting in CPU performance degradation.

[0071] Example 2

[0072] In the present invention, dynamic allocation is achieved through bus configuration information, and FLASH / RAM is allocated to different S-side ports, so that CPU0~3 can independently access different FLASH / RAM units, avoiding conflicts and improving performance; the details are as follows:

[0073] The address of S1 is 0x0000_0000~0x000F_FFFF, and the size is 1MB; assign sub-PFLASH unit 0 to S-side port S1 The address of S2 is 0x0010_0000~0x003F_FFFF, and the size is 3MB; assign sub-PFLASH units 1 / 2 / 3 to S-side port S2 The address of S3 is 0x0040_0000~0x005F_FFFF, and the size is 2MB; assign sub-PFLASH unit 4 / 5 to S-side port S3 The address of S4 is 0x0060_0000~0x007F_FFFF, and the size is 2MB; assign sub-PFLASH unit 6 / 7 to S-side port S4 The address of S6 is 0x2000_0000~0x2001_FFFF, and the size is 128KB; assign sub-RAM unit 0 to S-side port S6 The address of S7 is 0x2002_0000~0x2009_FFFF, and the size is 512KB; assign sub-RAM units 1 / 2 / 3 / 4 to S-side port S7 The address of S8 is 0x200A_0000~0x200D_FFFF, and the size is 256KB; assign sub-RAM unit 5 / 6 to S-side port S8 The address of S9 is 0x200E_0000~0x200F_FFFF, and the size is 128KB; assign sub-RAM unit 7 to S-side port S9

[0074] Through the above configuration, in the scenario of the above embodiment 2, the dynamic configuration effect is as follows: CPU0~3 and PFLASH, RAM are accessed through independent S-side ports, do not interfere with each other, avoid bus conflicts, and improve system performance;

[0075] CPU0 accesses 1MB PFLASH space through S1 and 128KB RAM space through S6 CPU1 accesses 3MB PFLASH space through S2 and 512KB RAM space through S7 CPU2 accesses 2MB PFLASH space through S3 and 256KB RAM space through S8 CPU3 accesses 2MB PFLASH space through S4 and 128KB RAM space through S9

[0076] Based on the same inventive concept, the present invention also provides a multi-core system chip to implement the dynamic allocation system of the multi-core system chip storage.

[0077] Based on the same inventive concept, the present invention also provides a multi-core system server, which implements the dynamic allocation system of the multi-core system chip storage.

[0078] A computer program (also referred to as a program, software, software application, script, or code) can be written in any form of a programming language, including an assembled or interpreted language, a declarative or procedural language, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple collaborative files (e.g., files storing one or more modules, subroutines, or code portions). A computer program can be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

[0079] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0080] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A system that specifies the functions of a box or multiple boxes.

[0081] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction system, which is implemented in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0082] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A dynamic allocation system for multi-core system chip storage, characterized in that: The system comprises: Multiple central processing units CPU, system bus matrix, FLASH bus matrix, RAM bus matrix, bus configuration unit, storage unit, scene decision module; the storage unit includes ROM, DFLASH, PFLASH and data storage area RAM; the PFLASH includes one or more sub-PFLASH units; the RAM includes one or more sub-RAM units; The system bus matrix is ​​provided with SN S-side ports and MN M-side ports; the S-side ports are used to connect to the storage unit; and the M-side ports are used to connect to the CPU; one side of the FLASH bus matrix is ​​connected to the S-side port of the system bus matrix, and the other side is connected to the PFLASH; one side of the RAM bus matrix is ​​connected to the S-side port of the system bus matrix, and the other side is connected to the RAM; The scene decision unit is arranged in the operating system kernel; the bus configuration unit is arranged in the multi-core system chip; Real-time monitoring of the storage space allocated to each application on the CPU in the current application scenario; generating bus configuration information based on the allocated storage space; and sending the generated bus configuration information to the bus configuration unit; The generating bus configuration information based on the allocated storage space specifically comprises: generating address allocation information according to the allocated storage space; allocating the address range corresponding to the storage space of the storage unit to each CPU, so that the address range allocated to each CPU is continuous and the size of the storage space corresponding to the address range satisfies the allocated storage space; and using the address allocation information as the first part of the bus configuration information; Generate address division information according to the address allocation information; divide each continuous address range into one or more sub-storage units, so that the divided address range is adapted to the available storage space size of the sub-storage unit, wherein each sub-storage unit corresponds to a sub-PFLASH unit or a sub-RAM unit; thereby the one or more sub-storage units are allocated to the same or different S-side ports and their corresponding CPUs; use the address range division information and the corresponding sub-storage units as the second part of the bus configuration information; The bus configuration unit is used to configure the system bus matrix, the FLASH bus matrix and the RAM bus matrix according to the bus configuration information; Sending the first part of the bus configuration information to the system bus matrix for configuration, and sending the second part of the bus configuration information to the FLASH bus matrix and the RAM bus matrix to achieve dynamic allocation of storage units between CPUs; The system bus matrix is ​​used to allocate addresses to the S-side ports according to the received bus configuration information; and to map the address space requested by the kernel to the S-side ports according to the address allocation result; The FLASH bus matrix and the RAM bus matrix are used to respectively divide the addresses of the PFLASH or RAM according to the received bus configuration information, and map the address space requested by the S-side port to different sub-PFLASH units or sub-RAM units according to the address division results; thereby associating the sub-FLASH units / sub-RAM units to the same or different S-side ports.

2. The dynamic allocation system for multi-core system chip storage according to claim 1, characterized in that: The number of MNs is equal to the number of CPUs.

3. The dynamic allocation system for multi-core system chip storage according to claim 2, characterized in that: SN is equal to 8, and the corresponding S-side ports are S1-S8.

4. The dynamic allocation system for multi-core system chip storage according to claim 3, characterized in that: The number of ports on the other side of the FLASH bus matrix is ​​equal to the number of sub-PFLASH units.

5. The dynamic allocation system for multi-core system chip storage according to claim 4, characterized in that: The number of ports on the other side of the RAM bus matrix is ​​equal to the number of sub-RAM cells.

6. The multi-core system chip storage dynamic allocation system according to claim 5, characterized in that: The bus configuration unit configures the system bus matrix, PFLASH bus matrix and RAM bus matrix based on the bus configuration information before the application program is run.

7. The dynamic allocation system for multi-core system chip storage according to claim 6, characterized in that: The number of CPUs is equal to 4.

8. A multi-core system chip, characterized in that: The chip implements a dynamic allocation system for multi-core system chip storage as described in any one of claims 1-7.

9. A method for dynamically allocating storage in a multi-core system chip, characterized in that: The method is applied to a dynamic allocation system for multi-core system chip storage as described in any one of claims 1 to 5; comprising: The multi-core system chip starts and runs the boot program. At the beginning of the boot program, the bus configuration unit is started and initialized. The bus configuration unit reads the initial configuration information to configure the system bus matrix, the FLASH bus matrix and the RAM bus matrix.

10. A multi-core system server, characterized in that: The multi-core system server implements a dynamic allocation system for multi-core system chip storage as described in any one of claims 1-7.

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