Dual-sided TOPCon battery structure and its preparation method

Abstract

The present invention provides a double-sided TOPCon cell structure and a preparation method thereof, specifically relating to the technical field of solar cell preparation. The double-sided TOPCon cell structure includes a silicon substrate, and on the back surface of the silicon substrate, a first tunneling oxide layer, a first polysilicon layer, a first passivation layer, a first antireflection layer, and a first metal electrode are sequentially arranged from inside to outside; on the front surface of the silicon substrate, a metal region and a non-metal region are provided; in the metal region, a second tunneling oxide layer, a second polysilicon layer, a second passivation layer, a second antireflection layer, and a second metal electrode are sequentially arranged from inside to outside; in the non-metal region, a boron-diffused emitter layer, a second passivation layer, and a second antireflection layer are sequentially arranged from inside to outside. The double-sided TOPCon cell structure provided by the present invention has polysilicon layers arranged on both sides of the silicon substrate, reducing the metallization contact recombination of the solar cell, improving the i-VOC of the cell, and improving the efficiency of the cell wafer.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell preparation, and in particular to a double-sided TOPCon cell structure and a preparation method thereof. Background Art

[0002] Tunneling oxide passivated contact (TOPCon) solar cells are a new type of silicon solar cells. When the cell is working, electrons tunnel from the n-type silicon wafer through the silicon oxide layer into the doped n-type thin film silicon layer. Existing TOPCon cells mostly use single-sided Poly technology, which solves the problem of back passivation and metallization, but the problem of front metallization has not been solved. In addition, the traditional boron diffusion process uses a high-temperature tubular boron diffusion process (temperature>1000℃), which causes great damage to the silicon wafer, affecting the yield and efficiency of the cell.

[0003] In view of this, the present invention is proposed. Summary of the invention

[0004] One of the objectives of the present invention is to provide a double-sided TOPCon battery structure, aiming to solve at least one of the above-mentioned technical problems in the prior art.

[0005] A second object of the present invention is to provide a method for preparing a double-sided TOPCon battery structure.

[0006] In order to achieve the above-mentioned purpose of the present invention, the following technical solutions are particularly adopted:

[0007] A first aspect of the present invention provides a double-sided TOPCon cell structure, comprising a silicon substrate;

[0008] The back side of the silicon substrate is provided with a first tunneling oxide layer, a first polysilicon layer, a first passivation layer, a first anti-reflection layer and a first metal electrode in sequence from inside to outside;

[0009] The front side of the silicon substrate is provided with a metal area and a non-metal area;

[0010] The metal area is provided with a second tunneling oxide layer, a second polysilicon layer, a second passivation layer, a second anti-reflection layer and a second metal electrode in sequence from the inside to the outside;

[0011] The non-metallic area is provided with a boron diffusion emitter layer, a second passivation layer and a second anti-reflection layer in sequence from the inside to the outside.

[0012] Furthermore, the material of the first tunneling oxide layer and / or the second tunneling oxide layer includes silicon oxide.

[0013] Preferably, the material of the first passivation layer and / or the second passivation layer includes aluminum oxide.

[0014] Preferably, the material of the first anti-reflection layer and / or the second anti-reflection layer includes silicon nitride.

[0015] Furthermore, the front surface is a pyramid-shaped surface.

[0016] Preferably, the first polysilicon layer is a phosphorus-doped polysilicon layer.

[0017] Preferably, the second polysilicon layer is a boron-doped polysilicon layer.

[0018] The second aspect of the present invention provides a method for preparing the double-sided TOPCon battery structure, comprising the following steps:

[0019] A BSG layer is deposited on the front side of the double-sided textured silicon substrate by PECVD, and the boron in the BSG layer is pushed into the silicon collective to form a PN junction by laser surface scanning, and then a second tunneling oxide layer and a second polysilicon layer are prepared in sequence; finally, a mask is prepared in the gate line area by laser oxidation process, and then the first tunneling oxide layer and the first polysilicon layer are prepared to obtain a semi-finished battery;

[0020] The semi-finished battery is annealed, and then a first passivation layer, a second passivation layer, a first anti-reflection layer, and a second anti-reflection layer are prepared on the back and front sides respectively, and finally a first metal electrode and a second metal electrode are prepared to obtain a double-sided TOPCon battery.

[0021] Furthermore, laser surface scanning is used to push the boron in the BSG layer into the silicon mass to form a shallow doping region and thus obtain a PN junction.

[0022] Preferably, the surface concentration of the shallow doping region is 1×10 18 cm -3 ~2×10 18 cm -3 .

[0023] Preferably, the sheet resistance of the shallow doped region is 190Ω to 230Ω.

[0024] Furthermore, the laser surface scanning uses nanosecond laser and / or picosecond laser.

[0025] Preferably, the BSG layer has a thickness of 60 nm to 140 nm.

[0026] Furthermore, the double-sided textured silicon substrate is used as a template in the deposition equipment, and N 2 O.B 2 H 6 、SiH 4 and H 2 Perform vapor deposition.

[0027] Preferably, N2 O.B 2 H 6 and SiH 4 The flow ratio is 5~9:4~10:1.

[0028] Preferably, the deposition temperature of the PECVD is 300° C. to 350° C., and the deposition time is 70 min to 90 min.

[0029] Preferably, the H 2 The flow rate is 2000sccm~8000sccm.

[0030] Preferably, the SiH 4 The flow rate is 100sccm~1000sccm.

[0031] Furthermore, a tunnel oxide layer, a polysilicon layer and an anti-reflection layer are prepared by a PECVD deposition process.

[0032] Preferably, the tunnel oxide layer includes a first tunnel oxide layer and / or a second tunnel oxide layer.

[0033] Preferably, the polysilicon layer includes a first polysilicon layer and / or a second polysilicon layer.

[0034] Preferably, the anti-reflection layer includes a first anti-reflection layer and / or a second anti-reflection layer.

[0035] Furthermore, a passivation layer is prepared by atomic layer deposition.

[0036] Preferably, the passivation layer includes a first passivation layer and / or a second passivation layer.

[0037] Furthermore, the annealing treatment is performed using a tubular annealing process.

[0038] Preferably, the method further comprises a polishing and cleaning process after masking and before forming the first tunneling oxide layer, removing the mask in the non-gate line area and polishing the velvet surface on the back side of the silicon substrate.

[0039] Compared with the prior art, the present invention has at least the following beneficial effects:

[0040] The double-sided TOPCon battery structure provided by the present invention has polysilicon layers on both sides of the silicon substrate, and the polysilicon layer is arranged between the tunneling oxide layer and the passivation layer, which reduces the carrier recombination rate on the battery surface, reduces the contact resistance, improves the i-VOC of the battery, and improves the efficiency of the battery cell.

[0041] The preparation method provided by the present invention uses PECVD to deposit the BSG layer, which reduces the damage of high temperature to the silicon substrate and improves the yield and efficiency of the battery cell; at the same time, the laser reverse etching method is used to reduce the damage of the laser to the second polysilicon layer, thereby improving the passivation effect of the second polysilicon layer on the front side and improving the efficiency of the battery cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 This is a schematic diagram of the structure of a double-sided TOPCon battery;

[0044] Figure 2 A magnified view of the metal area.

[0045] Icon: 10-N-type silicon substrate; 100-back side; 110-first tunneling oxide layer; 120-first polysilicon layer; 130-first passivation layer; 140-first anti-reflection layer; 150-first metal electrode; 200-front side; 210-metal region; 212-second tunneling oxide layer; 214-second polysilicon layer; 216-second passivation layer; 218-second anti-reflection layer; 219-second metal electrode; 220-non-metal region; 222-boron diffused emitter layer. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0047] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present invention, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0048] A first aspect of the present invention provides a double-sided TOPCon cell structure, comprising a silicon substrate;

[0049] The back side of the silicon substrate is provided with a first tunneling oxide layer, a first polysilicon layer, a first passivation layer, a first anti-reflection layer and a first metal electrode in sequence from inside to outside;

[0050] The front side of the silicon substrate is provided with a metal area and a non-metal area;

[0051] The metal area is provided with a second tunneling oxide layer, a second polysilicon layer, a second passivation layer, a second anti-reflection layer and a second metal electrode in sequence from the inside to the outside;

[0052] The non-metallic area is provided with a boron diffusion emitter layer, a second passivation layer and a second anti-reflection layer in sequence from the inside to the outside.

[0053] The double-sided TOPCon cell structure provided by the present invention has polycrystalline silicon layers on both sides of the silicon substrate, which reduces the metallization contact recombination of the solar cell, improves the i-VOC of the cell, and improves the efficiency of the cell.

[0054] The schematic diagram of the double-sided TOPCon battery structure is shown in Figure 1 As shown, it includes an N-type silicon substrate 10, and the N-type silicon substrate 10 includes a front side 200 and a back side 100; the back side 100 is provided with a first tunneling oxide layer 110, a first polysilicon layer 120, a first passivation layer 130, a first anti-reflection layer 140 and a first metal electrode 150 in sequence from the inside to the outside; the front side 200 is provided with a metal area 210 and a non-metal area 220 surrounding the metal area 210. The enlarged detail of the metal area 210 is shown in FIG. Figure 2 As shown, a second tunneling oxide layer 212, a second polysilicon layer 214, a second passivation layer 216, a second anti-reflection layer 218 and a second metal electrode 219 are sequentially arranged from the inside to the outside; the non-metallic area 220 is sequentially arranged from the inside to the outside with a boron diffusion emitter layer 222, a second passivation layer 216 and a second anti-reflection layer 218.

[0055] Furthermore, the material of the first tunneling oxide layer and / or the second tunneling oxide layer includes silicon oxide.

[0056] Preferably, the material of the first passivation layer and / or the second passivation layer includes aluminum oxide.

[0057] Preferably, the material of the first anti-reflection layer and / or the second anti-reflection layer includes silicon nitride.

[0058] Furthermore, the front surface is a pyramid-shaped surface.

[0059] Preferably, the first polysilicon layer is a phosphorus-doped polysilicon layer.

[0060] Preferably, the second polysilicon layer is a boron-doped polysilicon layer.

[0061] The second aspect of the present invention provides a method for preparing the double-sided TOPCon battery structure, comprising the following steps:

[0062] A BSG layer is deposited on the front side of the double-sided textured silicon substrate by PECVD, and the boron in the BSG layer is pushed into the silicon collective to form a PN junction by laser surface scanning, and then a second tunneling oxide layer and a second polysilicon layer are prepared in sequence; finally, a mask is prepared in the gate line area by laser oxidation process, and then the first tunneling oxide layer and the first polysilicon layer are prepared to obtain a semi-finished battery;

[0063] The semi-finished battery is annealed, and then a first passivation layer, a second passivation layer, a first anti-reflection layer, and a second anti-reflection layer are prepared on the back and front sides respectively, and finally a first metal electrode and a second metal electrode are prepared to obtain a double-sided TOPCon battery.

[0064] The preparation method provided by the present invention uses PECVD to deposit the BSG layer, which reduces the damage of high temperature to the silicon substrate and improves the yield and efficiency of the battery cell; at the same time, the laser reverse etching method is used to reduce the damage of the laser to the second polysilicon layer, thereby improving the passivation effect of the second polysilicon layer on the front side and improving the efficiency of the battery cell.

[0065] Furthermore, laser surface scanning is used to push the boron in the BSG layer into the silicon collective to form a shallow doping area to obtain a PN junction, and then a heavy doping area is formed in the fine gate area by SE technology. The boron doping process prepared by the method of the present invention can effectively reduce the concentric circle ratio of the silicon wafer caused by the long-term high-temperature process of the silicon substrate, thereby widening the oxygen content window of the silicon wafer and reducing the cost of the silicon wafer manufacturing end.

[0066] Preferably, the surface concentration of the shallow doping region is 1×10 18 cm -3 ~2×10 18 cm -3 .

[0067] The surface concentration of the shallow doping area is controlled at 1×10 18 cm -3 ~2×10 18 cm -3 , which can ensure lower emitter recombination in the shallow doping area, thereby increasing the battery opening voltage. 18 cm -3 , which will cause the contact resistivity of the metal area to be higher, affecting the efficiency of the cell; when the surface concentration of the shallow doped area is higher than 2×10 18 cm -3 , which will cause higher emitter recombination in the shallowly doped area, affecting the cell's turn-on voltage.

[0068] Typically, but not limiting, the surface concentration of the shallowly doped region may be, for example, 1×1018 cm -3 , 1.2×10 18 cm -3 , 1.4×10 18 cm -3 , 1.6×10 18 cm -3 , 1.8×10 18 cm -3 or 2×10 18 cm -3 , or 1×10 18 cm -3 ~2×10 18 cm -3 Any value in the range.

[0069] Preferably, the sheet resistance of the shallow doped region is 190Ω to 230Ω.

[0070] The square resistance of the shallow doped area is controlled to be 190Ω~230Ω, the PN junction formed has appropriate depth and moderate sintering window, which reduces the recombination of photogenerated carriers, increases the open circuit voltage and improves the efficiency of the battery cell.

[0071] When the square resistance of the shallow doped region is lower than 190Ω, it will lead to higher carrier recombination; when the square resistance of the shallow doped region is higher than 230Ω, it will lead to higher resistance of the battery cell.

[0072] Typically but not limiting, the sheet resistance of the shallowly doped region may be, for example, 190Ω, 200Ω, 210Ω, 220Ω or 230Ω, or any value within the range of 190Ω to 230Ω.

[0073] Furthermore, the laser surface scanning uses nanosecond laser and / or picosecond laser, and the boron source in the BSG layer is pushed into the silicon substrate by the nanosecond laser or picosecond laser to form a shallow doping area. The shallow doping area can be used as a boron source for subsequent boron doping.

[0074] Preferably, the BSG layer has a thickness of 60 nm to 140 nm.

[0075] Typically but not limiting, the thickness of the BSG layer may be, for example, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm or 140 nm, or any value within the range of 60 nm to 140 nm.

[0076] Furthermore, the double-sided textured silicon substrate is used as a template in the deposition equipment, and N 2 O.B 2 H 6 、SiH 4 and H 2 Perform vapor deposition.

[0077] Preferably, N 2 O.B 2 H 6 and SiH 4 The flow ratio is 5~9:4~10:1.

[0078] Typical but not limiting, N 2 O.B 2 H 6 and SiH 4 The flow ratio may be, for example, 5:4:1, 9:4:1, 5:10:1, 9:10:1, 7:4:1 or 7:7:1, or any value within the range of 5 to 9:4 to 10:1.

[0079] Preferably, the deposition temperature of the PECVD is 300° C. to 350° C., and the deposition time is 70 min to 90 min.

[0080] Typically but not restrictively, the deposition temperature of PECVD can be, for example, 300°C, 310°C, 320°C, 330°C, 340°C or 350°C, or any value in the range of 300°C to 350°C; the deposition time can be, for example, 70 min, 75 min, 80 min, 85 min or 90 min, or any value in the range of 70 min to 90 min.

[0081] Preferably, the H 2 The flow rate is 2000sccm~8000sccm.

[0082] Typical but not limiting, H 2 The flow rate can be, for example, 2000 sccm, 3000 sccm,

[0083] 4000sccm, 5000sccm, 6000sccm, 7000sccm or 8000sccm, or any value within the range of 2000sccm to 8000sccm.

[0084] Preferably, the SiH 4 The flow rate is 100sccm~1000sccm.

[0085] Typical but not limiting, SiH 4 The flow rate may be, for example, 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 800 sccm or 1000 sccm, or any value within the range of 100 sccm to 1000 sccm.

[0086] Furthermore, a tunnel oxide layer, a polysilicon layer and an anti-reflection layer are prepared by a PECVD deposition process.

[0087] Preferably, the tunnel oxide layer includes a first tunnel oxide layer and / or a second tunnel oxide layer.

[0088] Preferably, the polysilicon layer includes a first polysilicon layer and / or a second polysilicon layer.

[0089] Preferably, the anti-reflection layer includes a first anti-reflection layer and / or a second anti-reflection layer.

[0090] Furthermore, a passivation layer is prepared by atomic layer deposition.

[0091] Preferably, the passivation layer includes a first passivation layer and / or a second passivation layer.

[0092] Furthermore, the annealing treatment is performed using a tubular annealing process.

[0093] Preferably, the method further comprises a polishing and cleaning process after masking and before forming the first tunneling oxide layer, removing the mask in the non-gate line area and polishing the velvet surface on the back side of the silicon substrate.

[0094] The present invention is further described below by specific examples and comparative examples, but it should be understood that these examples are only used for more detailed description and should not be understood as limiting the present invention in any form. The raw materials used in the examples and comparative examples of the present invention, if no specific conditions are specified, are carried out according to conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used without indicating the manufacturer are all conventional products that can be purchased commercially.

[0095] Example 1

[0096] This embodiment provides a double-sided TOPCon battery, and the process steps are as follows:

[0097] 1. Perform double-sided texturing on the silicon substrate, and then deposit a 100nm thick BSG borosilicate glass layer on the front side of the silicon substrate by PECVD.

[0098] In the PECVD deposition equipment, a double-sided textured silicon substrate is used as a template and N 2 O.B 2 H 6 、SiH 4 and H 2 Vapor deposition, N 2 O.B 2 H 6 and SiH 4 The flow ratio of H is 7:7:1. The deposition temperature is 330℃ and the deposition time is 80min; 2The flow rate is 5000sccm, SiH 4 The flow rate is 500sccm.

[0099] 2. The laser surface scanning process is used to push the boron source in the BSG layer into the silicon substrate to form a shallow doping area and then obtain a PN junction. The surface concentration of the shallow doping area is 1×10 18 cm -3 , the square resistance is 213Ω.

[0100] 3. Use laser patterning process to remove the BSG layer in the gate line area, and clean and polish the suede surface in the gate line area.

[0101] 4. Use PECVD to prepare a silicon oxide layer and a boron-doped polysilicon layer in the gate line area; continue to use the laser oxidation process to prepare a mask in the gate line area, then clean the non-gate line area, remove the boron-doped polysilicon layer, and polish the back velvet surface.

[0102] 5. Continue to use the PECVD process to prepare a silicon oxide layer and a phosphorus-doped polysilicon layer (PSG layer) on the back side. After completion, perform tubular annealing on the silicon wafer; after annealing, polish and clean to remove the BSG layer on the front side and the PSG layer on the back side.

[0103] 6. Continue to use atomic layer deposition to prepare aluminum oxide layers on both sides of the silicon wafer; use PECVD process to prepare silicon nitride layer, and finally metallize the silicon wafer to obtain double-sided TOPCon cells.

[0104] Example 2

[0105] This embodiment provides a double-sided TOPCon cell. The difference from the first embodiment is that the thickness of the BSG borosilicate glass layer is 60 nm, and the surface concentration of the shallow doping area is 2×10 18 cm -3 , the square resistance is 190Ω, and the remaining steps are the same as those in Example 1, which will not be repeated here.

[0106] Example 3

[0107] This embodiment provides a double-sided TOPCon battery. The difference from Embodiment 1 is that the thickness of the BSG borosilicate glass layer is 140 nm, the square resistance of the shallow doped region is 230 Ω, and the remaining steps are the same as those in Embodiment 1 and will not be repeated here.

[0108] Example 4

[0109] This embodiment provides a double-sided TOPCon cell. The difference from the embodiment 1 is that the surface concentration of the shallow doping area is 1×10 17 cm -3 The remaining steps are the same as those in Example 1 and will not be described again.

[0110] Example 5

[0111] This embodiment provides a double-sided TOPCon cell. The difference from the embodiment 1 is that the surface concentration of the shallow doping area is 5×10 18 cm -3 The remaining steps are the same as those in Example 1 and will not be described again.

[0112] Example 6

[0113] This embodiment provides a double-sided TOPCon battery. The difference from Embodiment 1 is that the square resistance of the shallow doped region is 150Ω. The remaining steps are the same as those in Embodiment 1 and will not be repeated here.

[0114] Example 7

[0115] This embodiment provides a double-sided TOPCon battery. The difference from Embodiment 1 is that the square resistance of the shallow doped region is 280Ω. The remaining steps are the same as those in Embodiment 1 and will not be repeated here.

[0116] Example 8

[0117] This embodiment provides a double-sided TOPCon cell. The difference from the embodiment 1 is that in step 2, a high-temperature boron diffusion process is used to push the boron source in the BSG layer into the silicon substrate to form a shallow doping area. The surface concentration of the shallow doping area is 3×10 18 cm -3 , the square resistance is 230Ω. The remaining steps and methods are the same as those in Example 1 and will not be described again.

[0118] Comparative Example 1

[0119] This comparative example provides a TOPCon battery. The difference from Example 1 is that a laser patterning process is used to open the film directly on the silicon substrate after texturing, and then step 4 and subsequent steps are entered. The remaining methods and steps are the same as those in Example 1 and will not be repeated here.

[0120] Comparative Example 2

[0121] This comparative example provides a TOPCon battery, which is different from Example 1 in that in step 4, no mask preparation is required, and no cleaning of the non-gridline area is required, and only the back velvet surface is polished. The remaining methods and steps are the same as those in Example 1 and will not be repeated here.

[0122] Test Case

[0123] The TOPCon batteries obtained in the examples and comparative examples were subjected to performance tests, and the obtained data are shown in Table 1 below.

[0124] Table 1

[0125]

[0126] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A double-sided TOPCon battery structure, characterized in that: including a silicon substrate; The back side of the silicon substrate is provided with a first tunneling oxide layer, a first polysilicon layer, a first passivation layer, a first anti-reflection layer and a first metal electrode in sequence from inside to outside; The front side of the silicon substrate is provided with a metal area and a non-metal area; The metal area is provided with a second tunneling oxide layer, a second polysilicon layer, a second passivation layer, a second anti-reflection layer and a second metal electrode in sequence from the inside to the outside; The non-metallic area is provided with a boron diffusion emitter layer, a second passivation layer and a second anti-reflection layer in sequence from the inside to the outside; The method for preparing the double-sided TOPCon battery structure comprises the following steps: The front side of the double-sided textured silicon substrate is deposited with a BSG layer by PECVD, and the thickness of the BSG layer is 60nm~140nm; the boron in the BSG layer is pushed into the silicon collective by laser surface scanning to form a shallow doping area to obtain a PN junction, and the surface concentration of the shallow doping area is 1×10 18 cm -3 ~2×10 18 cm -3 , the square resistance is 190Ω~230Ω; then the second tunnel oxide layer and the second polysilicon layer are prepared in sequence; finally, a mask is prepared on the second polysilicon layer by a laser oxidation process, and then the first tunnel oxide layer and the first polysilicon layer are continued to be prepared to obtain a semi-finished battery; The semi-finished battery is annealed, and then a first passivation layer, a second passivation layer, a first anti-reflection layer, and a second anti-reflection layer are prepared on the back and front sides respectively, and finally a first metal electrode and a second metal electrode are prepared to obtain a double-sided TOPCon battery.

2. The double-sided TOPCon battery structure according to claim 1, characterized in that: The material of the first tunneling oxide layer and / or the second tunneling oxide layer includes silicon oxide.

3. The double-sided TOPCon battery structure according to claim 1, characterized in that: The material of the first passivation layer and / or the second passivation layer includes aluminum oxide.

4. The double-sided TOPCon battery structure according to claim 1, characterized in that: The material of the first anti-reflection layer and / or the second anti-reflection layer includes silicon nitride.

5. The double-sided TOPCon battery structure according to claim 1, characterized in that: The front side is a pyramid-shaped surface.

6. The double-sided TOPCon battery structure according to claim 1, characterized in that: The first polysilicon layer is a phosphorus-doped polysilicon layer.

7. The double-sided TOPCon battery structure according to claim 1, characterized in that: The second polysilicon layer is a boron-doped polysilicon layer.

8. The double-sided TOPCon battery structure according to claim 1, characterized in that: The laser surface scanning uses nanosecond laser and / or picosecond laser.

9. The double-sided TOPCon battery structure according to claim 1, characterized in that: In the deposition equipment, a double-sided textured silicon substrate is used as a template, and N2O, B2H6, SiH4 and H2 are introduced for vapor deposition.

10. The double-sided TOPCon battery structure according to claim 9, characterized in that: The flow ratio of N2O, B2H6 and SiH4 is 5~9:4~10:

1.

11. The double-sided TOPCon battery structure according to claim 1, characterized in that: The deposition temperature of the PECVD is 300° C. to 350° C., and the deposition time is 70 min to 90 min.

12. The double-sided TOPCon battery structure according to claim 9, characterized in that: The flow rate of H2 is 2000sccm~8000sccm.

13. The double-sided TOPCon battery structure according to claim 9, characterized in that: The flow rate of SiH4 is 100 sccm~1000 sccm.

14. The double-sided TOPCon battery structure according to any one of claims 1 to 13, characterized in that: The tunnel oxide layer, the polysilicon layer and the anti-reflection layer are prepared by a PECVD deposition process.

15. The double-sided TOPCon battery structure according to any one of claims 1 to 13, characterized in that: The tunneling oxide layer includes a first tunneling oxide layer and / or a second tunneling oxide layer.

16. The double-sided TOPCon battery structure according to any one of claims 1 to 13, characterized in that: The polysilicon layer includes a first polysilicon layer and / or a second polysilicon layer.

17. The double-sided TOPCon battery structure according to any one of claims 1 to 13, characterized in that: The anti-reflection layer includes a first anti-reflection layer and / or a second anti-reflection layer.

18. The double-sided TOPCon battery structure according to any one of claims 1 to 13, characterized in that: The passivation layer was prepared by atomic layer deposition.

19. The double-sided TOPCon battery structure according to any one of claims 1 to 13, characterized in that: The passivation layer includes a first passivation layer and / or a second passivation layer.

20. The double-sided TOPCon battery structure according to any one of claims 1 to 13, characterized in that: The annealing treatment is performed using a tubular annealing process.

21. The double-sided TOPCon battery structure according to any one of claims 1 to 13, characterized in that: The method also includes a polishing and cleaning process after the mask and before the first tunneling oxide layer is prepared, removing the mask in the non-gate line area and polishing the velvet surface on the back side of the silicon substrate.

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