Array substrate and display panel

Abstract

The application belongs to the field of display panels, and provides an array substrate and a display panel, wherein the array substrate comprises a substrate, a first signal line and a first pattern layer; the first pattern layer is located on the side of the first signal line away from the substrate, the first pattern layer comprises an electrostatic discharge layer and a main pattern layer, the electrostatic discharge layer is connected with the first signal line through a first via, the main pattern layer is connected with the first signal line through a second via, the distance from the second via to the first end of the first signal line is smaller than the distance from the first via to the first end of the first signal line, and the distance from the first via to the second via is smaller than the distance from the first via to the second end of the first signal line. In the process of discharge, more static charges are discharged through the first via, and fewer static charges are discharged through the second via, thereby reducing the risk of the second via being burned by static electricity or even being burned out, and being conducive to improving the yield of the array substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display panels, and in particular to an array substrate and a display panel. BACKGROUND

[0002] The array substrate is an important structure in various display devices, such as a Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and an Organic Light-Emitting Diode (OLED) display device.

[0003] The array substrate includes a substrate and a circuit formed on the surface of the substrate. The circuit structure on the surface of the array substrate is relatively fine, and the process flow for preparation is relatively long. The surface of the substrate is usually distributed with signal lines, and the signal lines are electrically connected to other film layers through vias. In the process of preparing other film layers, static charges accumulated in the signal lines are likely to form electrostatic discharge at the vias, resulting in the vias being burned or even destroyed, and reducing the yield of the array substrate. SUMMARY

[0004] Embodiments of the present application provide an array substrate and a display panel, which can reduce the possibility that the vias connecting the signal lines and the electrostatic protection circuit are burned out due to electrostatic discharge, and are beneficial to improving the yield of the array substrate.

[0005] A first aspect of embodiments of the present application provides an array substrate, which includes:

[0006] a substrate;

[0007] a first signal line located on the surface of the substrate and having opposite first and second ends;

[0008] a first pattern layer located on the side of the first signal line away from the substrate, the first pattern layer including an electrostatic discharge layer and a main pattern layer, the electrostatic discharge layer being connected to the first signal line through a first via, the main pattern layer being connected to the first signal line through a second via, the distance from the second via to the first end being less than the distance from the first via to the first end, and the distance from the first via to the second via being less than the distance from the first via to the second end.

[0009] In some examples, the first signal line includes a linear body and a first connecting portion, the first connecting portion being located on the side of the linear body and connected to the linear body, and the first via connecting the electrostatic discharge layer and the first connecting portion.

[0010] In some examples, the first signal line further includes a second connection portion, the second connection portion is located at an end of the linear body and connected to the linear body, and the second via connects the main pattern layer and the second connection portion.

[0011] In some examples, the first signal line includes a plurality of the first connection portions, each of which is connected to the linear body; the first pattern layer includes a plurality of the electrostatic release layers, each of which is arranged in a one-to-one correspondence with the plurality of the first connection portions; the array substrate has a plurality of the first vias, and the electrostatic release layers are connected to the corresponding first connection portions through the first vias.

[0012] In some examples, two of the plurality of first connection portions are symmetrically arranged with respect to the linear body.

[0013] In some examples, the array substrate includes a plurality of first signal lines arranged in parallel, and a plurality of first connection portions located between adjacent first signal lines are staggered.

[0014] In some examples, the orthographic projection of the electrostatic release layer on the base substrate is located within the orthographic projection of the first connecting portion on the base substrate.

[0015] In some examples, the main pattern layer includes a source-drain pattern layer, and the source-drain pattern layer is connected to the second via hole;

[0016] The array substrate includes an electrostatic protection circuit, which includes a diode ring. The diode ring is located in the non-display area of ​​the base substrate. The diode ring includes a gate pattern layer and the source and drain pattern layer. The gate pattern layer is located on a side of the source and drain pattern layer close to the base substrate. The gate pattern layer and the source and drain pattern layer are connected through a third via.

[0017] In some examples, the gate pattern layer and the first signal line are arranged in the same layer.

[0018] A second aspect of the embodiments of the present application further provides a display panel, comprising a cell substrate and the array substrate as described in the first aspect, wherein the cell substrate is arranged opposite to the array substrate.

[0019] The first aspect of the embodiment of the present application sets the first via and the second via connected with the first signal line, wherein the electrostatic discharge layer in the first pattern layer is connected with the first signal line through the first via, and the main pattern layer in the first pattern layer is connected with the first signal line through the second via, so that in the process of preparing the first pattern layer, the electrostatic charge accumulated in the first signal line can be discharged through the first via and the second via. Since the distance from the second via to the first end of the first signal line is less than the distance from the first via to the first end of the first signal line, and the distance from the first via to the second via is less than the distance from the first via to the second end of the first signal line, in the process of discharging, more electrostatic charge is discharged through the first via, and less electrostatic charge is discharged through the second via, thereby reducing the risk of the second via being electrostatically burned or even destroyed, and facilitating to improve the yield of the array substrate.

[0020] It can be understood that the beneficial effects of the second aspect described above can be referred to the related description in the first aspect described above, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0022] Figure 1 is a top view of an array substrate provided by the first embodiment of the present application;

[0023] Figure 2 is an equivalent circuit diagram of an electrostatic protection circuit provided by the present application;

[0024] Figure 3 is Figure 1 a partial enlarged view of

[0025] Figure 4 is Figure 3 the A-A sectional view of

[0026] Figure 5 is a structural schematic view of an array substrate provided by the second embodiment of the present application;

[0027] Figure 6 is a structural schematic view of a non-display area of an array substrate provided by the second embodiment of the present application;

[0028] Figure 7 is Figure 6 a partial enlarged view of

[0029] Figure 8is an equivalent circuit diagram of an electrostatic protection circuit of an array substrate provided by Embodiment Three of the present application.

[0030] Figure 9 is a structural schematic diagram of an array substrate provided by Embodiment Three of the present application.

[0031] Figure 10 is a structural schematic diagram of an array substrate provided by Embodiment Four of the present application.

[0032] Reference Signs:

[0033] Substrate substrate: 10; display area: 10a; non-display area: 10b; first signal line: 11; linear body: 111; first connecting part: 112; second connecting part: 113; electrostatic protection circuit: 20; second signal line: 21; diode ring: 22; first pattern layer: 200; electrostatic release layer: 201; main pattern layer: 202; gate pattern layer: 221; source-drain pattern layer: 222; active pattern layer: 223; first gate: 2211; second gate: 2212; third gate: 2213; fourth gate: 2214; third connecting part: 2215; first active layer: 2231; second active layer: 2232; third active layer: 2233; fourth active layer: 2234; first source-drain layer: 2221; second source-drain layer: 2222; third source-drain layer: 2223; first pole: 222a; second pole: 222b; first insulating layer: 31; second insulating layer: 32; third insulating layer: 33; fourth insulating layer: 34; first via hole: 31d; second via hole: 31a; third via hole: 31b; fourth via hole: 31c; gate driving unit: 40; bridging line: 41. DETAILED DESCRIPTION

[0034] In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc., in order to provide a thorough understanding of the present embodiments. However, it will be apparent to those skilled in the art that the present embodiments can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present embodiments.

[0035] It should also be understood that the term "and / or" as used herein refers to any one or more of the associated listed items, and all possible combinations of the items, and includes these combinations.

[0036] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0037] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0038] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0039] References to "one embodiment" or "some embodiments" in the present specification mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized. "Multiple" means two or more.

[0040] Example 1

[0041] Figure 1 : is a top view schematic diagram of an array substrate provided in Example 1 of the present application. Figure 1 As shown, the array substrate includes a base substrate 10 and a circuit formed on one side of the base substrate 10. The base substrate 10 serves as a carrier and has a display area 10a and a non-display area 10b. The display area 10a is generally located in the middle of the base substrate 10, and the non-display area 10b is generally located at the edge of the base substrate 10. A first signal line 11 and an electrostatic protection circuit 20 are provided in the non-display area 10b of the base substrate 10. The first end of the first signal line 11 is connected to the electrostatic protection circuit 20. The second end of the first signal line 11 can extend to the edge of the base substrate 10 to facilitate connection to other structures, such as a structure used for binding.

[0042] Figure 2 is an equivalent circuit diagram of the electrostatic protection circuit provided by an embodiment of the present application. As shown in Figure 2 , the electrostatic protection circuit 20 can include a second signal line 21 and a plurality of diode rings (DR) 22. The diode ring 22 can be located in the non-display area 10b.

[0043] Figure 3 is a partial enlarged schematic view in Figure 1 . As shown in Figure 3 , the diode ring 22 includes a gate pattern layer 221, a source-drain pattern layer 222, and an active pattern layer 223. The active pattern layer 223 and the source-drain pattern layer 222 are both located on the side of the gate pattern layer 221 away from the substrate 10. The source-drain pattern layer 222 is connected to the first signal line 11 through a second via 31a, and is also connected to the gate pattern layer 221 through a third via 31b.

[0044] In an embodiment of the present application, the gate pattern layer 221, the active pattern layer 223, and the source-drain pattern layer 222 form two thin film transistors.

[0045] The gate pattern layer 221 includes a first gate 2211 and a second gate 2212.

[0046] The active pattern layer 223 includes a first active layer 2231 and a second active layer 2232. The first active layer 2231 is located on the side of the first gate 2211 away from the substrate 10, and the first active layer 2231 at least partially overlaps the first gate 2211. The second active layer 2232 is located on the side of the second gate 2212 away from the substrate 10, and the second active layer 2232 at least partially overlaps the second gate 2212.

[0047] In an embodiment of the present application, two structural overlaps refer to the existence of overlap in the orthographic projection of the two structures on the surface of the substrate 10, that is, at least part of the orthographic projection of one structure on the surface of the substrate 10 is located within the orthographic projection of the other structure on the surface of the substrate 10. For example, the partial overlap of the second active layer 2232 and the second gate 2212 refers to the existence of overlap in the orthographic projection of the second active layer 2232 on the surface of the substrate 10 and the orthographic projection of the second gate 2212 on the surface of the substrate 10, that is, at least part of the orthographic projection of the second active layer 2232 on the surface of the substrate 10 is located within the orthographic projection of the second gate 2212 on the surface of the substrate 10.

[0048] The source-drain pattern layer 222 includes a first source-drain layer 2221 and a second source-drain layer 2222. The first source-drain layer 2221 includes a first pole 222a and a second pole 222b. The second source-drain layer 2222 also includes a first pole 222a and a second pole 222b. The first pole 222a is one of a source and a drain, and the second pole 222b is the other of the source and the drain.

[0049] The first gate 2211 is connected to the first signal line 11. There is a gap between the first gate 2211 and the second gate 2212, and between the second gate 2212 and the first signal line 11.

[0050] The first source-drain layer 2221 partially overlaps the first gate 2211 and the second gate 2212. The first pole 222a of the first source-drain layer 2221 partially overlaps the first gate 2211 and partially overlaps the first active layer 2231. The second pole 222b of the first source-drain layer 2221 partially overlaps the second gate 2212 and partially overlaps the second active layer 2232.

[0051] The second source-drain layer 2222 partially overlaps the first gate 2211 and the second gate 2212. The first pole 222a of the second source-drain layer 2222 partially overlaps the second gate 2212 and partially overlaps the second active layer 2232. The second pole 222b of the second source-drain layer 2222 partially overlaps the first gate 2211 and partially overlaps the first active layer 2231.

[0052] Figure 4 is Figure 3 the A-A cross-sectional view of the array substrate. As shown in Figure 4 The array substrate further includes a first insulating layer 31. The first insulating layer 31 is located on the side of the first signal line 11 away from the substrate 10. The first insulating layer 31 has a second via hole 31a exposing the first signal line 11. The first signal line 11 is connected to the first source-drain layer 2221 through the second via hole 31a.

[0053] In the embodiments of the present application, unless otherwise specified, the connection through the via hole refers to the electrical connection achieved by the structure in the via hole. The structure in the via hole for achieving the electrical connection can be part of either of the two structures at the two ends of the via hole, or other structures other than the two structures at the two ends of the via hole. For example, the connection of the first signal line 11 to the first source-drain layer 2221 through the second via hole 31a means that the two structures of the first signal line 11 and the first source-drain layer 2221 form an electrical connection, and the structure in the second via hole 31a for achieving the electrical connection of the first signal line 11 to the first source-drain layer 2221 is the part of the first source-drain layer 2221 located in the second via hole 31a.

[0054] The first insulating layer 31 further has a third via hole 31 b , and the second source-drain electrode layer 2222 is connected to the second gate 2212 through the third via hole 31 b .

[0055] The first signal line 11 is generally long. The longer it is, the more likely it is to accumulate charge during the fabrication of the array substrate. This results in the electrostatic charge accumulated in the first signal line 11 being released through the second via 31a during the fabrication of structures connected to the first signal line 11 via vias, for example, during the fabrication of the first source / drain electrode layer 2221. This discharge creates an electrostatic discharge at the second via 31a, potentially burning or even destroying the second via 31a, thus destroying the connection between the first signal line 11 and the first source / drain electrode layer 2221. This is directly manifested as the second via 31a of the array substrate becoming black, leading to abnormal functionality of the array substrate and directly affecting the yield of the array substrate.

[0056] Example 2

[0057] Figure 5 This is a structural diagram of an array substrate provided in Example 2 of this application. Figure 5 In the array substrate shown, the array substrate includes a first pattern layer 200, which is located on the side of the first signal line 11 away from the base substrate 10. The first pattern layer 200 includes an electrostatic release layer 201 and a main pattern layer 202. The main pattern layer 202 may include the aforementioned source and drain pattern layer 222.

[0058] The electrostatic release layer 201 is connected to the first signal line 11 through a first via 31d, and the main pattern layer 202 is connected to the first signal line 11 through a second via 31a. The first signal line 11 has a first end and a second end opposite each other. The distance from the second via 31a to the first end of the first signal line 11 is smaller than the distance from the first via 31d to the first end of the first signal line 11. The distance from the first via 31d to the second via 31a is smaller than the distance from the first via 31d to the second end of the first signal line 11.

[0059] The distance from the first via 31d to the first end of the first signal line 11, the distance from the second via 31a to the first end of the first signal line 11, the distance from the first via 31d to the second via 31a, and the distance from the first via 31d to the second end of the first signal line 11 all refer to the length of the path along the first signal line 11, not the straight-line distance between them. For example, the distance from the first via 31d to the second via 31a refers to the length of the path extending from the first via 31d along the first signal line 11 to the second via 31a. It can be assumed that if an electrical signal is input from the first via 31d and transmitted to the second via 31a, the length of the path that the electrical signal travels from the first via 31d along the first signal line 11 to the second via 31a is the distance from the first via 31d to the second via 31a.

[0060] In the embodiment of the present application, the first via 31d and the second via 31a are distributed near the same end of the first signal line 11, and the second via 31a is closer to the end of the first signal line 11. During the process of preparing the first pattern layer 200, the electrostatic charge accumulated in the first signal line 11 is released along the first signal line 11 through the first via 31d and the second via 31a. Due to the positional difference between the first via 31d and the second via 31a, the second via 31a is closer to the end of the first signal line 11. Therefore, more electrostatic charge is released through the first via 31d, reducing the electrostatic charge released through the second via 31a. This reduces the risk of the second via 31a being burned or even destroyed by static electricity, thereby maintaining a normal connection between the first signal line 11 and the main pattern layer 202, which is beneficial for improving the yield of the array substrate.

[0061] In the embodiment of the present application, the gate pattern layer 221 and the first signal line 11 are arranged in the same layer.

[0062] Since they are arranged in the same layer, the gate pattern layer 221 and the first signal line 11 can be formed by the same patterning process, thereby saving the process.

[0063] like Figure 5 As shown, the first signal line 11 includes a linear body 111 and a first connecting portion 112. The first connecting portion 112 is located on the side of the linear body 111 and connected to the linear body 111. The first via 31d connects the electrostatic release layer 201 and the first connecting portion 112.

[0064] In the process of electrostatic discharge, if the static electricity is strong, in addition to the possibility of causing the first via hole 31d to be damaged by static electricity, it is also possible to cause the part where the first signal line 11 is connected with the first via hole 31d to be damaged, thereby affecting the transmission of the electrical signal in the first signal line 11. In the example, by arranging the first connecting portion 112 on the side of the linear body 111, the first connecting portion 112 is connected with the first via hole 31d, so that even if the first connecting portion 112 is damaged by static electricity, the linear body 111 can still remain intact, so that the electrical signal can still be normally transmitted in the first signal line 11.

[0065] As an example, the width of the first connecting portion 112 is greater than the width of the linear body 111.

[0066] In the embodiment of the application, the width of the linear body 111 refers to the distance between the opposite two side edges of the linear body 111 in the direction parallel to the substrate 10 and perpendicular to the linear body 111. The width of the first connecting portion 112 refers to the distance between the opposite two side edges of the first connecting portion 112 in the direction parallel to the substrate 10 and perpendicular to the linear body 111.

[0067] The linear body 111 is arranged to be thin, which is beneficial to reduce the space occupied by the first signal line 11 and facilitate wiring. The first connecting portion 112 is arranged to be wide, which can facilitate the arrangement of the first via hole 31d with a large area, and avoid that the area of the first via hole 31d is too small to affect the release of static electricity.

[0068] As shown in Figure 5 , the orthogonal projection of the static electricity release layer 201 on the substrate 10 is located within the orthogonal projection of the first connecting portion 112 on the substrate 10.

[0069] The static electricity release layer 201 is a part of the pattern reserved in the patterning process of preparing the main pattern layer 202, and the circuit structure in the array substrate is complex. The static electricity release layer 201 and other structures in the array substrate can form a capacitor, which can have a certain adverse effect. By making the static electricity release layer 201 not exceed the boundary of the first connecting portion 112, the static electricity release layer 201 is arranged to be small, which is beneficial to reduce the possible adverse effects.

[0070] As shown in Figure 5 , the first signal line 11 further includes a second connecting portion 113. The second connecting portion 113 is located at the end of the linear body 111 and is connected with the linear body 111. The second via hole 31a connects the main pattern layer 202 with the second connecting portion 113.

[0071] In the example, by setting the second connection part 113 at the end position of the linear body 111, the distance from the second via hole 31a to the second end of the first signal line 11 is as far as possible, more static charges can be released through the first via hole 31d, the static charges released through the second via hole 31a is further reduced, thereby further reducing the risk of static burnout or even burning of the second via hole 31a, and improving the yield of the array substrate.

[0072] The width of the second connection part 113 is greater than the width of the linear body 111, the second connection part 113 partially overlaps the first source-drain layer 2221, and is connected through the second via hole 31a.

[0073] In the embodiment of the application, the width of the second connection part 113 refers to the distance between the opposite two sides of the second connection part 113 in the direction parallel to the substrate 10 and perpendicular to the linear body 111.

[0074] The linear body 111 is set to be thin, which is conducive to reducing the space occupied by the first signal line 11 and facilitating wiring. The second connection part 113 is set to be wide, which can facilitate the setting of the second via hole 31a with a larger area.

[0075] As an example, the first gate 2211 can be connected with the second connection part 113, and the two are an integral structure.

[0076] As shown in Figure 5 , the gate pattern layer 221 further includes a third connection part 2215. The third connection part 2215 is connected with the second gate 2212, the third connection part 2215 partially overlaps the second source-drain layer 2222, and is connected through the third via hole 31b.

[0077] The third connection part 2215 provides a relatively large area to facilitate the connection of the gate pattern layer 221 and the second source-drain layer 2222 through the third via hole 31b.

[0078] As shown in Figure 5 , the static protection circuit further includes a second signal line 21, and the second signal line 21 is arranged and connected with the source-drain pattern layer 222 in the same layer.

[0079] In the embodiment of the application, the second signal line 21 is connected with the second source-drain layer 2222.

[0080] The second signal line 21 is used for releasing static electricity. Exemplarily, the second signal line 21 can be a common signal line, that is, a common signal line is multiplexed to release static electricity. In other possible implementations, the second signal line 21 can also be a signal line other than the common signal line.

[0081] Figure 6is a structural schematic view of a non-display area of an array substrate provided in Embodiment Two of the present application. As shown in Figure 6 The array substrate further includes a plurality of gate driving units 40, and the first pattern layer 200 further includes a bridge line 41. The plurality of gate driving units 40 are located between the first signal lines 11 and the display area 10a, and the plurality of gate driving units 40 are arranged in sequence along the length direction of the first signal lines 11.

[0082] The circuit on the surface of the substrate 10 generally includes pixel circuits located in the display area 10a and driving circuits located in the non-display area 10b. The driving circuits in the non-display area 10b may, for example, include a gate driver on array (GOA) circuit, which may, in turn, include gate driving units and bus line units, the gate driving units being connected to the pixel circuits located in the display area 10a, and the bus line units may include clock signal lines (CK). As an example, in the present application, the first signal lines 11 may be clock signal lines.

[0083] The bridge line 41 may be arranged in the same layer as the source-drain pattern layer 222, and the plurality of first signal lines 11 and the plurality of gate driving units 40 are connected through the bridge line 41. Since they are arranged in the same layer, the bridge line 41 and the source-drain pattern layer 222 can be formed by the same patterning process, thereby achieving the purpose of saving processes.

[0084] Figure 7 is a partial enlarged schematic view of Figure 6 . As shown in Figure 7 Each first signal line 11 includes a first connecting portion 112, and for each first signal line 11, the first connecting portion 112 is located on the same side of the linear main body 111 connected thereto. For example, in each first signal line 11, the first connecting portion 112 is located on the side of the linear main body 111 connected thereto close to the display area 10a, or on the side of the linear main body 111 connected thereto away from the display area 10a.

[0085] Exemplarily, the first signal line 11 may be a single-layer structure made of a metal material, for example, a single-layer structure formed of copper (Cu), or a multi-layer structure made of a metal material, for example, a multi-layer structure of Al / Mo / MTD, i.e., a multi-layer structure of an aluminum layer, a molybdenum layer, and a molybdenum-nickel-titanium alloy layer.

[0086] The first insulating layer 31 may be located in the display area 10a and the non-display area 10b. Exemplarily, the first insulating layer 31 may be a gate insulating layer. The first insulating layer 31 may be made of inorganic non-metallic materials, for example, the first insulating layer 31 may include at least one of a silicon nitride layer and a silicon oxide layer. Exemplarily, the first insulating layer 31 includes SiN xSiN layer and a SiO layer are stacked on the SiN layer x SiO layer is located on the side of the SiN layer away from the substrate 10 x layer.

[0087] Exemplarily, the thin film transistors in the electrostatic protection circuit 20 can be oxide thin film transistors, and the first active layer 2231 and the second active layer 2232 can be metal oxide semiconductor layers. In some examples, the thin film transistors can also be polysilicon thin film transistors, amorphous silicon thin film transistors, or other thin film transistors.

[0088] As shown in FIG. 1, the array substrate further includes a second insulating layer 32, a third insulating layer 33, and a fourth insulating layer 34. The second insulating layer 32 is located on the side of the source-drain electrode pattern layer 222 away from the substrate 10, the third insulating layer 33 is located on the side of the second insulating layer 32 away from the substrate 10, and the fourth insulating layer 34 is located on the side of the third insulating layer 33 away from the substrate 10. Figure 4 The second insulating layer 32 can be located in the display area 10a and the non-display area 10b of the substrate 10. Exemplarily, the second insulating layer 32 can be a passivation layer (PVX), and the second insulating layer 32 can be made of inorganic non-metallic materials, for example, the second insulating layer 32 can include at least one of a silicon nitride layer and a silicon oxide layer. Exemplarily, the second insulating layer 32 includes SiO x SiN layer and a SiO layer are stacked on the SiN layer x SiN layer and a SiO layer are stacked on the SiN layer x layer.

[0089] The third insulating layer 33 can be made of inorganic non-metallic materials, for example, the third insulating layer 33 can be a resin layer, a photoresist layer, or an acrylic layer. Exemplarily, the third insulating layer 33 can be a perfluoroalkoxy resin PFA.

[0090] Embodiment Three

[0091]

[0092] is an equivalent circuit diagram of an electrostatic protection circuit of an array substrate provided by Embodiment Three of the present application. As shown in FIG. 3, in the electrostatic protection circuit, the diode ring 22 includes four thin film transistors. Figure 8 is a structural schematic diagram of an array substrate provided by Embodiment Three of the present application. Compared with the array substrate shown in FIG. 2, Figure 8 in the array substrate shown in FIG. 3, the gate pattern layer 221, the active pattern layer 223, and the source-drain electrode pattern layer 222 form four thin film transistors. Figure 9 Figure 5 As shown in FIG. 3, the array substrate further includes a second insulating layer 32, a third insulating layer 33, and a fourth insulating layer 34. The second insulating layer 32 is located on the side of the source-drain electrode pattern layer 222 away from the substrate 10, the third insulating layer 33 is located on the side of the second insulating layer 32 away from the substrate 10, and the fourth insulating layer 34 is located on the side of the third insulating layer 33 away from the substrate 10. Figure 9

[0093] As shown in FIG. 3, the array substrate further includes a second insulating layer 32, a third insulating layer 33, and a fourth insulating layer 34. The second insulating layer 32 is located on the side of the source-drain electrode pattern layer 222 away from the substrate 10, the third insulating layer 33 is located on the side of the second insulating layer 32 away from the substrate 10, and the fourth insulating layer 34 is located on the side of the third insulating layer 33 away from the substrate 10. Figure 8 ​​As shown, in the array substrate, the gate pattern layer 221 further includes a third gate 2213 and a fourth gate 2214. The third gate 2213 is connected to the second gate 2212, and there is a gap between the fourth gate 2214 and the third gate 2213, and between the fourth gate 2214 and the second gate 2212.

[0094] The active pattern layer 223 further includes a third active layer 2233 and a fourth active layer 2234. The third active layer 2233 is located on a side of the third gate 2213 away from the base substrate 10, and the third active layer 2233 at least partially overlaps with the third gate 2213. The fourth active layer 2234 is located on a side of the fourth gate 2214 away from the base substrate 10, and the fourth active layer 2234 at least partially overlaps with the fourth gate 2214.

[0095] The second source-drain electrode layer 2222 partially overlaps with the first gate 2211, the second gate 2212, the third gate 2213, and the fourth gate 2214, respectively. The second source-drain electrode layer 2222 includes two first electrodes 222a and two second electrodes 222b. One first electrode 222a partially overlaps with the second gate 2212 and the second active layer 2232; the other first electrode 222a partially overlaps with the third gate 2213 and the third active layer 2233; one second electrode 222b partially overlaps with the first gate 2211 and the first active layer 2231; and the other second electrode 222b partially overlaps with the fourth gate 2214 and the fourth active layer 2234.

[0096] The source-drain pattern layer 222 further includes a third source-drain layer 2223. The third source-drain layer 2223 includes a first electrode 222a and a second electrode 222b.

[0097] The third source and drain layer 2223 partially overlaps with the third gate 2213 and the fourth gate 2214 respectively, wherein the first pole 222a of the third source and drain layer 2223 partially overlaps with the fourth gate 2214 and partially overlaps with the fourth active layer 2234; the second pole 222b of the third source and drain layer 2223 partially overlaps with the third gate 2213 and partially overlaps with the third active layer 2233.

[0098] In the embodiment of the present application, the third source-drain layer 2223 is connected to the fourth gate 2214 through a fourth via hole 31 c.

[0099] In the embodiment of the present application, the electrostatic protection circuit 20 includes more thin film transistors, and the circuit structure is more complex, and the electrostatic protection effect during the operation of the array substrate is better. The specific structure of the electrostatic protection circuit 20 can have various forms. As an example, the electrostatic protection circuit 20 provided in the embodiment of the present application has four thin film transistors. In other examples, the number of thin film transistors in the electrostatic protection circuit 20 can also be 3, 5, 6, etc.

[0100] Embodiment Four

[0101] Figure 10 is a structural schematic diagram of an array substrate provided in Embodiment Four of the present application. Compared with the array substrate shown in Figure 5 , in the array substrate shown in Figure 10 , the first signal line 11 includes a plurality of first connection portions 112, and the plurality of first connection portions 112 are respectively connected with the linear body 111. The first pattern layer 200 includes a plurality of electrostatic discharge layers 201, and the plurality of electrostatic discharge layers 201 are arranged one by one corresponding to the plurality of first connection portions 112. The array substrate has a plurality of first vias 31d, and the electrostatic discharge layer 201 is connected with the corresponding first connection portion 112 through the first via 31d.

[0102] In the process of preparing the array substrate, the electrostatic charge accumulated in the first signal line 11 can be more, especially for the array substrate with a larger size, the length of the first signal line 11 is relatively long, and a large amount of electrostatic charge is more likely to be accumulated. In the case of a large amount of accumulated electrostatic charge, one first via 31d can not be enough to safely discharge the electrostatic charge, or in the process of discharging the electrostatic charge, the first via 31d can be burned by the electrostatic charge, losing the protection effect on the second via 31a, resulting in the risk of the second via 31a being burned or even burned by the electrostatic charge. In the present example, a plurality of first vias 31d are provided to discharge the electrostatic charge, which speeds up the discharge of the electrostatic charge. Even if an individual first via 31d is burned by the electrostatic charge and fails, other first vias 31d can also discharge the electrostatic charge, further reducing the risk of the second via 31a being burned or even burned by the electrostatic charge.

[0103] As an example, the first signal line 11 can include two first connection portions 112. In other possible implementations, the first signal line 11 can include three, four or more first connection portions 112. Figure 10 In the present example, only two first connection portions 112 are provided as an example.

[0104] As shown in Figure 10 , two of the plurality of first connection portions 112 connected with the same linear body 111 are symmetrically arranged about the linear body 111.

[0105] The two first connecting portions 112 are symmetrically arranged about the linear body 111. That is, the two first vias 31d are also symmetrically arranged about the linear body 111. The two symmetrically arranged first vias 31d are equidistant from the first end of the first signal line 11 and equidistant from the second end of the first signal line 11. When electrostatic charge is released, the two symmetrically arranged first vias 31d release a comparable amount of charge, reducing the risk of one of the first vias 31d being damaged by static electricity and causing failure.

[0106] like Figure 10 As shown, the array substrate includes a plurality of first signal lines 11 arranged in parallel, and a plurality of first connection portions 112 located between adjacent first signal lines 11 are staggered.

[0107] Here, the staggered distribution of the plurality of first connection portions 112 means that the plurality of first connection portions 112 are distributed in sequence in the extending direction of the linear body 111 .

[0108] In the array substrate, a plurality of first signal lines 11 are usually provided. The spacing between adjacent first signal lines 11 is relatively small, and a staggered distribution is adopted to save space.

[0109] In the aforementioned embodiments 1 to 4, although the main pattern layer 202 includes the source and drain pattern layer 222 of the electrostatic protection circuit 20, and the second via 31a is a via connecting the electrostatic protection circuit 20 and the first signal line 11, the description is given as an example, however, in other possible implementations, the main pattern layer 202 may include other pattern layers, and the second via 31a may be a via connecting the signal line and any pattern layer. As long as there is a risk of the via being burned or even destroyed by static electricity during the preparation of the array substrate, this risk can be reduced by providing the first via 31d.

[0110] Example 5

[0111] A fifth embodiment of the present application provides a display panel, which can be, but is not limited to, a display panel in a mobile phone, tablet computer, laptop computer, monitor, smart wearable device, or vehicle-mounted display device. The display panel includes a cell substrate and an array substrate, which can be any of the array substrates described in the previous embodiments.

[0112] Example 6

[0113] Embodiment 6 of the present application provides a display device, which includes the display panel of the aforementioned embodiment. The display device can be, but is not limited to, a mobile phone, a tablet computer, a laptop computer, a monitor, a smart wearable device, or a vehicle-mounted display device.

[0114] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: include: a substrate base plate (10); A first signal line (11), located on the surface of the substrate (10), having a first end and a second end opposite to each other; a first pattern layer (200) located on a side of the first signal line (11) away from the substrate (10), the first pattern layer (200) comprising an electrostatic release layer (201) and a main pattern layer (202), the electrostatic release layer (201) being connected to the first signal line (11) via a first via (31d), the main pattern layer (202) comprising a source-drain pattern layer (222), the source-drain pattern layer (222) being connected to the first signal line (11) via a second via (31a), the distance from the second via (31a) to the first end being smaller than the distance from the first via (31d) to the first end, and the distance from the first via (31d) to the second via (31a) being smaller than the distance from the first via (31d) to the second end; An electrostatic protection circuit (20) comprising a diode ring (22), the diode ring (22) being located in a non-display area (10b) of the base substrate (10), the diode ring (22) comprising a gate pattern layer (221) and a source-drain pattern layer (222), the gate pattern layer (221) being located on a side of the source-drain pattern layer (222) close to the base substrate (10), the gate pattern layer (221) and the source-drain pattern layer (222) being connected via a third via hole (31b).

2. The array substrate according to claim 1, wherein: The first signal line (11) comprises a linear body (111) and a first connecting portion (112), wherein the first connecting portion (112) is located on the side of the linear body (111) and is connected to the linear body (111), and the first via (31d) connects the electrostatic release layer (201) and the first connecting portion (112).

3. The array substrate according to claim 2, wherein: The first signal line (11) further comprises a second connecting portion (113), the second connecting portion (113) being located at an end of the linear body (111) and connected to the linear body (111), and the second via (31a) connecting the main pattern layer (202) and the second connecting portion (113).

4. The array substrate according to claim 2, wherein: The first signal line (11) includes a plurality of first connecting portions (112), and the plurality of first connecting portions (112) are respectively connected to the linear body (111); the first pattern layer (200) includes a plurality of electrostatic release layers (201), and the plurality of electrostatic release layers (201) are arranged in a one-to-one correspondence with the plurality of first connecting portions (112); the array substrate has a plurality of first via holes (31d), and the electrostatic release layers (201) are connected to the corresponding first connecting portions (112) through the first via holes (31d).

5. The array substrate according to claim 4, wherein: Two of the plurality of first connection portions (112) are symmetrically arranged with respect to the linear body (111).

6. The array substrate according to any one of claims 2 to 5, characterized in that: The array substrate comprises a plurality of first signal lines (11) arranged in parallel, and a plurality of first connection portions (112) located between adjacent first signal lines (11) are staggered.

7. The array substrate according to any one of claims 2 to 5, wherein: The orthographic projection of the electrostatic release layer (201) on the base substrate (10) is located within the orthographic projection of the first connecting portion (112) on the base substrate (10).

8. The array substrate according to any one of claims 1 to 5, wherein: The gate pattern layer (221) and the first signal line (11) are arranged in the same layer.

9. A display panel, characterized in that: It comprises a cell substrate and the array substrate according to any one of claims 1 to 8, wherein the cell substrate is arranged opposite to the array substrate.

Images