A GaN transistor with a P-GaN source extension and a method for preparing the same

Abstract

The present invention discloses a GaN transistor with a P-GaN source extension, which relates to the field of semiconductor technology and includes: an epitaxial structure, a source electrode, a gate electrode, and a drain electrode. The epitaxial structure includes a channel layer, a barrier layer on one side of the channel layer, and a P-GaN extension layer and a P-type layer on the surface of the barrier layer far from the channel layer. Among them, the source electrode and the drain electrode are oppositely arranged at both ends of the surface of the barrier layer far from the channel layer. In the first direction, the P-GaN extension layer is located on the side of the source electrode close to the drain electrode, the P-type layer is located between the P-GaN extension layer and the drain electrode, the gate electrode is located on the surface of the P-type layer far from the barrier layer, and the P-GaN extension layer, the barrier layer, and the channel layer form a pin diode structure. The first direction is the direction from the source electrode to the drain electrode. The introduced P-GaN extension layer in the present invention can deplete a part of the two-dimensional electron gas below it, thereby reducing the short-circuit saturation current and enhancing the short-circuit reliability of the P-GaN transistor.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a GaN transistor with a P-GaN source extension and a preparation method thereof. Background Art

[0002] GaN high electron mobility transistors (HEMTs) have been widely used in power electronic systems due to their higher power density, higher breakdown voltage, lower on-resistance, and faster switching speed. An enhancement-mode GaN HEMT with a P-GaN gate layer and a Schottky-type gate contact is a commercially available GaN power device with great application potential. With the commercialization of P-GaN HEMTs, their short-circuit (SC) capability in various applications such as motor drives and automotive power systems is crucial.

[0003] Generally, an accidental short circuit of the load, crosstalk in the phase leg circuit, or other external fault conditions can cause a short circuit. During a short circuit, since there is no load for current limiting and voltage bearing in the power loop, the loop current will increase rapidly, reaching the short-circuit saturation current of the power device. The loop bus voltage is borne by the power device, which causes the power device to simultaneously bear high voltage and large current stresses, generate a large amount of heat in a short time, and the electrical performance of the power device will degenerate or even the device will be burned out.

[0004] To solve the above problems, the prior art has added an overcurrent protection circuit and an external current limiting element in the circuit. However, this method will increase the circuit complexity; for the device itself, an SC-class GaN cascode structure can be adopted, that is, by removing part of the gate channel to reduce the saturation current. Although this method improves the short-circuit capability to a certain extent, it will also increase the on-resistance. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a GaN transistor with a P-GaN source extension and a preparation method thereof. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] In a first aspect, the present invention provides a GaN transistor with a P-GaN source extension, including: an epitaxial structure 1, a source electrode, a gate electrode, and a drain electrode. The epitaxial structure 1 includes a channel layer 11, a barrier layer 12 located on one side of the channel layer 11, and a P-GaN extension layer 13 and a P-type layer 14 located on the surface of the barrier layer 12 away from the channel layer 11; wherein,

[0007] The source electrode and the drain electrode are oppositely arranged at both ends of the surface of the barrier layer 12 away from the channel layer 11. In the first direction, the P-GaN extension layer 13 is located on the side of the source electrode close to the drain electrode, the P-type layer 14 is located between the P-GaN extension layer 13 and the drain electrode, the gate electrode is located on the surface of the P-type layer 14 away from the barrier layer 12, and the P-GaN extension layer 13, the barrier layer 12 and the channel layer 11 form a pin diode structure; the first direction is the direction from the source electrode to the drain electrode.

[0008] In an embodiment of the present invention, in the direction perpendicular to the plane where the epitaxial structure 1 is located, the thickness of the P-GaN extension layer 13 is less than or equal to the thickness of the P-type layer 14.

[0009] In an embodiment of the present invention, the P-GaN extension layer 13 includes a plurality of sub-blocks 131 arranged along the first direction.

[0010] In an embodiment of the present invention, the barrier layer 12 includes a groove, and at least part of the P-GaN extension layer 13 is located in the groove.

[0011] In an embodiment of the present invention, the material of the P-GaN extension layer 13 includes GaN, and the material of the P-type layer 14 includes GaN, AlN or AlGaN.

[0012] In an embodiment of the present invention, the epitaxial structure 1 further includes a substrate 15, a nucleation layer 16 and a buffer layer 17 grown in sequence from bottom to top, and the channel layer 11 is located on the surface of the buffer layer 17 away from the substrate 15.

[0013] In an embodiment of the present invention, a passivation layer 2 is further included; the passivation layer 2 covers the surfaces of the source electrode, the drain electrode, the gate electrode and the epitaxial structure 1.

[0014] In an embodiment of the present invention, the materials of the barrier layer 12 and the channel layer 11 both include AlGaN or AlN, the materials of the nucleation layer 16 and the buffer layer 17 both include AlN, GaN or AlGaN, and the material of the passivation layer 2 includes SiN x 、SiO2、Al2O3 or AlN, where x represents the component of N.

[0015] In an embodiment of the present invention, the aluminum component of the material of the barrier layer 12 is higher than the aluminum component of the material of the channel layer 11.

[0016] In a second aspect, the present invention provides a method for manufacturing a GaN transistor with a P-GaN source extension, which is characterized in that it is used to manufacture the GaN transistor with a P-GaN source extension as described in the first aspect.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0018] The present invention provides a GaN transistor with a P-GaN source extension and a preparation method thereof. In this GaN transistor, the source and the drain are oppositely arranged at both ends of the surface of the barrier layer away from the channel layer, and the P-GaN extension layer is located on the side of the source close to the drain. Introducing the P-GaN extension layer can deplete part of the two-dimensional electron gas below it, thereby reducing the short-circuit saturation current and enhancing the short-circuit reliability of the P-GaN transistor.

[0019] The following will further elaborate on the present invention in conjunction with the drawings and embodiments. Description of the Drawings

[0020] Figure 1 is a schematic structural diagram of a GaN transistor with a P-GaN source extension provided by an embodiment of the present invention;

[0021] Figure 2 is another schematic structural diagram of a GaN transistor with a P-GaN source extension provided by an embodiment of the present invention;

[0022] Figure 3 is a contour map of the electron concentration at the channel when the length of the P-GaN extension layer is 2 μm and the thickness is 0.035 μm provided by an embodiment of the present invention;

[0023] Figure 4a is a two-dimensional electron gas concentration map at the channel of the P-GaN extension layer with a thickness of 0.03 μm provided by an embodiment of the present invention;

[0024] Figure 4b is a two-dimensional electron gas concentration map at the channel of the P-GaN extension layer with a thickness of 0.035 μm provided by an embodiment of the present invention;

[0025] Figure 4c is a two-dimensional electron gas concentration map at the channel of the P-GaN extension layer with a thickness of 0.04 provided by an embodiment of the present invention;

[0026] Figure 5 is a simulation structural diagram of a GaN transistor when the P-GaN extension layer includes three sub-blocks provided by an embodiment of the present invention;

[0027] Figure 6 is provided by an embodiment of the present invention Figure 5 The two-dimensional electron gas concentration map at the channel of the P-GaN extension layer in the shown GaN transistor;

[0028] Figure 7It is a contour map of the electron concentration at the P-GaN extended layer channel when a part of the P-GaN extended layer in the embodiment of the present invention is located within the barrier layer;

[0029] Figure 8 is provided by the embodiment of the present invention Figure 7 The two-dimensional electron gas concentration map at the P-GaN extended layer channel in the GaN transistor shown. Detailed implementation manners

[0030] The present invention will be further described in detail below in conjunction with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0031] Figure 1 It is a schematic structural diagram of a GaN transistor with a P-GaN source extension provided by the embodiment of the present invention. Please refer to Figure 1 , the embodiment of the present invention provides a GaN transistor with a P-GaN source extension, including: an epitaxial structure 1, a source electrode S, a gate electrode G, and a drain electrode D. The epitaxial structure 1 includes a channel layer 11, a barrier layer 12 located on one side of the channel layer 11, and a P-GaN extended layer 13 and a P-type layer 14 located on the surface of the barrier layer 12 away from the channel layer 11; wherein,

[0032] The source electrode S and the drain electrode D are oppositely arranged at both ends of the surface of the barrier layer 12 away from the channel layer 11. In the first direction, the P-GaN extended layer 13 is located on the side of the source electrode S close to the drain electrode D, the P-type layer 14 is located between the P-GaN extended layer 13 and the drain electrode D, the gate electrode G is located on the surface of the P-type layer 14 away from the barrier layer 12, and the P-GaN extended layer 13, the barrier layer 12, and the channel layer 11 form a pin diode structure; the first direction is the direction from the source electrode S to the drain electrode D.

[0033] Specifically, the above GaN transistor includes an epitaxial structure 1, and the epitaxial structure 1 at least includes a channel layer 11, a barrier layer 12, a P-GaN extended layer 13, and a P-type layer 14. Among them, the barrier layer 12 is located on the upper surface of the channel layer 11, and the P-GaN extended layer 13 and the P-type layer 14 are located on the upper surface of the barrier layer 12. The GaN transistor further includes a source electrode S, a gate electrode G, and a drain electrode D. The source electrode S and the drain electrode D are oppositely arranged at both ends of the upper surface of the barrier layer 12. Optionally, taking the direction from the source electrode S to the drain electrode D as the first direction, that is Figure 1 the horizontal direction in the perspective shown, then in the first direction, the P-GaN extended layer 13 is located on the side of the source electrode S close to the drain electrode D, that is to say, the P-GaN extended layer 13 is located on the right side of the source electrode S, and the two can be in contact or not in contact. The P-type layer 14 is located between the P-GaN extended layer 13 and the drain electrode D, and the gate electrode G is above the P-type layer 14.

[0034] It should be understood that during a short circuit, since there is no current-limiting and voltage-bearing load in the power loop, the loop current will increase sharply and reach the short-circuit saturation current of the device, and the loop bus voltage is borne by the device. This causes the device to simultaneously bear large current and high voltage stress, resulting in a rapid increase in the power loss of the device and generating a large amount of heat in a short time. Moreover, the longer the short-circuit time, the more heat the device accumulates. Under such extreme stresses of high voltage, large current, and high temperature, the electrical characteristics of the device degenerate or even burn out. In this embodiment, the P-GaN extended layer 13 on the right side of the source electrode S, the barrier layer 12, and the channel layer 11 form a p-i-n diode structure. Therefore, the entire heterojunction energy band will be lifted by its built-in electric potential, and the electrons at the heterojunction interface will flow to the P-GaN extended layer 13 with a lower energy band, finally depleting part of the two-dimensional electron gas (2DEG, two Dimensional Electron Gas) at the heterojunction interface below the P-GaN extended layer 13, thereby achieving the purpose of reducing the saturation current and enhancing the short-circuit reliability of the P-GaN transistor.

[0035] Figure 2 FIG. is another schematic structural diagram of a GaN transistor with a P-GaN source extension provided by an embodiment of the present invention. Optionally, the P-GaN extended layer 13 includes a plurality of sub-blocks 131 arranged along the first direction.

[0036] Although Figure 1 FIG.

[0035] only shows the P-GaN extended layer 13 as a rectangular sub-block 131, in fact, the P-GaN extended layer 13 may include Figure 2 the plurality of sub-blocks 131 arranged along the first direction shown in FIG. Figure 2 . This design method is more conducive to balancing the output current and the short-circuit resistance. Of course, the present application does not limit the number of sub-blocks 131.

[0037] Optionally, in the direction perpendicular to the plane of the epitaxial structure, the thickness of the P-GaN extended layer 13 is less than or equal to the thickness of the P-type layer 14.

[0038] In this embodiment, the thickness of the P-GaN extended layer 13 is less than or equal to the thickness of the P-type layer 14, so as to avoid completely depleting the two-dimensional electron gas at the heterojunction interface below due to the too large thickness of the P-GaN extended layer 13 and causing the device to be unable to turn on. For example, the thickness of the P-GaN extended layer 13 in the direction perpendicular to the plane of the epitaxial structure is 10 - 30 nm, and the width in the first direction is 0 - 5 μm.

[0039] Actually, the thickness of the pGaN extended layer 13 can be adjusted according to requirements, so as to achieve a better compromise between short-circuit stress, conduction characteristics, etc. Therefore, the present application provides a technology with controllable short-circuit stress characteristics.

[0040] In addition, the barrier layer 12 may further include a groove, and at least a part of the P-GaN extension layer 13 is located in the groove. By etching the groove on the barrier layer 12, the two-dimensional electron gas concentration in the channel part can be better depleted, further improving the short-circuit ability of the device.

[0041] Optionally, the material of the P-GaN extension layer 13 includes GaN, and the material of the P-type layer 14 includes GaN or AlGaN.

[0042] Please continue to refer to Figure 1 , in the above GaN transistor with P-GaN source S extension, the epitaxial structure 1 further includes a substrate 15, a nucleation layer 16, and a buffer layer 17 that are grown in sequence from bottom to top, and the channel layer 11 is located on the surface of the buffer layer 17 away from the substrate 15.

[0043] The GaN transistor further includes a passivation layer 2; the passivation layer 2 covers the surfaces of the source S, the drain D, the gate G, and the epitaxial structure 1.

[0044] Specifically, in this embodiment, the material of the substrate 15 includes Si, SiC, sapphire, or GaN, the materials of the nucleation layer 16 and the buffer layer 17 include AlN, GaN, or AlGaN, the material of the channel layer 11 includes GaN or AlGaN, the material of the barrier layer 12 may include AlGaN or AlN, the source S and the drain D use a metal combination of Ti / Al / Ni / Au or Ti / Al / Pt / Au to form an ohmic contact, the gate G is a metal that can form a Schottky contact or an ohmic contact with the P-GaN extension layer 13, and the material of the passivation layer 2 includes SiN x , SiO2, Al2O3, or AlN, where x represents the composition of N. Optionally, in order to improve the carrier mobility, an insertion layer can also be introduced between the barrier layer and the channel layer, and its material includes AlN, InAlN, or AlGaN.

[0045] Exemplarily, in the direction perpendicular to the plane where the epitaxial structure 1 is located, the thickness of the nucleation layer 16 is 30 nm to 200 μm, the thickness of the buffer layer 17 is 0.5 μm to 2 μm, the thickness of the channel layer 11 is 50 nm to 200 nm, the thickness of the barrier layer 12 is 10 to 40 nm, and the thickness of the passivation layer 2 is 50 nm.

[0046] It should be noted that the aluminum composition of the material of the barrier layer 12 is higher than that of the material of the channel layer 11. Since the barrier layer 12 and the channel layer 11 form a heterojunction structure and a polarization effect occurs, the higher aluminum composition of the material of the barrier layer 12 than that of the material of the channel layer 11 is beneficial to generating a two-dimensional electron gas at the interface near the channel layer 11 to form a conductive channel layer 11.

[0047] An embodiment of the present invention further provides a method for manufacturing a GaN transistor with a P-GaN source S extension, which is used to manufacture the above-mentioned GaN transistor with a P-GaN source S extension.

[0048] In this embodiment, the method for manufacturing a GaN transistor with a P-GaN source S extension includes:

[0049] Step S1: Provide an epitaxial wafer, which sequentially includes, from bottom to top: a substrate 15, a nucleation layer 16, a buffer layer 17, a channel layer 11, a barrier layer 12, and a P-GaN layer.

[0050] Specifically, first, the substrate 15 is ultrasonically cleaned to eliminate the dangling bonds on the surface, then dried and heat-treated. Subsequently, a nucleation layer 16 with a thickness of 30 nm to 200 μm, a buffer layer 17 with a thickness of 0.5 μm to 2 μm, a channel layer 11 with a thickness of 50 nm to 200 nm, a barrier layer 12 with a thickness of 10 - 40 nm, and a P-GaN layer with a thickness of 60 nm are sequentially deposited on the substrate 15 by metalorganic chemical vapor deposition (MOCVD) process to obtain the epitaxial wafer.

[0051] Optionally, the obtained epitaxial wafer is ultrasonically cleaned in acetone for 2 minutes to remove the residual organic matter on the surface of the epitaxial wafer, then cooked in a positive photoresist stripping solution at 60 °C for 10 minutes, and then ultrasonically cleaned in acetone and ethanol for 3 minutes respectively, and then the residual acetone and ethanol are washed away with deionized water, further cleaned with a hydrofluoric acid solution for 30 s, and finally cleaned with deionized water and blown dry with N2.

[0052] Step S2: Etch the P-GaN layer to form a P-GaN extension layer 13 and a P-type layer 14.

[0053] In this embodiment, a Cl2 / N2 / O2 mixed gas is introduced and inductively coupled plasma etching (ICP) process is used to etch the P-GaN layer with high selectivity without damaging the barrier layer 12, removing the P-GaN layer in other regions except for the required P-GaN extension layer 13 and the P-GaN layer. After the P-type layer 14 in the middle of the upper surface of the barrier layer 12 is etched, the P-GaN extension layer 13 on the right side of the source S is etched.

[0054] Optionally, the thickness of the P-GaN extension layer 13 is 10 - 30 nm, not exceeding the thickness of the P-type layer 14, the width is about 0 - 5 μm, and the doping concentration is 1×10 16 ~1×10 20 / cm 3 .

[0055] Step S3: Fabricate source and drain electrodes D on the surface of the barrier layer 12.

[0056] Specifically, Ti / Al / Ni / Au or Ti / Al / Pt / Au metal is deposited on the barrier layer 12 by electron beam evaporation process, and high-temperature annealing is carried out in a rapid annealing furnace to form a good ohmic contact, thus obtaining the source electrode S and the drain electrode D; further, Ni / Au metal is deposited on the surface of the P-type layer 14 by electron beam evaporation process to form a Schottky contact, or metals such as Ti / Al / Ni / Au are deposited to form an ohmic contact, obtaining the fabricated gate G.

[0057] Step S4, fabricate the passivation layer 2.

[0058] Use plasma enhanced chemical vapor deposition (PECVD) process to deposit 50 nm of SiN x , SiO2, Al2O3 or AlN passivation layer 2 on the surfaces of the barrier layer 12, the source electrode S, the drain electrode D, the gate G, the P-type layer 14 and the P-type extended layer. Among them, the nitrogen (N) source can be provided by ammonia (NH3), and the silicon (Si) source is provided by silane (SiH4), so as to effectively suppress the current collapse phenomenon.

[0059] Step S4, open holes on the passivation layer 2 above the source electrode S, the drain electrode D and the gate G respectively, lead out electrodes, and obtain the fabricated GaN transistor with P-GaN source electrode S extension.

[0060] The GaN transistor with P-GaN source electrode S extension provided by the present invention is further described below through simulation.

[0061] Figure 3 is the electron concentration distribution contour map at the channel when the length of the P-GaN extended layer 13 in the embodiment of the present invention is 2 μm and the thickness is 0.035 μm. Figures 4a-4c is the two-dimensional electron gas concentration map at the channels of P-GaN extended layers with different thicknesses provided by the embodiment of the present invention. Among them, Figures 4a-4b the lengths of the P-GaN extended layers in are all 2 μm, and the thicknesses are 0.03 μm, 0.035 μm and 0.04 μm respectively. Please combine Figure 3 and Figures 4a-4b , it can be seen that the electron concentration between the channel layer and the barrier layer and near the channel layer interface shows a depletion trend at the P-GaN extended layer, and the two-dimensional electron gas concentration drops from 18 / cm 3 to 17 / cm 3 . The thicker the P-GaN extended layer, the more electrons are depleted. However, the thickness of the P-GaN extended layer cannot be too large, otherwise the device will turn off. Therefore, in this embodiment, by introducing the P-GaN extended layer, the two-dimensional electron gas concentration below it decreases, and the saturation current of the device decreases, thereby improving the short-circuit reliability.

[0062] Figure 5It is a simulation structure diagram of a GaN transistor when the P-GaN extension layer provided by an embodiment of the present invention includes three sub-blocks. Among them, the thickness of each sub-block 131 is 0.035 μm and the width is 0.5 μm. Figure 6 It is provided by an embodiment of the present invention Figure 5 The two-dimensional electron gas concentration map at the channel of the P-GaN extension layer in the shown GaN transistor. As Figures 5-6 shown, the electron concentration near the interface of the channel layer and the barrier layer close to the channel layer shows a depletion trend at the P-GaN extension layer, and the two-dimensional electron gas concentration decreases from 18 / cm 3 to 17.5 / cm 3 , thereby reducing the saturation current of the device and improving the short-circuit ability.

[0063] Furthermore, Figure 7 It is the electron concentration distribution nephogram at the channel of the P-GaN extension layer when a part of the P-GaN extension layer is located inside the barrier layer provided by an embodiment of the present invention. Among them, the length of the P-GaN extension layer 13 is 1.5 μm, the thickness is 0.04 μm, and the etching depth of the barrier layer 12 is 0.005 μm. Figure 8 It is provided by an embodiment of the present invention Figure 7 The two-dimensional electron gas concentration map at the channel of the P-GaN extension layer in the shown GaN transistor. Combining Figures 7-8 it can be seen that between the channel layer and the barrier layer, the electron concentration near the interface of the channel layer shows a depletion trend at the P-GaN extended at the source, and the two-dimensional electron gas concentration decreases from 18 / cm 3 to 16.8 / cm 3 , thereby reducing the saturation current of the device and improving the short-circuit ability.

[0064] It can be seen from the above embodiments that the beneficial effects of the present invention are as follows:

[0065] The present invention provides a GaN transistor with a P-GaN source extension and a preparation method thereof. In this GaN transistor, the source and the drain are oppositely arranged at both ends of the surface of the barrier layer far from the channel layer, and the P-GaN extension layer is located on the side of the source close to the drain. Introducing the P-GaN extension layer can deplete a part of the two-dimensional electron gas below it, thereby reducing the short-circuit saturation current and enhancing the short-circuit reliability of the P-GaN transistor.

[0066] In the description of the present invention, the description referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0067] The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A GaN transistor with a P-GaN source extension, characterized in that, Comprising: An epitaxial structure (1), a source electrode, a gate electrode, and a drain electrode. The epitaxial structure (1) includes a channel layer (11), a barrier layer (12) located on one side of the channel layer (11), and a P-GaN extension layer (13) and a P-type layer (14) located on the surface of the barrier layer (12) away from the channel layer (11); wherein, The source electrode and the drain electrode are oppositely disposed at both ends of the surface of the barrier layer (12) away from the channel layer (11). In a first direction, the P-type layer (14) is located between the source electrode and the drain electrode, the P-GaN extension layer (13) is located between the source electrode and the P-type layer (14), the gate electrode is located on the surface of the P-type layer (14) away from the barrier layer (12), and the P-GaN extension layer (13), the barrier layer (12), and the channel layer (11) form a pin diode structure; the first direction is the direction from the source electrode to the drain electrode; The P-GaN extension layer (13) includes a plurality of sub-blocks (131) arranged along the first direction.

2. The GaN transistor with P-GaN source extension according to claim 1, wherein In a direction perpendicular to the plane where the epitaxial structure (1) is located, the thickness of the P-GaN extension layer (13) is less than or equal to the thickness of the P-type layer (14).

3. The GaN transistor with a P-GaN source extension according to claim 2, characterized in that The barrier layer (12) includes a groove, and at least part of the P-GaN extension layer (13) is located in the groove.

4. The GaN transistor with P-GaN source extension according to claim 1, wherein The material of the P-GaN extension layer (13) includes GaN, and the material of the P-type layer (14) includes GaN, AlN, or AlGaN.

5. The GaN transistor with a P-GaN source extension according to claim 1, wherein The epitaxial structure (1) further includes a substrate (15), a nucleation layer (16), and a buffer layer (17) grown in sequence from bottom to top, and the channel layer (11) is located on the surface of the buffer layer (17) away from the substrate (15).

6. The GaN transistor with P-GaN source extension according to claim 5, characterized in that, Also including a passivation layer (2); the passivation layer (2) covers the surfaces of the source electrode, the drain electrode, the gate electrode, and the epitaxial structure (1).

7. The GaN transistor with a P-GaN source extension according to claim 6, characterized in that, The materials of the barrier layer (12) and the channel layer (11) both include AlGaN or AlN, the materials of the nucleation layer (16) and the buffer layer (17) both include AlN, GaN or AlGaN, and the material of the passivation layer (2) includes SiN x , SiO2, Al2O3 or AlN, where x represents the component of N.

8. The GaN transistor with a P-GaN source extension according to claim 7, wherein, The aluminum component of the material of the barrier layer (12) is higher than the aluminum component of the material of the channel layer (11).

9. A method for fabricating a GaN transistor with a P-GaN source extension, characterized in that, For preparing a GaN transistor with a P-GaN source extension as described in any one of claims 1 to 8.

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