A clock signal source circuit

Abstract

The present application relates to a clock signal source circuit, which belongs to the field of circuit technology. It includes: a frequency division circuit, a digital time converter and a gain adjustment circuit; the frequency division circuit is used to receive a base frequency signal and a frequency division ratio signal, generate a first clock signal based on the base frequency signal and the frequency division ratio signal, and provide the first clock signal to the digital time converter and the gain adjustment circuit respectively; the digital time converter is connected to the gain adjustment circuit, and the digital time converter processes the first clock signal to generate a second clock signal; the gain adjustment circuit determines the gain coefficient of the digital time converter based on the first clock signal and the second clock signal, and adjusts the gain of the digital time converter based on the gain coefficient; the digital time converter uses the adjusted gain to process the first clock signal, generates a clock signal of the clock signal source, and outputs a clock signal. Implementing the technical solution provided by the present application can improve the accuracy of the clock signal output.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a clock signal source circuit. Background Art

[0002] With the improvement of the integration of electronic systems, various devices (such as microprocessors, communication transceiver chips, and memory chips) are integrated together to form a system on chip (Soc). Therefore, it is usually necessary to integrate multiple clock sources of different frequencies in the Soc to meet various frequency outputs.

[0003] In order to meet the demand of providing multiple clock sources with different frequencies in the same SoC, the industry proposes to use fractional divider technology, that is, to set an integer PLL and multiple fractional dividers in the same SoC to achieve the output of multiple clock frequencies. However, the existing fractional dividers usually have high jitter, causing the output clock signal to lead or lag the divider input signal (for example, one clock cycle ahead or behind the divider input signal), which leads to inaccurate output clock signal. Summary of the invention

[0004] The clock signal source circuit provided in the embodiment of the present application can improve the accuracy of clock signal output.

[0005] In the first aspect, an embodiment of the present application provides a clock signal source circuit, comprising: a frequency division circuit, a digital time converter and a gain adjustment circuit; the first output end of the frequency division circuit is connected to the input end of the digital time converter and the gain adjustment circuit, the frequency division circuit is used to receive a baseband signal and a frequency division ratio signal, generate a first clock signal based on the baseband signal and the frequency division ratio signal, and provide the first clock signal to the digital time converter and the gain adjustment circuit respectively; the digital time converter is connected to the gain adjustment circuit, the digital time converter processes the first clock signal to generate a second clock signal; the gain adjustment circuit determines the gain coefficient of the digital time converter based on the first clock signal and the second clock signal, and adjusts the gain of the digital time converter based on the gain coefficient; the digital time converter processes the first clock signal using the adjusted gain to generate a clock signal of the clock signal source, and outputs the clock signal.

[0006] The clock signal source circuit provided in the embodiment of the present application, by setting a digital time converter and a gain adjustment circuit, compensates and corrects the gain of the digital time converter through the gain adjustment circuit, so that the digital time converter itself has lower jitter; in addition, the clock signal output by the frequency division circuit is jitter compensated by the digital time converter after gain correction, which can further reduce the jitter of the output signal of the frequency division circuit, thereby reducing the deviation of the output clock signal and improving the accuracy of the output clock signal. In addition, compared with the method of realizing multiple clock signals of different frequencies by means of multiple PLLs as shown in the conventional technology, the clock signal source circuit provided in the embodiment of the present application can reduce the chip layout area and system complexity, and reduce costs; in addition, using only one PLL can also reduce chip power consumption.

[0007] In one possible implementation, the gain adjustment circuit is used to: perform a first delay on the first clock signal to generate a third clock signal; perform a second delay on the second clock signal to generate a fourth clock signal; and determine the gain coefficient of the digital-to-time converter based on the first clock signal, the third clock signal, and the fourth clock signal.

[0008] In one possible implementation, the gain adjustment circuit is also used to: convert a first time difference between the first clock signal and the third clock signal into first data; convert a second time difference between the first clock signal and the fourth clock signal into second data; adjust a preset gain value of the digital time converter based on the data difference between the first data and the second data, and generate a gain coefficient based on the adjustment result.

[0009] In a possible implementation, the gain adjustment circuit includes a first trigger, a first selector, a second selector, a time-to-digital converter and a gain controller; the input end of the first trigger is connected to the first output end of the frequency division circuit, and the output end of the first trigger is connected to the first input end of the first selector; the output end of the digital-to-time converter is connected to the second input end of the first selector, and the output end of the first selector is connected to the first input end of the time-to-digital converter; the second input end of the time-to-digital converter is connected to the first output end of the frequency division circuit, and the output end of the time-to-digital converter is connected to the input end of the gain controller; the first output end of the gain controller is connected to the control end of the digital-to-time converter, and the second output end of the gain controller is connected to the control end of the first selector; the first input end of the second selector is connected to the second output end of the frequency division circuit, the second input end of the second selector is connected to the third output end of the gain controller, the control end of the second selector is connected to the fourth output end of the gain controller, and the output end of the second selector is connected to the input end of the gain controller.

[0010] In one possible implementation, the clock signal source circuit also includes an integral nonlinearity correction circuit, which is connected to the second output terminal of the frequency division circuit and the gain adjustment circuit; the integral nonlinearity correction circuit obtains fractional error data used for frequency division from the frequency division circuit, obtains a compensation value corresponding to the fractional error data from a pre-stored mapping relationship based on the fractional error data, and generates a correction value based on the compensation value and the fractional error data and provides it to the gain controller; the gain controller corrects the digital-to-time converter based on the correction value and the gain coefficient.

[0011] In one possible implementation, the gain controller is also used to: discretize the fractional error data of the frequency division circuit into multiple values ​​in ascending order, and provide the multiple values ​​to the integral nonlinearity correction circuit respectively; the integral nonlinearity correction circuit is also used to: generate a compensation value corresponding to each of the multiple values ​​based on the multiple values; and establish a mapping relationship based on the multiple values ​​and the compensation values ​​corresponding to the multiple values.

[0012] In one possible implementation, the integral nonlinearity correction circuit includes a third selector, a multiplier and an integral nonlinearity corrector; the output end of the digital-to-time converter is connected to the third input end of the first selector through the third selector; the output end of the second selector is connected to one of the input ends of the multiplier, so as to be connected to the input end of the gain controller through the multiplier; the input end of the integral nonlinearity corrector is connected to the second output end of the frequency division circuit, and the output end of the integral nonlinearity corrector is connected to the other input end of the multiplier; the output end of the multiplier is connected to the input end of the gain controller.

[0013] In one possible implementation, the frequency division circuit includes a frequency divider, an adder, and a second trigger; one of the input ends of the frequency divider is used to receive the baseband signal, the other input end of the frequency divider is connected to the output end of the adder, and the output end of the frequency divider is connected to the input end of the digital time converter and the gain adjustment circuit through the second trigger; one of the input ends of the adder is used to input the integer part signal of the frequency division ratio signal, and the other input end of the adder is used to input the decimal part signal of the frequency division ratio signal.

[0014] In a possible implementation, the frequency division circuit also includes a modulator; the input end of the modulator is used to input the fractional part signal; one of the output ends of the modulator is connected to the other input end of the adder; and the other output end of the modulator is connected to the first input end of the second selector.

[0015] In one possible implementation, a modulator modulates a fractional part signal based on a fractional part signal of a frequency division ratio signal inputted at an input end, generates a modulated signal and outputs it to a first input end of a second selector, and provides the fractional part signal to an adder; an adder superimposes an integer part signal and a fractional part signal of the frequency division ratio signal, generates a frequency division ratio signal and provides it to a frequency divider; a frequency divider generates an initial clock signal based on a baseband signal and the frequency division ratio signal and outputs it to a second trigger; and a second trigger, based on the triggering of the baseband signal, generates a first clock signal generated from the initial clock signal and provides it to a digital-to-time converter, a time-to-digital converter and a first trigger, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of an application scenario of the clock signal source circuit provided in an embodiment of the present application.

[0017] Figure 2 It is a structural schematic diagram of a clock signal source circuit provided in an embodiment of the present application.

[0018] Figure 3 This embodiment of the present application provides Figure 2 A specific structural schematic diagram of the clock signal source circuit shown.

[0019] Figure 4 It is another structural schematic diagram of the clock signal source circuit provided in an embodiment of the present application.

[0020] Figure 5 This embodiment of the present application provides Figure 4 A specific structural schematic diagram of the clock signal source circuit shown. DETAILED DESCRIPTION

[0021] In order to enable technicians in this field to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0022] In the description of the embodiments of the present application, words such as "for example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "for example" or "for example" is intended to present related concepts in a specific way.

[0023] In the description of the embodiments of the present application, the term "multiple" means two or more. For example, multiple transducers refer to two or more transducers. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0024] In traditional technology, multiple different phase-locked loops (PLLs) are usually used to implement multiple clock sources with different frequencies. However, as the frequencies required by SOCs increase and the frequency needs to be adjusted at any time, integrating multiple PLLs inside the SOC will occupy too much chip layout area, resulting in a large chip area and increased costs. In addition, the more PLLs integrated in the SOC, the more complex the internal system will be. In addition, too many PLLs will also generate huge power consumption.

[0025] Therefore, the industry further proposed to use fractional frequency divider technology to achieve the output of multiple clock frequencies. However, the existing fractional frequency divider usually has high jitter, causing the output clock signal to lead or lag the divider input signal (for example, one clock cycle ahead or behind the divider input signal), which results in inaccurate output clock signal.

[0026] The clock signal source circuit provided in the embodiment of the present application, by setting a digital time converter and a gain adjustment circuit, compensates and corrects the gain of the digital time converter through the gain adjustment circuit, so that the digital time converter itself has lower jitter; in addition, the clock signal output by the frequency division circuit is jitter compensated by the digital time converter after gain correction, which can further reduce the jitter of the output signal of the frequency division circuit, thereby reducing the deviation of the output clock signal and improving the accuracy of the output clock signal. In addition, compared with the method of realizing multiple clock signals of different frequencies by means of multiple PLLs as shown in the conventional technology, the clock signal source circuit provided in the embodiment of the present application can reduce the chip layout area and system complexity, and reduce costs; in addition, using only one PLL can also reduce chip power consumption.

[0027] Please refer to Figure 1 , Figure 1 Schematic diagram of an application scenario of the clock signal source circuit provided in the embodiment of the present application. Figure 1 The application scenario shown includes a phase-locked loop circuit and three clock signal source circuits, and the three clock signal source circuits are respectively connected to the phase-locked loop circuit. Figure 1 Three clock signal source circuits are schematically shown in FIG. 1 . In other scenarios, the phase-locked loop circuit can be connected to more or fewer clock signal source circuits, which is determined based on the number of different clock frequencies to be output. The phase-locked loop circuit is used to input an integer-divided clock signal to each clock signal source circuit, and each clock signal source circuit generates a clock frequency signal to be output based on the integer-divided clock signal and the division ratio.

[0028] based on Figure 1 The application scenario shown below is Figure 2~Figure 5 The embodiment shown in the figure describes in detail the clock signal source circuit provided in the embodiment of the present application. Figure 2 , Figure 2 1 is a schematic diagram of a clock signal source circuit 100 provided in an embodiment of the present application. Figure 2 As shown, the clock signal source circuit 100 includes a frequency division circuit 101, a digital-to-time converter 102 and a gain adjustment circuit 103. Figure 2 As shown, the frequency division circuit 101 includes input terminals fi1, fi2, fi3 and a first output terminal fo1; the digital time converter 102 includes a control terminal dc, an input terminal di and an output terminal do; the gain adjustment circuit 103 includes input terminals gi1, gi2, gi3 and an output terminal go1. The first output terminal fo1 of the frequency division circuit 101 is connected to the input terminal di of the digital time converter 102 and the input terminal gi1 of the gain adjustment circuit 103; the output terminal go1 of the gain adjustment circuit 103 is connected to the control terminal dc of the digital time converter 102. The input terminal fi1 of the frequency dividing circuit 101 is used to input the baseband signal (also known as the system clock signal) fin, the input terminal fi2 of the frequency dividing circuit 101 is used to input the integer part signal int of the frequency dividing ratio signal, and the input terminal fi3 of the frequency dividing circuit 101 is used to input the fractional part signal frac of the frequency dividing ratio signal; the input terminal gi2 of the gain adjustment circuit 103 is used to input the baseband signal fin; the output terminal do of the digital time converter 102 is the output terminal of the clock signal source circuit 100, and is used to output the divided clock signal clk_o. In addition, the output terminal do of the digital time converter 102 is connected to the input terminal gi3 of the gain adjustment circuit 103.

[0029] The frequency division circuit 101 generates a frequency division ratio signal by adding the integer part signal int and the fractional part signal frac of the received frequency division ratio signal; then, based on the frequency division ratio signal and the baseband signal fin, generates a first clock signal, and sends the first clock signal to the digital time converter 102 and the gain adjustment circuit 103 respectively. The digital time converter 102 processes the first clock signal to generate a second clock signal. The gain adjustment circuit 103 determines the gain coefficient k of the digital time converter based on the first clock signal, the second clock signal and the preset gain value, and then sends the gain coefficient k to the digital time converter 102 to adjust the gain of the digital time converter 102. The digital time converter 102 processes the first clock signal with the adjusted gain to generate the final clock signal clk_o, and outputs the clock signal clk_o.

[0030] In an embodiment of the present application, the digital-to-time converter 102 processes the first clock signal using an adjusted gain, which may include adjusting the phase of the first clock signal so that each clock cycle in the output clock signal is the same, thereby avoiding situations where some clock cycles are ahead or behind, thereby making the output clock signal more stable.

[0031] In a possible implementation, the gain adjustment circuit 103 is specifically used for: step 301, performing a first delay on the first clock signal to generate a third clock signal; step 302, performing a second delay on the second clock signal to generate a fourth clock signal; step 304, adjusting the gain coefficient of the digital-to-time converter 102 based on the first clock signal, the third clock signal, and the fourth clock signal. Specifically, the first delay time may include a T1+Tin period, and the second delay time may include a T1+T2 period. The gain adjustment circuit 103 may pre-set a gain value for the digital-to-time converter 102, generate a second clock signal based on the pre-set gain value, perform a second delay on the second clock signal, and after obtaining the fourth signal, the fourth signal and the third signal may be subtracted. When the signal after the difference is greater than zero, the step length of the pre-set gain value is increased, and when the signal after the difference is less than zero, the step length of the pre-set gain value is reduced, and then steps 301 to 304 are continued. After steps 301 to 304 are executed for a preset number of times (for example, the number of times is determined according to the number of bits of the set gain value), the final gain value is determined as the gain coefficient of the digital-to-time converter 102 .

[0032] from Figure 1It can be seen from the clock signal source circuit 100 shown that the clock signal source circuit 100 provided in the embodiment of the present application, by setting a digital time converter 102 and a gain adjustment circuit 103, the gain adjustment circuit 103 compensates and corrects the gain of the digital time converter 102, so that the digital time converter 102 itself has lower jitter; in addition, the clock signal output by the frequency division circuit 101 is jitter compensated by the digital time converter 102 after gain correction, which can further reduce the jitter of the output signal of the frequency division circuit 101, thereby reducing the deviation of the output clock signal and improving the accuracy of the output clock signal. In addition, compared with the method of realizing multiple clock signals of different frequencies by means of multiple PLLs shown in the conventional technology, the clock signal source circuit 100 provided in the embodiment of the present application can reduce the chip layout area and system complexity, and reduce costs; in addition, using only one PLL can also reduce chip power consumption.

[0033] based on Figure 2 The clock signal source circuit 100 shown in FIG. Figure 3 , Figure 3 This embodiment of the present application provides Figure 2 FIG. 1 is a schematic diagram of a specific structure of a clock signal source circuit 100. Figure 3 As shown, the frequency dividing circuit 101 includes a frequency divider M, a second trigger D2, an adder A1 and a modulator DSM. The input end of the frequency divider M is the input end fi1 of the frequency dividing circuit 101, which is used to input the baseband signal fin, the output end of the frequency divider M is connected to the input end of the second trigger D2, the frequency divider M is connected to the output end of the adder A1, one of the input ends of the adder A1 is the input end fi2 of the frequency dividing circuit 101, which is used to input the integer part signal int, and the other input end of the adder A1 is connected to the output end of the modulator DSM; the input end of the modulator DSM is the input end fi2 of the frequency dividing circuit 101, which is used to input the fractional part signal frac; the clock signal end of the second trigger D2 is used to input the baseband signal fin, and the output end of the second trigger D2 is the output end fo1 of the frequency dividing circuit 101, which is used to output the first clock signal clk_d1.

[0034] In a possible implementation, the gain adjustment circuit 103 includes a first trigger D1, a selector S1, a selector S2, a time-to-digital converter TDC, and a gain controller G. The input end of the first trigger D1 is the input end gi1 of the gain adjustment circuit 103, which is connected to the first output end fo1 of the frequency division circuit 101 (that is, the output end of the second trigger D2), and the output end of the first trigger D1 is connected to the first input end "0" of the first selector S1; the output end do of the digital-to-time converter 102 is connected to the second input end "1" of the first selector S1 (that is, the input end gi3 of the gain adjustment circuit 103), the output end of the first selector S1 is connected to the first input end of the time-to-digital converter TDC, and the control end of the first selector S1 is connected to the second output end go2 of the gain controller G; the second input end of the time-to-digital converter TDC The first output terminal "0" of the second selector S2 is connected to the other output terminal of the modulator DSM, the second input terminal "1" of the second selector S2 is connected to the third output terminal go3 of the gain controller G, the output terminal of the second selector S2 is connected to the other input terminal of the gain controller G, and the fourth output terminal go4 of the gain controller G is connected to the control terminal jc of the second selector S2.

[0035] In the embodiment of the present application, the gain controller G may be a programmable control device, for example, including but not limited to a microcontroller, a programmable logic controller PLC, etc. The gain controller G may also be provided with a plurality of registers. Figure 3 In the circuit structure shown, when the clock signal source circuit 100 is powered on and initialized, the gain coefficient of the digital-to-time converter 102 in the gain controller G can be set to 1 / 2 of the maximum gain value, the first input terminal "0" of the first selector S1 is controlled to be selected, the second input terminal "1" of the second selector S2 is controlled to be selected, and the signal input to the second input terminal "1" of the second selector S2 is set to 1.

[0036] The modulator DSM provides the fractional part signal frac of the frequency division ratio signal to the adder A1, and the adder A1 adds the integer part signal int and the fractional part signal frac of the frequency division ratio signal to generate a frequency division ratio signal and provides it to the frequency divider M. The frequency divider M generates a first clock signal based on the frequency division ratio signal and the base frequency signal fin, and sends the first clock signal to the digital-to-time converter 102, the first trigger D1 and the time-to-digital converter TDC respectively through the second trigger D2.

[0037] During the operation of the gain adjustment circuit 103, step 1, the first trigger D1 generates a third clock signal after delaying the first clock signal clk_d1 based on the triggering of the baseband signal fin, and provides it to the time-to-digital converter TDC; the time-to-digital converter TDC calculates the difference between the first clock signal clk_d1 and the third clock signal, converts the calculated result into a data signal data1 and provides it to the gain controller G, and the gain controller G stores the data signal data1 in the register 1. Step 2, the gain controller G controls the second input terminal "1" of the selector S1 to be selected, and the digital-to-time converter 102 generates a fourth clock signal by delaying the generated second clock signal (that is, the clk_o signal at this time) through the selector S1, and provides the fourth clock signal to the time-to-digital converter TDC; the time-to-digital converter TDC calculates the difference between the fourth clock signal and the first clock signal clk_d1, converts the calculated result into data data2 and provides it to the gain controller G, and the gain controller G stores the data data2 in the register 2. Step 3, the gain controller G performs a difference calculation on the data data2 and the data data1. If the result of the difference calculation is greater than 0, the gain coefficient is increased; if the result of the difference calculation is less than 0, the gain coefficient is decreased. Thus, based on the adjusted gain coefficient, steps 1 to 5 are re-executed. When steps 1 to 5 are executed a preset number of times (for example, the number of executions is the same as the number of bits of the gain coefficient), the gain coefficient determined by the last adjustment is determined as the final gain coefficient of the digital-to-time converter 102, so that the digital-to-time converter 102 generates a final clock signal output based on the final determined gain coefficient.

[0038] Please continue to refer to Figure 4 , Figure 4 1 is another structural diagram of the clock signal source circuit 100 provided in the embodiment of the present application. Different from the clock signal source circuit 100 shown in the above embodiments, Figure 4 The clock signal source circuit 100 shown in FIG. 1 includes, in addition to the frequency division circuit 101, the digital time converter 102, and the gain adjustment circuit 103, an integral nonlinear correction circuit 104, which is used to perform integral nonlinear correction on the digital time converter 102. The specific structures of the frequency division circuit 101, the digital time converter 102, and the gain adjustment circuit 103 and the connection relationship between the circuits are similar to those in FIG. Figure 2~Figure 3The integral nonlinear correction circuit 104 includes an input terminal ji1, an input terminal ji2, and an output terminal jo. The input terminal ji1 of the integral nonlinear correction circuit 104 is connected to the second output terminal fo2 of the frequency division circuit 101, the input terminal ji2 of the integral nonlinear correction circuit 104 is connected to the output terminal go5 of the gain adjustment circuit 103, and the output terminal jo of the integral nonlinear correction circuit 104 is connected to the input terminal gi4 of the gain adjustment circuit 103. The integral nonlinear correction circuit 104 can pre-generate a mapping relationship between the indication fractional error data and the compensation value. During the operation of the clock signal source circuit 100, the integral nonlinear correction circuit 104 can obtain the fractional error data for frequency division from the frequency division circuit 101, obtain the compensation value corresponding to the fractional error data from the pre-stored mapping relationship based on the fractional error data, and generate a correction value based on the compensation value and the fractional error data and provide it to the gain adjustment circuit 103; the gain adjustment circuit 103 corrects the digital-to-time converter 102 based on the correction value and the pre-generated gain coefficient. Specifically, after the gain adjustment circuit 103 determines the gain coefficient of the digital-to-time converter 102, the fractional error data of the frequency division circuit 101 can be discretized into multiple values ​​in ascending order, and the multiple values ​​can be provided to the integral nonlinearity correction circuit 104 respectively; the integral nonlinearity correction circuit 104 generates a compensation value corresponding to each of the multiple values ​​based on the multiple values; and the above-mentioned mapping relationship is established based on the multiple values ​​and the compensation values ​​corresponding to the multiple values.

[0039] based on Figure 4 The clock signal source circuit 100 shown in FIG. Figure 5 , Figure 5 This embodiment of the present application provides Figure 4 The specific structural diagram of the clock signal source circuit 100 is shown in FIG. Figure 5 As shown, the specific components included in the frequency division circuit 101 and the gain adjustment circuit 103 in the clock signal source circuit 100 and the connection relationship between the components are similar to Figure 3 The frequency division circuit 101 and the gain adjustment circuit 103 are the same as those shown in the figure, and the details are referred to in the relevant description, which will not be described again. Figure 3The difference between the clock signal source circuit 100 shown in the figure is that the integral nonlinear correction circuit 104 includes a third selector S3, a multiplier A2 and an integral nonlinear correction circuit F, wherein the input terminal "1" of the third selector S3 is connected to the output terminal do of the digital-to-time converter 102, the output terminal of the third selector S3 is connected to the third input terminal "2" of the first selector, and in addition, the control terminal of the third selector S3 is connected to the gain controller G; the input terminal of the integral nonlinear correction circuit F (that is, the input terminal ji1 of the integral nonlinear correction circuit 104) is connected to the output terminal of the modulator DSM (that is, the integral nonlinear correction circuit 104). The output end of the integral nonlinear corrector F is connected to one of the input ends of the multiplier A2; in addition, the output end of the second selector S2 in the gain adjustment circuit 103 (that is, the output end go5 of the gain adjustment circuit 103) is connected to the other input end of the multiplier A2 (that is, the input end ji2 of the integral nonlinear correction circuit 104), and the output end of the multiplier A2 is connected to the input end of the gain controller G, that is, the second selector S2 in the gain adjustment circuit 103 is connected to the input end of the gain controller G through the multiplier A2.

[0040] based on Figure 5 In the clock signal source circuit 100 shown in the embodiment of the present application, the gain adjustment circuit 103 can first determine the gain coefficient of the digital-to-time converter 102. When determining the gain coefficient of the digital-to-time converter 102, the coefficient output by the multiplier A2 can be kept as 1, that is, only the gain coefficient of the digital-to-time converter 102 is adjusted; wherein the specific adjustment steps of the gain coefficient of the digital-to-time converter 102 can be as described above. Figure 2 or Figure 3In the embodiment shown, the gain coefficient of the digital-to-time converter 102 is adjusted by adjusting the adjustment step to determine the gain coefficient K of the digital-to-time converter 102. Then, the integral nonlinearity of the digital-to-time converter 102 can be further corrected by keeping the gain coefficient K of the digital-to-time converter 102 unchanged. The integral nonlinearity correction of the digital-to-time converter 102 may include the following steps: Step 1, control the first input terminal "0" of the first selector S1 to be selected, control the second input terminal "1" of the second selector S2 to be selected, set the signal inputted at the second input terminal "1" of the second selector S2 to 0.5, the first trigger D1 is triggered based on the baseband signal fin, delays the first clock signal clk_d1 to generate a third clock signal and provides it to the time-to-digital converter TDC; the time-to-digital converter TDC calculates the difference between the first clock signal clk_d1 and the third clock signal, converts the calculated result into a data signal data1 and provides it to the gain controller G, and the gain controller G stores the data signal data1 in the register 1. Step 2: The gain controller G controls the second input terminal "1" of the selector S1 to be selected, and the digital-to-time converter 102 generates a fourth clock signal by delaying the second clock signal (i.e., the clk_o signal at this time) through the selector S1, and provides the fourth clock signal to the time-to-digital converter TDC; the time-to-digital converter TDC performs a difference calculation on the fourth clock signal and the first clock signal clk_d1, converts the calculated result into data data2 and provides it to the gain controller G, and the gain controller G stores the data data2 in register 2. Step 3: The gain controller G controls the third input terminal "2" of the selector S1 to be selected, and the digital-to-time converter 102 generates a fifth clock signal by delaying the second clock signal (i.e., the clk_o signal at this time) through the selectors S2 and S1, and provides the fifth clock signal to the time-to-digital converter TDC; the time-to-digital converter TDC performs a difference calculation on the fifth clock signal and the first clock signal clk_d1, converts the calculated result into data data3 and provides it to the gain controller G, and the gain controller G stores the data data3 in register 3. Step 4, the gain controller G calculates the difference between the data data3 and the data data2 to generate data data4. Step 5, calculate the value of 2*(data2-data4) / (data1-data4), if the value is greater than 1, then reduce the value of the nonlinear corrector F, if the value is less than 1, then increase the value of the nonlinear corrector F. Repeat the above steps 1 to 5 for a preset number of times until the correction value of the signal input to the second input terminal "1" of the second selector S2 is completed to be 0.5.

[0041] It should be noted that, in the embodiment of the present application, if it is necessary to improve the accuracy of the nonlinear correction of the gain controller G, the signal input to the second input terminal "1" of the second selector S2 can be set to 0.25 and 0.75, and the above steps 1 to 5 are repeated to obtain the correction values ​​of 0.25 and 0.75 for the signal input to the second input terminal "1" of the second selector S2, respectively. Further, if it is necessary to make the accuracy of the nonlinear correction of the gain controller G more precise, the signal input to the second input terminal "1" of the second selector S2 can be set to 0.125, 0.375, 0.625, 0.875, etc., respectively, and the above steps 1 to 5 are repeated to obtain the correction values ​​of 0.125, 0.375, 0.625, 0.875 for the signal input to the second input terminal "1" of the second selector S2, respectively. Thus, the mapping relationship between multiple fractional error data and compensation values ​​can be obtained. Then, an interpolation method is used to generate mapping relationships between more fractional error data and compensation values, thereby generating a mapping relationship table for use when the clock signal source circuit 100 is running.

[0042] When the clock signal source circuit 100 is running, the second selector S2 selects the input terminal "0" of the second selector S2 based on the control of the gain controller G, and the modulator DSM converts the acquired fractional part signal into fractional error data and provides them to the first input terminal "0" of the second selector S2 and the integral nonlinear corrector F respectively; the integral nonlinear corrector F determines the compensation value corresponding to the received fractional error data based on the pre-generated mapping relationship table, and then provides the compensation value to the multiplier A2; the second selector S2 provides the fractional error data to the multiplier A2; the multiplier A2 multiplies the fractional error data and the compensation value to generate the integral nonlinear adjustment data cdot and provides it to the gain controller G; the gain controller G multiplies the integral nonlinear adjustment data cdot with the gain coefficient K to generate the final compensation value of the digital-to-time converter 102, and provides it to the digital-to-time converter 102; thereby, the digital-to-time converter 102 adjusts the frequency-divided signal output by the frequency-dividing circuit 101 based on the final compensation value to generate a final clock output signal.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application is described in detail with reference to the above embodiments, a person skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A clock signal source circuit, characterized in that: It includes a frequency division circuit, a digital time converter and a gain adjustment circuit; The first output end of the frequency division circuit is connected to the input end of the digital time converter and the gain adjustment circuit, the frequency division circuit is used to receive a base frequency signal and a frequency division ratio signal, generate a first clock signal based on the base frequency signal and the frequency division ratio signal, and provide the first clock signal to the digital time converter and the gain adjustment circuit respectively; The digital-to-time converter is connected to the gain adjustment circuit, and the digital-to-time converter processes the first clock signal to generate a second clock signal; The gain adjustment circuit determines a gain coefficient of the digital-to-time converter based on the first clock signal and the second clock signal, and adjusts the gain of the digital-to-time converter based on the gain coefficient; The digital-to-time converter processes the first clock signal using the adjusted gain to generate a clock signal of the clock signal source, and outputs the clock signal; The gain adjustment circuit includes a first trigger, a first selector, a second selector, a time-to-digital converter and a gain controller; The input end of the first trigger is connected to the first output end of the frequency dividing circuit, and the output end of the first trigger is connected to the first input end of the first selector; The output end of the digital-to-time converter is connected to the second input end of the first selector, and the output end of the first selector is connected to the first input end of the time-to-digital converter; The second input terminal of the time-to-digital converter is connected to the first output terminal of the frequency dividing circuit, and the output terminal of the time-to-digital converter is connected to the input terminal of the gain controller; The first output terminal of the gain controller is connected to the control terminal of the digital-to-time converter, and the second output terminal of the gain controller is connected to the control terminal of the first selector; The first input end of the second selector is connected to the second output end of the frequency division circuit, the second input end of the second selector is connected to the third output end of the gain controller, the control end of the second selector is connected to the fourth output end of the gain controller, and the output end of the second selector is connected to the input end of the gain controller.

2. The clock signal source circuit according to claim 1, characterized in that: The gain adjustment circuit is used for: Performing a first delay on the first clock signal to generate a third clock signal; Performing a second delay on the second clock signal to generate a fourth clock signal; A gain factor of the digital-to-time converter is determined based on the first clock signal, the third clock signal, and the fourth clock signal.

3. The clock signal source circuit according to claim 2, characterized in that: The gain adjustment circuit is also used for: converting a first time difference between the first clock signal and the third clock signal into first data; converting a second time difference between the first clock signal and the fourth clock signal into second data; Based on the data difference between the first data and the second data, a preset gain value of the digital-to-time converter is adjusted, and based on the adjustment result, the gain coefficient is generated.

4. The clock signal source circuit according to claim 1, characterized in that: The clock signal source circuit further comprises an integral nonlinearity correction circuit, and the integral nonlinearity correction circuit is connected to the second output terminal of the frequency dividing circuit and the gain adjustment circuit; The integral nonlinear correction circuit acquires fractional error data used for frequency division from the frequency division circuit, acquires a compensation value corresponding to the fractional error data from a pre-stored mapping relationship based on the fractional error data, and generates a correction value based on the compensation value and the fractional error data and provides it to the gain controller; The gain controller corrects the digital-to-time converter based on the correction value and the gain coefficient.

5. The clock signal source circuit according to claim 4, characterized in that: The gain controller is also used to: discretize the fractional error data of the frequency division circuit into a plurality of values ​​in ascending order, and provide the plurality of values ​​to the integral nonlinearity correction circuit respectively; The integral nonlinear correction circuit is further used for: generating a compensation value corresponding to each of the multiple values ​​based on the multiple values; and establishing the mapping relationship based on the multiple values ​​and the compensation values ​​corresponding to the multiple values.

6. The clock signal source circuit according to claim 5, characterized in that: The integral nonlinear correction circuit comprises a third selector, a multiplier and an integral nonlinear corrector; The output terminal of the digital-to-time converter is connected to the third input terminal of the first selector through the third selector; The output terminal of the second selector is connected to one of the input terminals of the multiplier so as to be connected to the input terminal of the gain controller through the multiplier; The input end of the integral nonlinearity corrector is connected to the second output end of the frequency dividing circuit, and the output end of the integral nonlinearity corrector is connected to the other input end of the multiplier; The output end of the multiplier is connected to the input end of the gain controller.

7. The clock signal source circuit according to claim 1, characterized in that: The frequency division circuit includes a frequency divider, an adder and a second trigger; One of the input ends of the frequency divider is used to receive the baseband signal, the other input end of the frequency divider is connected to the output end of the adder, and the output end of the frequency divider is connected to the input end of the digital-to-time converter and the gain adjustment circuit through the second trigger; One of the input ends of the adder is used to input the integer part signal of the frequency division ratio signal, and the other input end of the adder is used to input the decimal part signal of the frequency division ratio signal.

8. The clock signal source circuit according to claim 7, characterized in that: The frequency division circuit also includes a modulator; The input end of the modulator is used to input a fractional part signal; one of the output ends of the modulator is connected to the other input end of the adder; and the other output end of the modulator is connected to the first input end of the second selector.

9. The clock signal source circuit according to claim 8, characterized in that: The modulator modulates the fractional part signal based on the fractional part signal of the frequency division ratio signal inputted at the input terminal, generates a modulated signal and outputs it to the first input terminal of the second selector, and provides the fractional part signal to the adder; The adder adds the integer part signal and the decimal part signal of the frequency division ratio signal to generate the frequency division ratio signal and provide it to the frequency divider; The frequency divider generates an initial clock signal based on the base frequency signal and the frequency division ratio signal and outputs it to the second trigger; The second trigger, based on the triggering of the baseband signal, generates a first clock signal from the initial clock signal and provides the first clock signal to the digital-to-time converter, the time-to-digital converter and the first trigger respectively.

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