Array substrate and display panel

Abstract

This application belongs to the field of display panels and provides an array substrate and a display panel. The array substrate includes a substrate, a first signal line, and a first pattern layer. The first signal line is located on the surface of the substrate. The first pattern layer is located on the side of the first signal line away from the substrate. The first pattern layer and the first signal line are connected through a first via. A first orthographic projection portion is located outside a second orthographic projection. The first orthographic projection is the orthographic projection of the first via onto the substrate, and the second orthographic projection is the orthographic projection of the first signal line onto the substrate. Only a portion of the bottom of the first via is located on the surface of the first signal line, while another portion is located outside the first signal line. Therefore, the first pattern layer formed at the connection point between the portion of the first via bottom outside the first signal line and the wall of the first via is less prone to breakage, reducing the possibility of failure of the first via and thus improving the yield of the array substrate.

Description

Technical Field

[0001] This application relates to the field of display panels, and in particular to an array substrate and a display panel. Background Technology

[0002] Array substrates are important structures in various display devices, such as thin-film transistor liquid crystal displays (TFT-LCDs) and organic light-emitting diode (OLED) displays.

[0003] An array substrate comprises a substrate and circuitry formed on its surface. The circuitry structure on the surface of the array substrate is quite intricate, typically consisting of multiple film layers, some of which are electrically connected by vias. Via failure leads to abnormal electrical connections between film layers, and vias are relatively prone to failure during the fabrication of array substrates, significantly impacting the yield rate. Summary of the Invention

[0004] This application provides an array substrate and a display panel that can reduce the possibility of via failure and improve the yield of the array substrate.

[0005] A first aspect of this application provides an array substrate, the array substrate comprising:

[0006] Substrate;

[0007] The first signal line is located on the surface of the substrate.

[0008] A first pattern layer is located on the side of the first signal line away from the substrate. The first pattern layer is connected to the first signal line through a first via. A first orthographic projection portion is located outside the second orthographic projection. The first orthographic projection is the orthographic projection of the first via on the substrate, and the second orthographic projection is the orthographic projection of the first signal line on the substrate.

[0009] In some examples, at least one side of the second orthographic projection extends through the first orthographic projection.

[0010] In some examples, the first end of the second orthographic projection is located within the first orthographic projection.

[0011] In some examples, the first end of the second orthographic projection is an arc shape.

[0012] In some examples, the first signal line includes a connector and a linear body, the width of the connector being greater than the width of the linear body, and the first via connecting the first pattern layer and the connector.

[0013] In some examples, the first patterned layer is also connected to the connection portion via at least one second via, the second via being located outside the second orthographic projection portion of the substrate.

[0014] In some examples, the first patterning layer includes a source-drain patterning layer;

[0015] The array substrate includes an electrostatic discharge (ESD) protection circuit, which includes a diode ring located in the non-display area of ​​the substrate. The diode ring includes a gate pattern layer and a source / drain pattern layer. The gate pattern layer is located on the side of the source / drain pattern layer closer to the substrate. The gate pattern layer and the source / drain pattern layer are connected through a third via.

[0016] In some examples, the third via is located outside the orthogonal projection of the gate pattern layer onto the substrate.

[0017] In some examples, the overlap area between the first via and the first signal line is greater than the overlap area between the third via and the gate pattern layer.

[0018] A second aspect of this application also provides a display panel, the display panel including a cell substrate and an array substrate as described in the first aspect, the cell substrate and the array substrate being arranged opposite to each other.

[0019] In a first aspect of this application, a first signal line and a first pattern layer are formed on a substrate. The first pattern layer is connected to the first signal line through a first via. Since the orthographic projection of the first via on the substrate is outside the orthographic projection of the first signal line on the substrate, only a portion of the bottom of the first via is located on the surface of the first signal line, while the remaining portion is outside the first signal line. The formed first pattern layer is less prone to breakage at the connection between the portion of the first via bottom outside the first signal line and the via wall, thus reducing the possibility of via failure and improving the yield of the array substrate.

[0020] It is understandable that the beneficial effects of the second aspect mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a partial structural schematic diagram of an array substrate provided as an example of this application;

[0023] Figure 2 yes Figure 1 AA section diagram;

[0024] Figure 3 This is a partial structural diagram of an array substrate;

[0025] Figure 4 This is a partial structural diagram of the array substrate during the manufacturing process;

[0026] Figure 5 This is a top view schematic diagram of an array substrate provided in Embodiment 2 of this application;

[0027] Figure 6 This is an equivalent circuit diagram of the electrostatic discharge protection circuit provided in the embodiments of this application;

[0028] Figure 7 yes Figure 5 A magnified view of a portion of the image;

[0029] Figure 8 yes Figure 7 BB cross-section diagram;

[0030] Figure 9 This is a schematic diagram of the non-display area of ​​the array substrate provided in Embodiment 2 of this application;

[0031] Figure 10 This is an equivalent circuit diagram of an electrostatic discharge protection circuit for an array substrate provided in Embodiment 3 of this application;

[0032] Figure 11 This is a schematic diagram of the structure of an array substrate provided in Embodiment 3 of this application;

[0033] Figure 12 This is a partial structural schematic diagram of an array substrate provided in an embodiment of this application;

[0034] Figure 13 This is a partial structural schematic diagram of an array substrate provided in an embodiment of this application.

[0035] Icon labels:

[0036] Substrate: 10; Display area: 10a; Non-display area: 10b; First pattern layer: 100; First portion: 100a; Second portion: 100b; Third portion: 100c; Signal line: 101; Second pattern layer: 102; Via: 103; Insulating layer: 104; Recess: 105; First signal line: 11; Connector: 111; Linear body: 112; Electrostatic discharge protection circuit: 20; Second signal line: 21; Diode ring: 22; Gate pattern layer: 221; Source / drain pattern layer: 222; Active pattern layer: 223; First gate: 2211; Second gate: 2212 Third gate: 2213; Fourth gate: 2214; First active layer: 2231; Second active layer: 2232; Third active layer: 2233; Fourth active layer: 2234; First source-drain layer: 2221; Second source-drain layer: 2222; Third source-drain layer: 2223; First electrode: 222a; Second electrode: 222b; First insulating layer: 31; Second insulating layer: 32; Third insulating layer: 33; Fourth insulating layer: 34; First via: 31a; Second via: 31d; Third via: 31c; Fourth via: 31c; Gate drive unit: 40; Bridge connection: 41. Detailed Implementation

[0037] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0038] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0039] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0040] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0041] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0042] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. "A plurality" means two or more.

[0043] Example 1

[0044] Vias are important structures for achieving electrical connections between different film layers in array substrates, and they are widely present in array substrates. Figure 1 This is a partial structural schematic diagram of an array substrate provided as an example of this application.

[0045] Figure 1 The image shows two film layers of the array substrate, such as... Figure 1 As shown, one of the film layers includes a signal line 101, and the other film layer includes a second pattern layer 102, which is connected to the signal line 101 through a via 103.

[0046] Figure 2 yes Figure 1 AA section diagram. (See diagram below.) Figure 2 As shown, an insulating layer 104 is provided between the two film layers. A portion of the second pattern layer 102 is located inside the via 103, covering the wall of the via 103 and the surface of the signal line 101 exposed at the bottom of the via.

[0047] Figure 3 This is a partial structural diagram of an array substrate. Figure 3This is a partial cross-sectional view of the array substrate obtained using microscopic equipment. For example... Figure 3 As shown, the second patterned layer 102 is fractured at the bottom edge of via 103. If the fracture is complete around the entire circumference of the bottom edge of via 103, the electrical connection between the two film layers will be completely broken, thereby reducing the yield of the array substrate. This defect can occur between any two film layers connected by vias within the array substrate.

[0048] like Figure 3 As indicated by the circle, at the bottom of via 103, there is a recess 105 on the surface of the signal line 101, located at the edge of the bottom of the via. Research has shown that this recess 105 affects the adhesion of the film layer at the bottom edge of the via, leading to film layer breakage. Regarding the formation mechanism of the recess 105, research has found that during the etching of the insulating layer 104 to form the via 103, for example, during dry etching, the exposed signal line 101 at the bottom of the via will inevitably be etched to some extent. During etching, etching gas tends to accumulate at the edge of the bottom of the via, resulting in a greater degree of etching of the signal line 101 at that edge, thus forming the recess 105 at the bottom edge of the via. Figure 4 This is a partial structural diagram of the array substrate during the manufacturing process. Figure 4 This is a structural diagram obtained using microscopic equipment after the via 103 has been fabricated, such as... Figure 4 As shown, a full-circle recess 105 is formed at the edge of the bottom of the hole. The recess 105 at the bottom of the hole may cause the film layer to break at the edge of the bottom of the hole, thereby reducing the yield of the array substrate.

[0049] Example 2

[0050] This application provides an array substrate, which includes a substrate, a first signal line, and a first pattern layer. The first signal line is located on one side of the substrate; the first pattern layer is located on the side of the first signal line away from the substrate, and the first pattern layer is connected to the first signal line through a first via. A first orthographic projection portion is located outside a second orthographic projection, where the first orthographic projection is the orthographic projection of the first via onto the substrate, and the second orthographic projection is the orthographic projection of the first signal line onto the substrate.

[0051] During the fabrication of the first via, even if the exposed first signal line at the bottom of the via is etched, forming a depression, fracture will only occur at the interface between the surface of the first signal line and the wall of the first via during the formation of the first pattern layer. No fracture will occur at the interface between the area at the bottom of the first via, other than the first signal line, and the via wall. This ensures a good connection between the first signal line and the first pattern layer, preventing via failure and improving the yield of the array substrate.

[0052] The first signal line and the first pattern layer can be any signal line and any pattern layer arranged in different layers in the array substrate and connected by vias. The first signal line can be located in the display area or non-display area of ​​the substrate, or part of it can be located in the display area and part of it can be located in the non-display area; the first pattern layer can be located in the display area or non-display area of ​​the substrate, or part of it can be located in the display area and part of it can be located in the non-display area.

[0053] Figure 5 This is a top view schematic diagram of an array substrate provided in Embodiment 2 of this application. The array substrate provided in this embodiment will be described in detail below using this array substrate as an example. Figure 5 As shown, the array substrate includes a substrate 10 and circuitry formed on one side of the substrate 10. The substrate 10 serves as a carrier and has a display area 10a and a non-display area 10b. The display area 10a is generally located in the center of the substrate 10, and the non-display area 10b is generally located at the edge of the substrate 10.

[0054] The circuit includes a first signal line 11 and an electrostatic discharge (ESD) protection circuit 20, with one end of the first signal line 11 connected to the ESD protection circuit 20. As an example, both the first signal line 11 and the ESD protection circuit 20 are located in the non-display area 10b of the substrate 10.

[0055] Figure 6 This is an equivalent circuit diagram of the electrostatic discharge protection circuit provided in the embodiments of this application. For example... Figure 6 As shown, the electrostatic discharge protection circuit 20 may include a second signal line 21 and several diode rings (DRs) 22. The diode rings 22 are located in the non-display area 10b.

[0056] Figure 7 yes Figure 5 A magnified view of a portion of the image. (See attached image.) Figure 7 As shown, the diode ring 22 includes a gate pattern layer 221, a source-drain pattern layer 222, and an active pattern layer 223. Both the active pattern layer 223 and the source-drain pattern layer 222 are located on the side of the gate pattern layer 221 away from the substrate 10. In this example, the first pattern layer 100 may include the source-drain pattern layer 222.

[0057] In this embodiment, the gate pattern layer 221, the active pattern layer 223, and the source / drain pattern layer 222 form two thin-film transistors.

[0058] The gate pattern layer 221 includes a first gate 2211 and a second gate 2212.

[0059] The active patterned layer 223 includes a first active layer 2231 and a second active layer 2232. The first active layer 2231 is located on the side of the first gate 2211 away from the substrate 10, and the first active layer 2231 at least partially overlaps with the first gate 2211. The second active layer 2232 is located on the side of the second gate 2212 away from the substrate 10, and the second active layer 2232 at least partially overlaps with the second gate 2212.

[0060] In this embodiment, the overlap of two structures means that the orthographic projections of the two structures on the surface of the substrate 10 overlap, that is, at least a portion of the orthographic projection of one structure on the surface of the substrate 10 lies within the orthographic projection of the other structure on the surface of the substrate 10. For example, the partial overlap of the second active layer 2232 and the second gate 2212 means that the orthographic projections of the second active layer 2232 and the second gate 2212 on the surface of the substrate 10 overlap, that is, at least a portion of the orthographic projection of the second active layer 2232 on the surface of the substrate 10 lies within the orthographic projection of the second gate 2212 on the surface of the substrate 10. The overlap area of ​​the two structures refers to the area of ​​the overlapping portion of the orthographic projections of the two structures on the surface of the substrate 10.

[0061] The source-drain pattern layer 222 includes a first source-drain layer 2221 and a second source-drain layer 2222. The first source-drain layer 2221 includes a first electrode 222a and a second electrode 222b. The second source-drain layer 2222 also includes a first electrode 222a and a second electrode 222b. The first electrode 222a is one of the source and the drain, and the second electrode 222b is the other of the source and the drain.

[0062] The first gate 2211 is connected to the first signal line 11, and there are gaps between the second gate 2212 and the first gate 2211, and between the second gate 2212 and the first signal line 11.

[0063] The first source-drain layer 2221 partially overlaps with the first gate 2211 and the second gate 2212, respectively. Specifically, the first electrode 222a of the first source-drain layer 2221 partially overlaps with the first gate 2211 and the first active layer 2231; the second electrode 222b of the first source-drain layer 2221 partially overlaps with the second gate 2212 and the second active layer 2232.

[0064] The second source-drain layer 2222 partially overlaps with the first gate 2211 and the second gate 2212, respectively. Specifically, the first electrode 222a of the second source-drain layer 2222 partially overlaps with the second gate 2212 and the second active layer 2232; the second electrode 222b of the second source-drain layer 2222 partially overlaps with the first gate 2211 and the first active layer 2231.

[0065] like Figure 7 As shown, the first pattern layer 100 is connected to the first signal line 11 through a first via 31a. In this example, the first pattern layer 100 includes a source-drain pattern layer 222, and the first source-drain layer 2221 in the source-drain pattern layer 222 is connected to the first signal line 11 through the first via 31a. The portion of the first via 31a projected onto the substrate 10 is located outside the projection of the first signal line 11 onto the substrate 10.

[0066] In this embodiment of the application, unless otherwise specified, "connected via" refers to achieving an electrical connection, which is implemented by a structure located within the via. The structure within the via used to achieve the electrical connection can be part of either of the two structures at both ends of the via, or it can be a structure other than the two structures at both ends of the via. For example, if the first signal line 11 is connected to the first source-drain layer 2221 through the first via 31a, it means that the first signal line 11 and the first source-drain layer 2221 form an electrical connection, and the structure within the first via 31a used to achieve the electrical connection between the first signal line 11 and the first source-drain layer 2221 is the portion of the first source-drain layer 2221 located within the first via 31a.

[0067] Figure 8 yes Figure 7 The BB cross-sectional view. For example... Figure 8 As shown, the array substrate also includes a first insulating layer 31, which is located on the side of the first signal line 11 away from the substrate 10. A first via 31a is located in the first insulating layer 31.

[0068] In this embodiment, the orthographic projection of the first via 31a onto the substrate 10 is located outside the orthographic projection of the first signal line 11 onto the substrate 10. That is, the portion of the first source / drain layer 2221 located within the first via 31a, i.e., the portion of the first pattern layer 100 located within the first via 31a, has a portion located on the surface of the first signal line 11 and a portion located on the surface of the substrate 10. For ease of explanation, the portion of the first pattern layer 100 located on the surface of the first signal line 11 within the first via 31a is defined as the first portion 100a, the portion of the first pattern layer 100 located on the surface of the substrate 10 is defined as the second portion 100b, and the portion of the first pattern layer 100 located on the wall of the first via 31a is defined as the third portion 100c.

[0069] During the fabrication of the first via 31a, even at the bottom of the first via 31a, the exposed surface of the first signal line 11 is etched, forming a depression. During the fabrication of the source-drain pattern layer 222, only the first portion 100a and the third portion 100c of the first source-drain layer 2221 will break, affecting the connection between the first portion 100a and the third portion 100c of the first source-drain layer 2221. Since the second portion 100b of the first source-drain layer 2221 is located on the surface of the substrate 10, the surface of the substrate 10 will not form a groove during etching. Therefore, no breakage will occur between the second portion 100b and the third portion 100c of the first source-drain layer 2221, and the connection between the second portion 100b and the third portion 100c of the first source-drain layer 2221 will be affected. This allows the first signal line 11 to form a good connection with the first source-drain layer 2221, which is beneficial to improving the yield of the array substrate.

[0070] Furthermore, during the fabrication of the first via 31a, the edge portion of the first signal line 11 within the first via 31a will also be affected by etching, see... Figure 8 The area indicated by the dotted coil reduces the thickness of the edge of the first signal line 11 and makes the slope of the side more gentle. This is also conducive to the formation of the first source-drain layer 2221 on the surface of the first signal line 11, and the possibility of breakage between the first part 100a and the second part 100b is also reduced.

[0071] like Figure 7 As shown, the gate pattern layer 221 and the source / drain pattern layer 222 are also connected through a third via 31b.

[0072] In this example, the third via 31b connects the second source-drain layer 2222 and the second gate 2212.

[0073] Figure 7 In the example shown, the orthographic projection of the third via 31b onto the substrate 10 is located within the orthographic projection of the gate pattern layer 221 onto the substrate 10.

[0074] In some other possible implementations, the orthogonal projection of the third via 31b onto the substrate 10 may be partially located outside the orthogonal projection of the gate pattern layer 221 onto the substrate 10.

[0075] During the fabrication of the third via 31b, the gate pattern layer 221 will inevitably be etched, resulting in problems similar to those described in Embodiment 1. In this embodiment, a portion of the orthogonal projection of the third via 31b onto the substrate 10 is located outside the orthogonal projection of the gate pattern layer 221 onto the substrate 10. This avoids failure of the third via 31b, allowing the gate pattern layer 221 and the source / drain pattern layer 222 to form a good connection, which is beneficial for further improving the yield of the array substrate.

[0076] As an example, the overlap area between the first via 31a and the first signal line 11 is greater than the overlap area between the third via 31b and the gate pattern layer 221.

[0077] The larger the overlap area between the first via 31a and the first signal line 11, the larger the connection area between them. The first signal line 11 is typically quite long, and during the fabrication of the array substrate, it easily accumulates electrostatic charge. This can lead to electrostatic discharge at the first via 31a during the fabrication of the source / drain pattern layer 222, potentially damaging the via 31a. By setting a larger overlap area between the first via 31a and the first signal line 11, the connection area between them is increased, facilitating the release of electrostatic charge within the first signal line 11. This reduces the likelihood of the first via 31a being burned out by electrostatic discharge, further improving the yield of the array substrate.

[0078] like Figure 7 As shown, at least one side of the second orthographic projection passes through the first orthographic projection. That is, one side of the orthographic projection of the first signal line 11 on the substrate 10 passes through the orthographic projection of the first via 31a on the substrate 10.

[0079] The circuit structure of the array substrate is complex, and the positions of each via, signal line, and other structure need to be designed in advance during fabrication. If the position of a via is changed, due to space constraints, the positions of other structures often need to be adjusted as well. Typically, the orthographic projection of a via on the substrate 10 lies within the orthographic projection of the signal line on the substrate 10. In this example, one side of the second orthographic projection penetrates the first orthographic projection, meaning that the first via 31a is equivalent to... Figure 1 Based on the example shown, the position of via 103 was slightly adjusted. This has little impact on the layout of other structures during the fabrication of the array substrate, and it may not even require any adjustment to the position of other structures.

[0080] like Figure 7 As shown, the first signal line 11 includes a connecting portion 111 and a linear body 112. The width of the connecting portion 111 is greater than the width of the linear body 112, and the first via 31a connects the first pattern layer 100 and the connecting portion 111.

[0081] In this embodiment, the width of the linear body 112 refers to the distance between the two opposite sides of the linear body 112 in a direction parallel to the substrate 10 and perpendicular to the linear body 112. The width of the connecting portion 111 refers to the distance between the two opposite sides of the connecting portion 111 in a direction parallel to the substrate 10 and perpendicular to the linear body 112.

[0082] By providing a connecting part 111 with a larger width to connect with the first through hole 31a, it is convenient to set a larger first through hole 31a. Although Figure 7 In the width direction of the linear body 111, the width of the overlapping portion of the first via 31a and the first signal line 11 is smaller than the width of the linear body 111. However, since the width of the connecting portion 111 is larger than the width of the linear body 111, in some examples, the width of the overlapping portion of the first via 31a and the first signal line 11 can be set to be larger than the width of the linear body 111, so that the first signal line 11 and the first via 31a can have a larger contact area, which is beneficial to reduce the impedance of the first via 31a and improve the antistatic capability of the first via 31a.

[0083] In some other possible implementations, the first via 31a may also be connected to the linear body 112. As an example, both sides of the linear body 112's orthographic projection onto the substrate 10 extend through the orthographic projection of the first via 31a onto the substrate 10. The two sides of the linear body 112's orthographic projection onto the substrate 10 refer to two opposite sides; that is, the diameter of the first via 31a can be larger than the width of the linear body 112. This maximizes the area of ​​communication between the first via 31a and the linear body 112.

[0084] exist Figure 7 In the example shown, the first source-drain layer 2221 is connected to the connection portion 111 through a first via 31a. In other possible implementations, the first source-drain layer 2221 may also be connected to the connection portion 111 through multiple first vias 31a, which may be spaced apart along the edge of the connection portion 111. By providing multiple first vias 31a, the impedance between the first source-drain layer 2221 and the first signal line 11 can be reduced, the anti-static capability can be improved, and the possibility of disconnection between the first source-drain layer 2221 and the first signal line 11 can be further reduced.

[0085] like Figure 7 As shown, the electrostatic discharge protection circuit also includes a second signal line 21, which is arranged on the same layer as and connected to the source-drain pattern layer 222.

[0086] In this embodiment of the application, the second signal line 21 is connected to the second source-drain layer 2222.

[0087] The second signal line 21 is used to discharge static electricity. Exemplarily, the second signal line 21 can be a common signal line, i.e., a common signal line is reused for static electricity discharge. In other possible implementations, the second signal line 21 can also be a signal line other than a common signal line.

[0088] Figure 9 This is a schematic diagram of the non-display area of ​​the array substrate provided in Embodiment 2 of this application. Figure 9 As shown, the first pattern layer 100 may further include a bridging line 41, and the array substrate may further include a plurality of gate driving units 40. The plurality of gate driving units 40 are located between the first signal line 11 and the display area 10a, and the plurality of gate driving units 40 are arranged sequentially along the length direction of the first signal line 11.

[0089] The wiring on the surface of the substrate 10 typically includes pixel circuits located in the display area 10a and driving circuits located in the non-display area 10b. The driving circuits in the non-display area 10b may, for example, include a Gate Driver On Array (GOA) circuit. The gate driver circuit may further include a gate driver unit and a bus line. The gate driver unit is connected to the pixel circuits located in the display area 10a, and the bus line may include a clock signal line (CK). As an example, in this embodiment, the first signal line 11 may be a clock signal line.

[0090] The bridging wire 41 is connected to the first signal line 11 through a via. The orthogonal projection of the via onto the substrate 10 can be partially located outside the orthogonal projection of the first signal line 11 onto the substrate 10, so as to reduce the possibility of via failure and further improve the yield.

[0091] In other words, some or all of the vias connected to the same signal line can be configured as described above with the first via 31a to improve the yield of the array substrate.

[0092] The bridging wire 41 can be arranged on the same layer as the source-drain pattern layer 222, and the first signal line 11 is connected to the gate driving unit 40 through the bridging wire 41. Since they are arranged on the same layer, the bridging wire 41 and the source-drain pattern layer 222 can be formed in the same patterning process to save process time.

[0093] For example, the first signal line 11 can be a single-layer structure made of metal material, such as a single-layer structure formed by metal copper Cu, or a multi-layer structure made of metal material, such as Al / Mo / MTD material, that is, a multi-layer structure of aluminum layer, molybdenum layer, and molybdenum nickel titanium alloy layer.

[0094] The first insulating layer 31 may be located in the display area 10a and the non-display area 10b. Exemplarily, the first insulating layer 31 may be a gate insulating layer. The first insulating layer 31 may be made of an inorganic non-metallic material; for example, the first insulating layer 31 may include at least one of a silicon nitride layer and a silicon oxide layer. Exemplarily, the first insulating layer 31 includes SiN. x Layers and stacks in SiN x SiO layer on the side away from the substrate 10 x layer.

[0095] For example, the thin-film transistor in the electrostatic discharge protection circuit 20 can be an oxide thin-film transistor, and the first active layer 2231 and the second active layer 2232 can be metal oxide semiconductor layers. In some examples, the thin-film transistor can also be a polycrystalline silicon thin-film transistor, an amorphous silicon thin-film transistor, or other thin-film transistors.

[0096] like Figure 8 As shown, the array substrate further includes a second insulating layer 32, a third insulating layer 33, and a fourth insulating layer 34. The second insulating layer 32 covers the side of the source-drain pattern layer 222 away from the substrate 10, the third insulating layer 33 is located on the side of the second insulating layer 32 away from the substrate 10, and the fourth insulating layer 34 is located on the side of the third insulating layer 33 away from the substrate 10.

[0097] The second insulating layer 32 may be located in the display area 10a and the non-display area 10b of the substrate 10. Exemplarily, the second insulating layer 32 may be a passivation layer (PVX), and the second insulating layer 32 may be made of an inorganic non-metallic material. For example, the second insulating layer 32 may include at least one of a silicon nitride layer and a silicon oxide layer. Exemplarily, the second insulating layer 32 includes SiO2. x Layers and stacks in SiO x SiN layer on the side away from the substrate 10 x layer.

[0098] The third insulating layer 33 can be made of inorganic non-metallic materials, such as a resin layer, a photoresist layer, or an acrylic layer. For example, the third insulating layer 33 can be a perfluoroalkoxy resin (PFA).

[0099] Optionally, the thickness of the third insulating layer 33 is 1.5 μm to 3 μm. The relatively thick thickness of the third insulating layer 33 is set to form a relatively flat surface, making the subsequently formed film layer relatively flat.

[0100] In the display area 10a, the array substrate may also include a common electrode located between the third insulating layer 33 and the fourth insulating layer 34.

[0101] For example, the common electrode can be fabricated using ITO (Indium Tin Oxide). The fourth insulating layer 34 can be made of SiN. x Made of materials.

[0102] Example 3

[0103] Figure 10 This is an equivalent circuit diagram of an electrostatic discharge (ESD) protection circuit for an array substrate provided in Embodiment 3 of this application. Figure 10 As shown, in this electrostatic discharge protection circuit, diode ring 22 includes four thin-film transistors. Figure 11 This is a schematic diagram of an array substrate provided in Embodiment 3 of this application. Compared to Figure 7 The example shown, Figure 10 In the array substrate shown, the gate pattern layer 221, the active pattern layer 223, and the source-drain pattern layer 222 form four thin-film transistors.

[0104] like Figure 11 As shown, in this array substrate, the gate pattern layer 221 further includes a third gate 2213 and a fourth gate 2214. The third gate 2213 is connected to the second gate 2212, and there are gaps between the fourth gate 2214 and the third gate 2213, and between the fourth gate 2214 and the second gate 2212.

[0105] The active pattern layer 223 further includes a third active layer 2233 and a fourth active layer 2234. The third active layer 2233 is located on the side of the third gate 2213 away from the substrate 10, and the third active layer 2233 at least partially overlaps with the third gate 2213. The fourth active layer 2234 is located on the side of the fourth gate 2214 away from the substrate 10, and the fourth active layer 2234 at least partially overlaps with the fourth gate 2214.

[0106] The second source-drain layer 2222 partially overlaps with the first gate 2211, the second gate 2212, the third gate 2213, and the fourth gate 2214, respectively. The second source-drain layer 2222 includes two first electrodes 222a and two second electrodes 222b. Specifically, one first electrode 222a partially overlaps with the second gate 2212 and the second active layer 2232; the other first electrode 222a partially overlaps with the third gate 2213 and the third active layer 2233; one second electrode 222b partially overlaps with the first gate 2211 and the first active layer 2231; and the other second electrode 222b partially overlaps with the fourth gate 2214 and the fourth active layer 2234.

[0107] The source-drain pattern layer 222 also includes a third source-drain layer 2223. The third source-drain layer 2223 includes a first electrode 222a and a second electrode 222b.

[0108] The third source-drain layer 2223 partially overlaps with the third gate 2213 and the fourth gate 2214, respectively. Specifically, the first electrode 222a of the third source-drain layer 2223 partially overlaps with the fourth gate 2214 and also partially overlaps with the fourth active layer 2234; the second electrode 222b of the third source-drain layer 2223 partially overlaps with the third gate 2213 and also partially overlaps with the third active layer 2233.

[0109] In this embodiment, the third source / drain layer 2223 and the fourth gate 2214 are connected through a fourth via 31c. The orthogonal projection of the fourth via 31c onto the substrate 10 may be partially located outside the orthogonal projection of the fourth gate 2214 onto the substrate 10, thereby reducing the possibility of failure of the fourth via 31c.

[0110] The electrostatic discharge protection circuit 20 can have various specific structures. As an example, this application provides an electrostatic discharge protection circuit 20 with four thin-film transistors. In other examples, the number of thin-film transistors in the electrostatic discharge protection circuit 20 can be three, five, six, etc.

[0111] Example 4

[0112] Figure 12 This is a partial structural schematic diagram of an array substrate provided in an embodiment of this application. For example... Figure 12 As shown in this example, the first signal line 11 includes a connecting portion 111 and a linear body 112. The width of the connecting portion 111 is greater than the width of the linear body 112. The first via 31a connects the first pattern layer 100 and the connecting portion 111.

[0113] The first pattern layer 100 and the connecting portion 111 are also connected through at least one second via 31d, the second via 31d being located outside the second orthographic projection portion of the substrate 10.

[0114] Figure 12 This example uses only one second via 31d. In other examples, there may be more second vias 31d, such as two, three or more.

[0115] Typically, the same signal line is connected to other film layers through multiple vias. The width of the linear body 112 is relatively small. By setting the connecting part 111, a larger area is provided to facilitate the arrangement of multiple vias, especially facilitating the arrangement of vias that are close to each other.

[0116] For example, in Figure 9 In the example shown, the first pattern layer 100 also includes a bridging wire 41, which is connected to the first signal line 11 through a via. The second via 31d here can be a via connecting the bridging wire 41 and the first signal line 11. For the bridging wire 41 that is relatively close to the first via 31a, it can be connected to the connection part 111 through the via.

[0117] Figure 12 The first pattern layer 100 shown includes two unconnected portions, with a first via 31a connected to one portion and a second via 31d connected to the other portion. In other examples, the first via 31a and the second via 31d may also be connected to the same portion of the first pattern layer 100. For example, in Figure 7 In the example shown, the first source-drain layer 2221 can be connected to the connection portion 111 through a via 31a and a second via 31d.

[0118] In other possible implementations, the first pattern layer 100 may also include other structures that can be connected to the connection portion 111 via vias.

[0119] Example 5

[0120] Figure 13 This is a partial structural schematic diagram of an array substrate provided in an embodiment of this application. For example... Figure 13 As shown, in this example, the first end of the second orthographic projection is located within the first orthographic projection, that is, one end of the first signal line 11 in the orthographic projection of the substrate 10 is located within the orthographic projection of the first via 31a in the substrate 10.

[0121] The first signal line 11 typically has two opposing ends, for example, one end is connected to the electrostatic discharge protection circuit 20, and the other end extends to the edge of the array substrate and is connected to the structure used for bonding.

[0122] The first end of the second orthographic projection can be the orthographic projection of the end of the first signal line 11 connected to the electrostatic protection circuit 20 onto the substrate 10.

[0123] During the transmission of an electrical signal from the first signal line 11 to the first pattern layer 100, the conduction path between the first signal line 11 and the first pattern layer 100 is as follows: from the first signal line 11 to the first portion 100a of the first pattern layer 100 located on the surface of the first signal line 11, then from the first portion 100a to the second portion 100b of the first pattern layer 100 located on the surface of the substrate 10, and then from the second portion 100b to the third portion 100c of the first pattern layer 100 located on the wall of the first via 31a. Since there is a risk of breakage between the first portion 100a and the third portion 100c, the path directly from the first portion 100a to the third portion 100c is ignored here. Based on the law of resistance, increasing the area of ​​the first portion 100a and increasing the length of the boundary line between the first portion 100a and the second portion 100b can reduce the resistance of the first via 31a, which is beneficial for the transmission of electrical signals between the first signal line 11 and the first pattern layer 100.

[0124] In this embodiment, since one end of the first signal line 11 in the orthographic projection of the substrate 10 is located within the orthographic projection of the first via 31a in the substrate 10, the boundary line between the first portion 100a and the second portion 100b has three segments. During the design of the array substrate, as the relative position of the first via 31a and the first signal line 11 is adjusted to increase the area of ​​the first portion 100a, the length of the boundary line between the first portion 100a and the second portion 100b will also increase significantly, which is beneficial for reducing the resistance of the first via 31a.

[0125] like Figure 13 As shown, the first end of the second orthographic projection is an arc shape.

[0126] In other words, the end of the first signal line 11 is convex. For example, the first end of the second orthographic projection is a semi-circular arc.

[0127] This not only slightly increases the length of the boundary line between the first part 100a and the second part 100b, but also makes the transition between the side and the first end of the first signal line 11 smoother. During the fabrication of the first pattern layer 100, the film layer is more easily formed at the corner of the end of the first signal line 11.

[0128] Example 6

[0129] Embodiment Six of this application provides a display panel, which may be, but is not limited to, a display panel used in mobile phones, tablets, laptops, monitors, smart wearable devices, or automotive display devices. The display panel includes a cell substrate and an array substrate, and the array substrate may be any of the array substrates shown in the foregoing embodiments.

[0130] Example 7

[0131] Embodiment 7 of this application provides a display device, which includes the display panel of the foregoing embodiments. The display device may be, but is not limited to, a mobile phone, tablet computer, laptop computer, monitor, smart wearable device, or vehicle display device.

[0132] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate (10); a first signal line (11) on one side of the substrate (10); a first pattern layer (100) on the side of the first signal line (11) away from the substrate (10), the first pattern layer (100) being connected to the first signal line (11) by a first via (31a), a first orthographic projection of the first via (31a) being outside a second orthographic projection of the first signal line (11), the second orthographic projection being the orthographic projection of the first signal line (11) on the substrate (10).

2. The array substrate of claim 1, wherein, At least one side of the second orthographic projection penetrates the first orthographic projection.

3. The array substrate of claim 1, wherein, A first end of the second orthographic projection is inside the first orthographic projection.

4. The array substrate of claim 3, wherein, The first end of the second orthographic projection is in the shape of a circular arc.

5. The array substrate of claim 1, wherein, The first signal line (11) comprises a connecting portion (111) and a linear main body (112), the width of the connecting portion (111) being greater than the width of the linear main body (112), the first via (31a) connecting the first pattern layer (100) and the connecting portion (111).

6. The array substrate of claim 5, wherein, The first pattern layer (100) and the connecting portion (111) are further connected by at least one second via (31d), the orthographic projection of the second via (31d) on the substrate (10) being outside the orthographic projection of the gate pattern layer (221) on the substrate (10).

7. The array substrate according to any one of claims 1 to 6, wherein, The first pattern layer (100) comprises a source-drain pattern layer (222). The array substrate comprises an electrostatic protection circuit (20), the electrostatic protection circuit (20) comprising a diode ring (22), the diode ring (22) being located in a non-display area (10b) of the substrate (10), the diode ring (22) comprising a gate pattern layer (221) and the source-drain pattern layer (222), the gate pattern layer (221) being located on the side of the source-drain pattern layer (222) close to the substrate (10), the gate pattern layer (221) and the source-drain pattern layer (222) being connected by a third via (31b).

8. The array substrate of claim 7, wherein, The orthographic projection of the third via (31b) on the substrate (10) is outside the orthographic projection of the gate pattern layer (221) on the substrate (10).

9. The array substrate of claim 7, wherein, The overlapping area of the first via (31a) and the first signal line (11) is greater than the overlapping area of the third via (31b) and the gate pattern layer (221).

10. A display panel, characterized by, The array substrate comprises a counter substrate, the counter substrate being arranged opposite to the array substrate.

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