Transistor module and method for manufacturing transistor module

Abstract

The present invention discloses a transistor module and a manufacturing method of the transistor module, wherein the transistor module comprises: a substrate; a drift layer of the first conductivity type, the transistor module comprises an insulated gate bipolar transistor region, a transition region and a fast recovery diode region; a secondary main junction region of the second conductivity type, the secondary main junction region is arranged in the transition region; a first groove; an insulating layer, a portion of the insulating layer corresponding to the transition region is provided with a first contact hole; a semiconductor region of the second conductivity type, the semiconductor region is arranged in the secondary main junction region, and the semiconductor region corresponds to the first contact hole; an emitter metal layer, a connection protrusion is provided on the emitter metal layer, the connection protrusion penetrates the first contact hole and is in contact and electrically connected with the semiconductor region. Thus, the avalanche current near the secondary main junction region can be relieved and led out through the first contact hole nearby, so that the voltage resistance of the transition region and even the transistor module can be further improved without sacrificing the performance and area of ​​the transistor module.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a transistor module and a method for manufacturing the transistor module. Background Art

[0002] RC-IGBT (reverse conducting-insulated gate bipolar transistor) refers to the integration of IGBT (insulated gate bipolar transistor) and FRD (fast recovery diode) on a single chip. Generally speaking, the industry usually integrates IGBT and FRD in the cell area of ​​the chip through a lumped or distributed method, and the two share terminals, thus realizing a highly integrated RC-IGBT, without the need to connect the two discrete devices IGBT and FRD through packaging.

[0003] In the related art, the voltage resistance of IGBT on the outside of the chip is mostly considered, so a more complex terminal structure is designed to improve the voltage resistance of the chip. However, due to less consideration of the voltage resistance of IGBT on the inside, in the case of higher voltage resistance, failure and burning occurred in the transition area between IGBT and FRD, which greatly reduced the stability of the RC-IGBT system. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a transistor module having better voltage resistance.

[0005] The present invention further provides a method for manufacturing a transistor module.

[0006] According to an embodiment of the present invention, a transistor module comprises: a substrate, the substrate having a first main surface and a second main surface on the opposite side of the first main surface, the first main surface and the second main surface are arranged at intervals in a first direction; a drift layer of a first conductivity type, the drift layer is arranged between the first main surface and the second main surface, the transistor module comprises an insulated gate bipolar transistor region, a transition region and a fast recovery diode region, the insulated gate bipolar transistor region is circumferentially arranged outside the fast recovery diode region, the transition region is arranged around the outside of the fast recovery diode region and is located between the insulated gate bipolar transistor region and the fast recovery diode region; a secondary main junction region of a second conductivity type, the secondary main junction region is arranged in the transition region, the secondary main junction region is arranged around the outside of the fast recovery diode region, the secondary main junction region is located on a side of the drift layer facing the first main surface, and a side of the secondary main junction region away from the drift layer constitutes at least a part of the first main surface; a first groove, the first groove is arranged in the transition region and is a plurality of, and the plurality of first grooves The length of the groove is extended in the second direction, and the plurality of first grooves are arranged at intervals in the third direction. The depth of at least part of the plurality of first grooves extends from the first main surface to the secondary main junction area in the first direction and does not extend out of the secondary main junction area, and the first direction, the second direction and the third direction are perpendicular to each other; an insulating layer, the insulating layer is arranged on the first main surface, and a first contact hole is arranged on a portion of the insulating layer corresponding to the transition area, and a projection of the first contact hole in the first direction is staggered from a projection of the first groove in the first direction; a semiconductor region of a second conductivity type, the semiconductor region is arranged in the secondary main junction area, and a side of the semiconductor region away from the drift layer constitutes at least a part of the first main surface, and the semiconductor region corresponds to the first contact hole; an emitter metal layer, the emitter metal layer is arranged on a side of the insulating layer away from the first main surface, and a connection protrusion is arranged on the emitter metal layer, and the connection protrusion passes through the first contact hole and is in contact and electrically connected with the semiconductor region.

[0007] Therefore, by providing a first contact hole in the portion of the insulating layer corresponding to the transition area, the semiconductor area is provided in the secondary main junction area, the semiconductor area corresponds to the first contact hole, and a connecting protrusion is provided on the emitter metal layer, so that the connecting protrusion passes through the first contact hole and is electrically connected to the semiconductor area, so that the avalanche current near the secondary main junction area can be relieved and led out through the first contact hole nearby, thereby further improving the voltage resistance of the transition area and even the transistor module without sacrificing the performance and area of ​​the transistor module.

[0008] In some examples of the present invention, there are a plurality of the first contact holes and a plurality of the semiconductor regions, and the plurality of the first contact holes and the plurality of the semiconductor regions are arranged in a one-to-one correspondence.

[0009] In some examples of the present invention, the projection of the secondary main junction region in the first direction covers the projections of the plurality of first contact holes in the first direction.

[0010] In some examples of the present invention, the projection of the secondary main junction region in the first direction covers a portion of the projections of the multiple first contact holes in the first direction, and another portion of the projections of the multiple first contact holes in the first direction is staggered with the projection of the secondary main junction region in the first direction.

[0011] In some examples of the present invention, a plurality of the first contact holes extend in the second direction and are spaced apart in the third direction; and / or a plurality of the first contact holes spaced apart in the second direction form a contact hole group, and the plurality of the contact hole groups are spaced apart in the third direction.

[0012] In some examples of the present invention, the first contact hole is in a strip shape; and / or the first contact hole is in a rectangular shape.

[0013] In some examples of the present invention, one first contact hole is provided between at least two adjacent first grooves among the plurality of first grooves; and / or a plurality of first contact holes are provided between at least two adjacent first grooves among the plurality of first grooves.

[0014] In some examples of the present invention, in a top view, the total area of ​​the first contact holes is S1, the total area of ​​the transition region is S2, and S1 and S2 satisfy the relationship: 0≤S1 / S2≤50%.

[0015] In some examples of the present invention, the ion doping concentration of the semiconductor region is greater than the ion doping concentration of the sub-main junction region.

[0016] In some examples of the present invention, the transistor module also includes a second trench and a third trench, the second trench is arranged in the fast recovery diode region and is multiple, the multiple second trenches are spaced apart in a third direction, the depth of the second trench extends from the first main surface toward the drift layer, the length of the second trench extends in the second direction, and the second trenches on both sides of the third direction of the multiple second trenches are first boundary trenches; the third trench is arranged in the insulated gate bipolar transistor region and is multiple, the multiple third trenches are spaced apart in the third direction, the depth of the third trench extends from the first main surface toward the drift layer, the length of the third trench extends in the second direction, the multiple third trenches include a main trench and a spacing trench, multiple main trenches spaced apart in the third direction are arranged on both sides of the multiple second trenches in the third direction, and the spacing trenches include a first spacing trench and a second spacing trench. The first spacing groove and the second spacing groove are respectively arranged on both sides of the second direction of the plurality of second grooves, and one of the plurality of main grooves on one side of the third direction of the plurality of second grooves adjacent to the plurality of second grooves is a second boundary groove; the secondary main junction area includes two first sub-secondary main junction areas and two second sub-secondary main junction areas, the two first sub-secondary main junction areas are respectively located on both sides of the third direction of the plurality of second grooves, the two second sub-secondary main junction areas are respectively located on both sides of the second direction of the plurality of second grooves and are respectively connected to the two first sub-secondary main junction areas, the projection of the first sub-secondary main junction area in the first direction is the first projection, the projections of the adjacent first boundary grooves and the second boundary grooves in the first direction are the second projection and the third projection respectively, the first projection is located between the second projection and the third projection in the third direction, and both sides of the first projection in the third direction do not exceed the second projection and the third projection.

[0017] In some examples of the present invention, one side of the first projection in the third direction coincides with a center line extending in the second direction of the second projection, and the other side of the first projection in the third direction coincides with a center line extending in the second direction of the third projection.

[0018] In some examples of the present invention, the widths of the first sub-sub main junction region and the second sub-sub main junction region are equal and are both D, and D satisfies the relationship: D≥4μm.

[0019] In some examples of the present invention, the transistor module also includes a base region of a second conductivity type, the base region is arranged on a side of the drift layer facing the first main surface, and the side of the base region away from the drift layer constitutes a part of the first main surface, the base region is multiple, the insulated gate bipolar transistor region, the transition region and the fast recovery diode region are all provided with the base region, the depth of the base region in the first direction is H1, the depth of the secondary main junction region in the first direction is H2, the thickness of the transistor module in the first direction is H3, H1≤H2≤0.5H3.

[0020] A manufacturing method of a transistor module according to an embodiment of the present invention is applicable to the transistor module described above, and the manufacturing method of the transistor module comprises the following steps: preparing a substrate, and arranging a drift layer of a first conductivity type in the substrate; simultaneously injecting doping ions of a second conductivity type into the terminal region and the transition region of the insulated gate bipolar transistor region to simultaneously form a main junction region in the terminal region of the insulated gate bipolar transistor region and a secondary main junction region in the transition region; etching a first trench in the transition region, the depth of the first trench extending from the first main surface to the secondary main junction region in the first direction and not extending out of the secondary main junction region; injecting doping ions of the second conductivity type into the secondary main junction region to form a base region; arranging an insulating layer on the first main surface; arranging a contact hole in a portion of the insulating layer corresponding to the transition region, the projection of the contact hole in the first direction being staggered from the projection of the first trench in the first direction, and injecting doping ions of the second conductivity type into the base region to form a semiconductor region; arranging an emitter metal layer on the insulating layer, and a connection protrusion on the emitter metal layer, the connection protrusion penetrating the contact hole and contacting the semiconductor region.

[0021] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0023] Figure 1 is a partial top view of a transistor module according to an embodiment of the present invention;

[0024] Figure 2 is a partial cross-sectional view of a transistor module along the AA direction according to an embodiment of the present invention;

[0025] Figure 3 is a flow chart of a method for manufacturing a transistor module according to an embodiment of the present invention;

[0026] Figure 4 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0027] Figure 5 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0028] Figure 6 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0029] Figure 7 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0030] Figure 8 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0031] Fig. 9 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0032] Fig.10 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0033] Fig.11 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0034] Fig.12 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0035] Fig.13 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention.

[0036] Reference numerals:

[0037] 100, transistor module; 110, insulated gate bipolar transistor region; 120, transition region; 130, fast recovery diode region;

[0038] 10. substrate; 101. first main surface; 102. second main surface; 11. drift layer; 12. secondary main junction region; 121. first sub-secondary main junction region; 122. second sub-secondary main junction region; 13. first trench; 14. semiconductor region; 15. second trench; 151. first boundary trench; 16. third trench; 161. main trench; 1611. second boundary trench; 162. spacing trench; 1621. first spacing trench; 17. base region; 18. field stop layer; 19. collector layer; 111. cathode layer;

[0039] 20, insulating layer; 21, first contact hole; 211, first sub-contact hole; 212, second sub-contact hole; 213, third sub-contact hole; 214, fourth sub-contact hole; 215, contact hole group; 22, second contact hole;

[0040] 30. emitter metal layer; 31. connection bump;

[0041] 40. Collector metal layer. DETAILED DESCRIPTION

[0042] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0043] Reference below Figure 1-Figure 13 The transistor module 100 according to the embodiment of the present invention is described. The transistor module 100 may adopt a manufacturing method of the transistor module 100. The transistor module 100 may be an RC-IGBT (reverse conducting-insulated gate bipolar transistor). In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type for description.

[0044] Combination Figure 1 and Figure 2 As shown, the transistor module 100 according to the present invention may mainly include: a base 10, a drift layer 11 of a first conductivity type, a secondary main junction region 12 of a second conductivity type, a first trench 13, an insulating layer 20, a semiconductor region 14 of a second conductivity type and an emitter metal layer 30.

[0045] Among them, the transistor module 100 may include an active area and a terminal area arranged outside the active area. The active area may mainly include an insulated gate bipolar transistor region 110, a transition region 120 and a fast recovery diode region 130. The insulated gate bipolar transistor region 110 is circumferentially arranged on the outside of the fast recovery diode region 130, so that the insulated gate bipolar transistor region 110 and the fast recovery diode region 130 can share the terminal region. In this way, the insulated gate bipolar transistor region 110 can realize forward conduction of the transistor module 100, and the fast recovery diode region 130 can realize reverse conduction of the transistor module 100, so that the transistor module 100 has the characteristics of forward conduction and reverse conduction at the same time.

[0046] Furthermore, by surrounding the transition region 120 on the outside of the fast recovery diode region 130 and being located between the insulated gate bipolar transistor region 110 and the fast recovery diode region 130, the transition region 120 can connect the insulated gate bipolar transistor region 110 and the fast recovery diode region 130, thereby ensuring the respective working performances of the insulated gate bipolar transistor region 110 and the fast recovery diode region 130 and improving the reliability of the transistor module 100.

[0047] Specifically, the substrate 10 has a first main surface 101 and a second main surface 102 on the opposite side of the first main surface 101, the first main surface 101 and the second main surface 102 are arranged at intervals in the first direction, the drift layer 11 is arranged between the first main surface 101 and the second main surface 102, a plurality of first trenches 13 are arranged in the transition region 120, the lengths of the plurality of first trenches 13 extend in the second direction, the plurality of first trenches 13 are arranged at intervals in the third direction, and the insulating layer 20 is arranged on the first main surface 101, wherein the first direction, the second direction and the third direction are perpendicular to each other. In this way, the basic structure of the transition region 120 can be formed.

[0048] Further, the secondary main junction region 12 is arranged in the transition region 120, the secondary main junction region 12 is arranged around the outer side of the fast recovery diode region 130, the secondary main junction region 12 is located on the side of the drift layer 11 facing the first main surface 101, the side of the secondary main junction region 12 away from the drift layer 11 constitutes at least a part of the first main surface 101, and the depth of at least part of the multiple first grooves 13 extends from the first main surface 101 to the secondary main junction region 12 in the first direction and does not extend out of the secondary main junction region 12. In this way, on the one hand, the secondary main junction region 12 can widen the depletion region at the edge of the insulated gate bipolar transistor region 110, can weaken the electric field peak, avoid the failure and burning of the transistor module 100 caused by local electric field concentration or excessive local electric field strength, and can improve the reliability of the transistor module 100. On the other hand, due to the introduction of the secondary main junction region 12 of the second conductivity type, the anode injection efficiency of the fast recovery diode region 130 can be improved, the forward conduction voltage drop of the fast recovery diode region 130 of the transistor module 100 can be reduced, and the system loss can be reduced.

[0049] It should be noted that the implantation of the secondary main junction region 12 can be performed together with the voltage-resistant structure of the terminal region, so that it can be compatible with the existing process without adding additional process steps, thus saving process steps and time costs.

[0050] Considering that when withstanding high voltage, the strong electric field enables the carriers to obtain enough energy in the mean free path, collide with the valence electrons in the crystal and free them from the valence bonds, excite the electrons in the valence band to the conduction band, and generate a pair of secondary electron-hole pairs. This process is called impact ionization. Subsequently, the generated pair of secondary electron-hole pairs continue to collide with the particles in the crystal to form an avalanche multiplication process similar to a chain reaction, resulting in an instantaneous increase in the current in the transistor module 100 in a short period of time, generating an avalanche current. If the avalanche current cannot be discharged in time, the accumulated avalanche current will cause local overheating and cause the transistor module 100 to fail.

[0051] The first contact hole 21 is provided at the portion of the insulating layer 20 corresponding to the transition region 120, so that the projection of the first contact hole 21 in the first direction is staggered with the projection of the first trench 13 in the first direction, and the semiconductor region 14 is provided in the secondary main junction region 12, and the side of the semiconductor region 14 away from the drift layer 11 constitutes at least a part of the first main surface 101, so that the semiconductor region 14 corresponds to the first contact hole 21. In addition, the emitter metal layer 30 is provided at the side of the insulating layer 20 away from the first main surface 101, and the emitter metal layer 30 is provided with a connection protrusion 31, so that the connection protrusion 31 passes through the first contact hole 21 and contacts and electrically connects with the semiconductor region 14.

[0052] In this way, the avalanche current near the secondary main junction region 12 can be relieved and led out through the semiconductor region 14, the first contact hole 21 and the emitter metal layer 30 in sequence, thereby shortening the avalanche current path, avoiding the accumulation of avalanche current and causing local overheating, and improving the withstand voltage capability of the transistor module 100. Among them, the setting of the semiconductor region 14 can further improve the current carrying capacity, and improve the rate and reliability of leading out the avalanche current.

[0053] It should be noted that since the first contact hole 21 is located in the transition area 120, the space in the transition area 120 can be fully utilized without increasing the overall area of ​​the transistor module 100. This can improve the voltage resistance of the transistor module 100 while improving the integration of the transistor module 100, and can reduce the loss of the transistor module 100, thereby improving the utilization rate of the wafer and reducing the cost.

[0054] Furthermore, to ensure the normal operation of the transistor module 100, a second contact hole 22 needs to be opened on the insulating layer 20, and doping ions of the second conductive type need to be injected under the second contact hole 22. During production, the first contact hole 21 and the second contact hole 22 can be opened and doping ions can be injected at the same time, so that it can be compatible with the existing process without adding additional process steps, thus saving process steps and time costs.

[0055] Therefore, by providing a first contact hole 21 on a portion of the insulating layer 20 corresponding to the transition region 120, the semiconductor region 14 is provided in the secondary main junction region 12, the semiconductor region 14 corresponds to the first contact hole 21, and a connecting protrusion 31 is provided on the emitter metal layer 30, so that the connecting protrusion 31 passes through the first contact hole 21 and is electrically connected to the semiconductor region 14, so that the avalanche current near the secondary main junction region 12 can be relieved and led out through the first contact hole 21 nearby, so that without sacrificing the performance and area of ​​the transistor module 100, the voltage resistance of the transition region 120 and even the transistor module 100 can be further improved.

[0056] Combination Figure 2 As shown, there are multiple first contact holes 21, multiple semiconductor regions 14, and the multiple first contact holes 21 and the multiple semiconductor regions 14 are arranged one-to-one. Specifically, the first contact holes 21 can be arranged in multiples, and the multiple first contact holes 21 are arranged at intervals, and the semiconductor regions 14 can also be arranged in multiples, and the multiple first contact holes 21 and the multiple semiconductor regions 14 are arranged one-to-one. In this way, a leakage channel in which multiple first contact holes 21 and the corresponding semiconductor regions 14 act together can be formed in the secondary main junction region 12, so that the path of the avalanche current can be further shortened, and the avalanche current can be timely led out from above the secondary main junction region 12, thereby further improving the structural reliability of the transistor module 100.

[0057] Further, the ion doping concentration of the semiconductor region 14 is greater than the ion doping concentration of the secondary main junction region 12. Specifically, the ion doping concentration of the semiconductor region 14 can be set to be greater than the ion doping concentration of the secondary main junction region 12, so that the electric field distribution in the area below the first contact hole 21 can be optimized, and the current flow capacity can be improved, so that the avalanche current near the secondary main junction region 12 can be more timely and effectively led out through the first contact hole 21, and the voltage resistance of the transistor module 100 can be improved.

[0058] In some embodiments of the present invention, the projection of the secondary main junction region 12 in the first direction covers the projection of the multiple first contact holes 21 in the first direction. In this way, the multiple first contact holes 21 can all be located in the area where the secondary main junction region 12 is located, thereby ensuring the timely lead-out of the avalanche current.

[0059] In other embodiments of the present invention, the projection of the secondary main junction region 12 in the first direction covers a portion of the projections of the plurality of first contact holes 21 in the first direction, and the other portion of the projections of the plurality of first contact holes 21 in the first direction is staggered with the projection of the secondary main junction region 12 in the first direction. Specifically, when the projection of the secondary main junction region 12 in the first direction does not completely cover the transition region 120, other positions in the transition region 120 except the position where the secondary main junction region 12 is located are available for setting the semiconductor region 14 and the corresponding first contact holes 21, and by making the projection of the secondary main junction region 12 in the first direction cover a portion of the projections of the plurality of first contact holes 21 in the first direction, the other portion of the projections of the plurality of first contact holes 21 in the first direction is staggered with the projection of the secondary main junction region 12 in the first direction, thereby ensuring the timely extraction of the avalanche current.

[0060] It should be noted that, in some further embodiments of the present invention, Figure 1 As shown, the multiple first contact holes 21 include multiple first sub-contact holes 211 and multiple second sub-contact holes 212, the projection of the secondary main junction region 12 in the first direction covers the projection of the multiple first sub-contact holes 211 in the first direction, and the projection of the secondary main junction region 12 in the first direction covers a part of the projection of the multiple second sub-contact holes 212 in the first direction, and the other part of the projection of the multiple second sub-contact holes 212 in the first direction is staggered with the projection of the secondary main junction region 12 in the first direction, which is not elaborated here.

[0061] Furthermore, the specific positions of the plurality of first contact holes 21 relative to the secondary main junction region 12 can be designed according to the specific width of the secondary main junction region 12, the length of the first contact holes 21, actual application requirements, etc., and are not specifically limited here.

[0062] In some embodiments of the present invention, a plurality of first contact holes 21 extend in the second direction and are arranged at intervals in the third direction. In this way, a first contact hole 21 extending continuously in the second direction can lead out the avalanche current in the second direction, and a plurality of first contact holes 21 arranged at intervals in the third direction can lead out the avalanche current at different positions in the third direction, thereby not only shortening the number of first contact holes 21 and facilitating the opening of the first contact holes 21, but also making the setting positions of the plurality of first contact holes 21 more reasonable and orderly, leading out the avalanche current near the secondary main junction region 12 in time, and improving the withstand voltage capability of the transistor module 100.

[0063] In other embodiments of the present invention, a plurality of first contact holes 21 spaced apart in the second direction form a contact hole group 215, and there are a plurality of contact hole groups 215, and the plurality of contact hole groups 215 are spaced apart in the third direction. In this way, the plurality of first contact holes 21 in the contact hole group 215 can lead out the avalanche current in the second direction, and the plurality of contact hole groups 215 spaced apart in the third direction can lead out the avalanche current at different positions in the third direction, so that the setting positions of the plurality of first contact holes 21 can be made more reasonable and orderly, and the avalanche current near the secondary main junction region 12 can be led out in time, thereby improving the withstand voltage capability of the transistor module 100.

[0064] It should be noted that, in some further embodiments of the present invention, Figure 1 As shown, the multiple first contact holes 21 include multiple third sub-contact holes 213 and multiple fourth sub-contact holes 214, so that the multiple third sub-contact holes 213 can extend in the second direction and be spaced apart in the third direction, and the multiple fourth sub-contact holes 214 can form a contact hole group 215. There are multiple contact hole groups 215, and the multiple contact hole groups 215 are spaced apart in the third direction, which will not be elaborated here.

[0065] Combination Figure 1 As shown, the first contact hole 21 is in the shape of an elongated strip, or the first contact hole 21 is in the shape of a rectangle. Specifically, the shape of the first contact hole 21 includes but is not limited to an elongated strip and a rectangle. In actual production, it can be selected according to demand to facilitate the production of the first contact hole 21. It should be noted that the plurality of first contact holes 21 can also be a combination of a rectangle and an elongated strip, which will not be described in detail here.

[0066] In some embodiments of the present invention, Figure 1 and Figure 2 As shown, a first contact hole 21 is disposed between at least two adjacent first trenches 13 among the plurality of first trenches 13; and / or a plurality of first contact holes 21 are disposed between at least two adjacent first trenches 13 among the plurality of first trenches 13. In this way, the space between at least two adjacent first trenches 13 among the plurality of first trenches 13 can be fully utilized, and the arrangement of one or more first contact holes 21 is facilitated without increasing the area of ​​the transistor module 100 and without affecting the normal operation of the first trenches 13, thereby improving the reliability of the transistor module 100. It should be noted that the specific number of the first contact holes 21 between at least two adjacent first trenches 13 among the plurality of first trenches 13 can be adjusted according to actual conditions, and is not specifically limited here.

[0067] Furthermore, in a top view, the total area of ​​the first contact holes 21 is S1, the total area of ​​the transition region 120 is S2, and S1 and S2 satisfy the relationship: 0≤S1 / S2≤50%.

[0068] Specifically, the ratio between the total area of ​​the first contact holes 21 and the total area of ​​the secondary main junction region 12 , that is, the area proportion of the first contact holes 21 in the secondary main junction region 12 , will affect the size of the avalanche current flux discharged by the first contact holes 21 .

[0069] For a transistor module 100 with a lower voltage specification, it may be selected not to provide the first contact hole 21 .

[0070] For the transistor module 100 with a higher voltage specification, on the one hand, by setting the first contact hole 21, it is possible to prevent the avalanche current from being unable to be discharged in time above the secondary main junction area 12, causing excessive local current, and then causing local hot spots and burning problems. On the other hand, the ratio between the total area of ​​the first contact hole 21 and the total area of ​​the secondary main junction area 12 can be set to be no more than 50% to prevent excessive injection of second conductive type doped ions in the semiconductor region 14 below the first contact hole 21, resulting in increased anode minority carrier injection and prolonged reverse recovery performance time, thereby avoiding negative impact on the reverse recovery performance of the fast recovery diode area 130.

[0071] Combination Figure 1 and Figure 2 As shown, the transistor module 100 may further include a second trench 15, the second trench 15 is arranged in the fast recovery diode region 130 and is a plurality of second trenches 15, the plurality of second trenches 15 are arranged at intervals in the third direction, the depth of the second trench 15 extends from the first main surface 101 toward the drift layer 11, the length of the second trench 15 extends in the second direction, and an oxide insulating layer 20 and polysilicon are arranged on one side of the second trench 15, and the second trench 15 is electrically connected to the emitter metal layer 30. Among them, the second trenches 15 defining the second trenches 15 on both sides of the third direction of the plurality of second trenches 15 are first boundary trenches 151.

[0072] Furthermore, the transistor module 100 may also include a third trench 16, which is arranged in the insulated gate bipolar transistor region 110 and is multiple, and the multiple third trenches 16 are spaced apart in the third direction, the depth of the third trench 16 extends from the first main surface 101 toward the drift layer 11, the length of the third trench 16 extends in the second direction, and an oxide insulating layer 20 and polysilicon are sequentially arranged in the third trench 16, so that a gate can be formed at the third trench 16, and the multiple third trenches 16 are electrically connected to the gate pad.

[0073] Among them, the multiple third grooves 16 can mainly include main grooves 161 and spacing grooves 162, and the multiple second grooves 15 are provided with multiple main grooves 161 spaced apart in the third direction on both sides thereof, and the spacing grooves 162 include first spacing grooves 1621 and second spacing grooves 162, and the first spacing grooves 1621 and the second spacing grooves 162 are respectively spaced apart on both sides of the second direction of the multiple second grooves 15, and one of the multiple main grooves 161 adjacent to the multiple second grooves 15 on one side of the third direction of the multiple second grooves 15 is defined as a second boundary groove 1611.

[0074] Combination Figure 1 and Figure 2 As shown, the secondary main junction region 12 can mainly include two first sub-sub-main junction regions 121 and two second sub-sub-main junction regions 122. The two first sub-sub-main junction regions 121 are respectively located on both sides of the third direction of the plurality of second grooves 15, and the two second sub-sub-main junction regions 122 are respectively located on both sides of the second direction of the plurality of second grooves 15 and are respectively connected to the two first sub-sub-main junction regions 121, so that the secondary main junction region 12 can be closed as a whole and surround the outside of the fast recovery diode region 130.

[0075] The projection of the first sub-sub main junction region 121 in the first direction is defined as the first projection, and the projections of the adjacent first boundary trenches 151 and the second boundary trenches 1611 in the first direction are defined as the second projection and the third projection, respectively. It can be understood that: the second projection is located between the transition region 120 and the fast recovery diode region 130, and the third projection is located between the transition region 120 and the insulated gate bipolar transistor region 110. By making the first projection located between the second projection and the third projection in the third direction, and both sides of the first projection in the third direction do not exceed the second projection and the third projection, the width design of the first sub-sub main junction region 121 can be optimized, and the width of the first sub-sub main junction region 121 is avoided to be too wide to affect the insulated gate bipolar transistor region 110 and the fast recovery diode region 130, so as to ensure the normal operation of the transistor module 100.

[0076] In a preferred embodiment of the present invention, Figure 2 As shown, one side of the third direction of the first projection coincides with the center line extending in the second direction of the second projection, and the other side of the third direction of the first projection coincides with the center line extending in the second direction of the third projection.

[0077] Specifically, the center line extending in the second direction of the second projection and the center line extending in the second direction of the third projection are respectively located at the two side boundaries of the width direction of the transition region 120. By making one side of the third direction of the first projection coincide with the center line extending in the second direction of the second projection, and making the other side of the third direction of the first projection coincide with the center line extending in the second direction of the third projection, the projection of the secondary main junction region 12 in the first direction can coincide with the projection of the transition region 120 in the first direction, thereby widening the depletion region to the greatest extent without increasing the loss of doping ions, thereby improving the voltage resistance of the transistor module 100.

[0078] Furthermore, combined with Figure 1 As shown, the widths of the first sub-sub main junction region 121 and the second sub-sub main junction region 122 are equal and are both D, and D satisfies the relationship: D ≥ 4 μm. Specifically, by making the widths of the first sub-sub main junction region 121 and the second sub-sub main junction region 122 equal, the overall width distribution of the main junction region can be made more uniform and reasonable, and the electric field modulation effect of the sub-sub main junction region 12 on the position is made more uniform, thereby improving the reliability of the transistor module 100.

[0079] Furthermore, the width of the first sub-sub main junction region 121 and the width of the second sub-sub main junction region 122 are set to be no less than 4 μm, so as to avoid the width of the first sub-sub main junction region 121 or the second sub-sub main junction region 122 being too small, resulting in a smaller widening effect on the depletion region at the edge of the insulated gate bipolar transistor region 110, thereby ensuring the widening effect of the first sub-sub main junction region 121 and the second sub-sub main junction region 122 on the depletion region, and effectively avoiding the occurrence of local electric field concentration or excessive local electric field strength in the transition region 120, which can more reliably avoid the failure and burning of the transistor module 100, improve the voltage resistance of the transistor module 100, and improve the reliability of the transistor module 100.

[0080] It should be noted that the secondary main junction region 12 is arranged in a surrounding manner in the horizontal direction, and the width of the first sub-sub-main junction region 121 or the width of the second sub-sub-main junction region 122 or the width of the secondary main junction region 12 is in the horizontal direction and perpendicular to the surrounding direction of the secondary main junction region 12.

[0081] Combination Figure 2As shown, the transistor module 100 may further include a base region 17 of a second conductivity type, the base region 17 is arranged on a side of the drift layer 11 facing the first main surface 101, and a side of the base region 17 away from the drift layer 11 constitutes a part of the first main surface 101, there are multiple base regions 17, the insulated gate bipolar transistor region 110, the transition region 120 and the fast recovery diode region 130 are all provided with the base region 17, the depth of the base region 17 in the first direction is H1, the depth of the secondary main junction region 12 in the first direction is H2, the thickness of the transistor module 100 in the first direction is H3, H1≤H2≤0.5H3.

[0082] Specifically, by setting the depth of the secondary main junction region 12 in the first direction to be no less than the depth of the base region 17 in the first direction, the secondary main junction region 12 can play the role of widening the depletion region, ensuring that the secondary main junction region 12 can further expand the depletion region and reduce the peak electric field strength, thereby improving the voltage resistance of the transition region 120 and even the transistor module 100.

[0083] Furthermore, by setting the depth of the secondary main junction region 12 in the first direction to be no greater than half of the thickness of the transistor module 100 in the first direction, not only can the main junction region be separated from the super junction region of the transistor module 100 to ensure the normal operation of the transistor module 100, but also it can avoid the secondary main junction region 12 being too deep in the first direction, causing the depletion region to expand too wide and affect the insulated gate bipolar transistor region 110 and the fast recovery diode region 130, or causing the electric field in the transition region 120 to change too quickly and cause the local field strength to be too high, resulting in failure of the transistor module 100.

[0084] In this way, the depth design of the primary and secondary junction regions in the first direction can be optimized and the depth of the primary and secondary junction regions in the first direction can be set within a reasonable range, thereby improving the voltage resistance of the transition region 120 and even the entire transistor module 100 while ensuring the normal operation of the transistor module 100.

[0085] Combination Figure 3-10 As shown, the method for manufacturing the transistor module 100 according to the present invention can be applied to the above-mentioned transistor module 100 .

[0086] The manufacturing method of the transistor module 100 may mainly include the following steps: preparing a substrate 10, and setting a drift layer 11 of a first conductivity type in the substrate 10; simultaneously implanting doping ions of a second conductivity type in the terminal region and the transition region 120 of the insulated gate bipolar transistor region 110, so as to simultaneously form a main junction region in the terminal region of the insulated gate bipolar transistor region 110 and a secondary main junction region 12 in the transition region 120; etching a first trench 13 in the transition region 120, wherein the depth of the first trench 13 extends from the first main surface 101 to the secondary main junction region 12 in a first direction and does not extend out of the secondary main junction region 12; Doping ions of the second conductivity type are injected into the secondary main junction region 12 to form a base region 17; an insulating layer 20 is arranged on the first main surface 101; a first contact hole 21 is arranged in a portion of the insulating layer 20 corresponding to the transition region 120, and a projection of the first contact hole 21 in the first direction is staggered from a projection of the first trench 13 in the first direction, and doping ions of the second conductivity type are injected into the base region 17 to form a semiconductor region 14; an emitter metal layer 30 is arranged on the insulating layer 20, and a connecting protrusion 31 is arranged on the emitter metal layer 30, and the connecting protrusion 31 passes through the first contact hole 21 and contacts the semiconductor region 14.

[0087] Specifically, when manufacturing the transistor module 100, a substrate 10 can be provided first, and a drift layer 11 of the first conductivity type can be set in the substrate 10. Then, after taking certain protective measures, the second conductivity type of doping ions are simultaneously implanted in the terminal area of ​​the insulated gate bipolar transistor area 110 and the transition area 120 to simultaneously form a main junction area in the terminal area of ​​the insulated gate bipolar transistor area 110 and a secondary main junction area 12 in the transition area 120. Then, a first trench 13, a second trench 15 and a third trench 16 are etched in the transition area 120 so that the depth of the first trench 13 extends from the first main surface 101 to the secondary main junction area 12 in the first direction and does not extend out of the secondary main junction area 12, and processes such as rounding and oxide layer growth are completed.

[0088] The lateral expansion effect generated when the secondary main junction region 12 is implanted can be utilized to make the secondary main junction region 12 located in the transition region 120. In this way, the process of the secondary main junction region 12 can be made compatible with the main junction region of the terminal region of the insulated gate bipolar transistor region 110, without adding additional process steps, thus saving process steps and time costs.

[0089] Furthermore, doping ions of the second conductivity type are injected into the secondary main junction region 12 to form a base region 17, and then an insulating layer 20 is arranged on the first main surface 101, and then a first contact hole 21 and a second contact hole 22 are arranged on the insulating layer 20, the projection of the first contact hole 21 in the first direction is staggered with the projection of the first groove 13 in the first direction, and doping ions of the second conductivity type are injected into the base region 17 to form a semiconductor region 14, and then an emitter metal layer 30 is deposited on the insulating layer 20, and the emitter metal layer 30 is formed with a connecting protrusion 31 at the first contact hole 21, and the connecting protrusion 31 penetrates the first contact hole 21 and contacts the semiconductor region 14.

[0090] Among them, the formation process corresponding to the first contact hole 21 can be made compatible with the formation process of the second contact hole 22, and the formation process corresponding to the semiconductor region 14 can be made compatible with the formation process of the voltage-resistant structure in the terminal area, thereby eliminating the need for additional process steps and saving process steps and time costs.

[0091] Combination Figure 3 as well as Figure 11-13 As shown, after the steps of arranging an emitter metal layer 30 on the insulating layer 20, and a connecting protrusion 31 on the emitter metal layer 30, and the connecting protrusion 31 passes through the first contact hole 21 and contacts the semiconductor region 14, the manufacturing method of the transistor module 100 may further include: sequentially injecting a first conductive type field stop layer 18 and a second conductive type collector layer 19 on the side of the drift layer 11 facing the second main surface 102; injecting a first conductive type cathode layer 111 into the collector; and depositing a collector metal layer 40 on the second main surface 102.

[0092] In this way, the manufacturing of the transistor module 100 can be completed, and the voltage resistance of the transistor module 100 is better. In addition, the manufacturing of the transistor module 100 can also be compatible with the existing process without adding additional process steps, which can save process steps and time costs.

[0093] It should be noted that other structures and operations of the transistor module 100 according to the embodiment of the present invention are known to those skilled in the art and will not be described in detail here.

[0094] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0095] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0096] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A transistor module, characterized in that: include: A substrate (10), the substrate (10) having a first main surface (101) and a second main surface (102) on the opposite side of the first main surface (101), the first main surface (101) and the second main surface (102) being arranged at intervals in a first direction; A drift layer (11) of a first conductive type, the drift layer (11) being arranged between the first main surface (101) and the second main surface (102), the transistor module (100) comprising an insulated gate bipolar transistor region (110), a transition region (120) and a fast recovery diode region (130), the insulated gate bipolar transistor region (110) being arranged circumferentially outside the fast recovery diode region (130), the transition region (120) being arranged circumferentially outside the fast recovery diode region (130) and being located between the insulated gate bipolar transistor region (110) and the fast recovery diode region (130); a secondary main junction region (12) of a second conductivity type, the secondary main junction region (12) being arranged in the transition region (120), the secondary main junction region (12) being arranged around the outside of the fast recovery diode region (130), the secondary main junction region (12) being located on a side of the drift layer (11) facing the first main surface (101), and a side of the secondary main junction region (12) facing away from the drift layer (11) constituting at least a portion of the first main surface (101); a first groove (13), wherein the first groove (13) is arranged in the transition region (120) and is in plurality, the lengths of the plurality of first grooves (13) extending in the second direction, the plurality of first grooves (13) being arranged at intervals in the third direction, the depths of at least some of the first grooves (13) extending in the first direction from the first main surface (101) to the secondary main junction region (12) and not protruding out of the secondary main junction region (12), and the first direction, the second direction and the third direction being perpendicular to each other; an insulating layer (20), the insulating layer (20) being arranged on the first main surface (101), a first contact hole (21) being arranged on a portion of the insulating layer (20) corresponding to the transition region (120), a projection of the first contact hole (21) in the first direction being offset from a projection of the first groove (13) in the first direction; a semiconductor region (14) of a second conductivity type, the semiconductor region (14) being arranged in the secondary main junction region (12), the side of the semiconductor region (14) facing away from the drift layer (11) constituting at least a portion of the first main surface (101), and the semiconductor region (14) corresponding to the first contact hole (21); An emitter metal layer (30), the emitter metal layer (30) being arranged on a side of the insulating layer (20) away from the first main surface (101), the emitter metal layer (30) being provided with a connection protrusion (31), the connection protrusion (31) penetrating the first contact hole (21) and being in contact and electrically connected with the semiconductor region (14).

2. The transistor module according to claim 1, characterized in that: There are a plurality of the first contact holes (21), and a plurality of the semiconductor regions (14), and the plurality of the first contact holes (21) and the plurality of the semiconductor regions (14) are arranged in a one-to-one correspondence.

3. The transistor module according to claim 2, characterized in that: The projection of the secondary main junction region (12) in the first direction covers the projections of the plurality of first contact holes (21) in the first direction.

4. The transistor module according to claim 2, characterized in that: The projection of the secondary main junction region (12) in the first direction covers a portion of the projections of the plurality of first contact holes (21) in the first direction, and another portion of the projections of the plurality of first contact holes (21) in the first direction is staggered with the projection of the secondary main junction region (12) in the first direction.

5. The transistor module according to claim 2, characterized in that: A plurality of the first contact holes (21) extend in the second direction and are arranged at intervals in the third direction; and / or A plurality of the first contact holes (21) arranged at intervals in the second direction form a contact hole group (215), and the plurality of contact hole groups (215) are arranged at intervals in the third direction.

6. The transistor module according to claim 2, characterized in that: The first contact hole (21) is in the shape of an elongated strip; and / or the first contact hole (21) is in the shape of a rectangle.

7. The transistor module according to claim 2, characterized in that: A first contact hole (21) is provided between at least two adjacent first grooves (13) among the plurality of first grooves (13); and / or A plurality of first contact holes (21) are arranged between at least two adjacent first trenches (13) among the plurality of first trenches (13).

8. The transistor module according to any one of claims 2, characterized in that: In a top view, the total area of ​​the first contact hole (21) is S1, the total area of ​​the transition region (120) is S2, and S1 and S2 satisfy the relationship: 0≤S1 / S2≤50%.

9. The transistor module according to claim 1, characterized in that: The ion doping concentration of the semiconductor region (14) is greater than the ion doping concentration of the secondary main junction region (12).

10. The transistor module according to claim 1, characterized in that It also includes a second trench (15) and a third trench (16), wherein the second trench (15) is arranged in the fast recovery diode region (130) and is in plurality, the plurality of second trenches (15) are arranged at intervals in the third direction, the depth of the second trench (15) extends from the first main surface (101) toward the drift layer (11), the length of the second trench (15) extends in the second direction, and the second trenches (15) on both sides of the plurality of second trenches (15) in the third direction are first boundary trenches (151); The third trenches (16) are arranged in the insulated gate bipolar transistor region (110) and are in plurality. The plurality of third trenches (16) are arranged at intervals in the third direction. The depth of the third trenches (16) extends from the first main surface (101) toward the drift layer (11). The length of the third trenches (16) extends in the second direction. The plurality of third trenches (16) include main trenches (161) and spacing trenches (162). Both sides of the plurality of second trenches (15) in the third direction are provided with There are a plurality of main grooves (161) arranged at intervals in a third direction, the spacing grooves (162) include a first spacing groove (1621) and a second spacing groove (162), the first spacing groove (1621) and the second spacing groove (162) are respectively arranged at intervals on both sides of the plurality of second grooves (15) in the second direction, and one of the plurality of main grooves (161) on one side of the plurality of second grooves (15) in the third direction adjacent to the plurality of second grooves (15) is a second boundary groove (1611); The sub-main junction region (12) comprises two first sub-sub-main junction regions (121) and two second sub-sub-main junction regions (122), the two first sub-sub-main junction regions (121) are respectively located on both sides of the plurality of second grooves (15) in the third direction, the two second sub-sub-main junction regions (122) are respectively located on both sides of the plurality of second grooves (15) in the second direction and are respectively connected to the two first sub-sub-main junction regions (121), the projection of the first sub-sub-main junction region (121) in the first direction is the first projection, the projections of the adjacent first boundary grooves (151) and the second boundary grooves (1611) in the first direction are the second projection and the third projection respectively, the first projection is located between the second projection and the third projection in the third direction, and both sides of the first projection in the third direction do not exceed the second projection and the third projection.

11. The transistor module according to claim 10, characterized in that: One side of the first projection in the third direction coincides with a center line extending in the second direction of the second projection, and the other side of the first projection in the third direction coincides with a center line extending in the second direction of the third projection.

12. The transistor module according to claim 10, characterized in that: The widths of the first sub-sub main junction region (121) and the second sub-sub main junction region (122) are equal and both are D, and D satisfies the relationship: D≥4μm.

13. The transistor module according to claim 1, characterized in that: It also comprises a base region (17) of a second conductivity type, the base region (17) being arranged on a side of the drift layer (11) facing the first main surface (101), and a side of the base region (17) facing away from the drift layer (11) constituting a part of the first main surface (101), the base region (17) being multiple, the insulated gate bipolar transistor region (110), the transition region (120) and the fast recovery diode region (130) all being provided with the base region (17), the depth of the base region (17) in the first direction being H1, the depth of the secondary main junction region (12) in the first direction being H2, and the thickness of the transistor module (100) in the first direction being H3, H1≤H2≤0.5H3.

14. A method for manufacturing a transistor module, applicable to the transistor module according to any one of claims 1 to 13, characterized in that , including the following steps: A substrate (10) is prepared, and a drift layer (11) of a first conductivity type is disposed in the substrate (10); Simultaneously implanting doping ions of a second conductivity type into the terminal region and the transition region (120) of the insulated gate bipolar transistor region (110) to simultaneously form a main junction region in the terminal region of the insulated gate bipolar transistor region (110) and a secondary main junction region (12) in the transition region (120); Etching a first trench (13) in the transition region (120), wherein the depth of the first trench (13) extends from the first main surface (101) to the secondary main junction region (12) in a first direction and does not extend beyond the secondary main junction region (12); Implanting doping ions of a second conductivity type into the secondary main junction region (12) to form a base region (17); Providing an insulating layer (20) on the first main surface (101); A first contact hole (21) is provided in a portion of the insulating layer (20) corresponding to the transition region (120), wherein a projection of the first contact hole (21) in a first direction is staggered from a projection of the first trench (13) in the first direction, and doping ions of a second conductivity type are implanted in the base region (17) to form a semiconductor region (14); An emitter metal layer (30) is arranged on the insulating layer (20), a connection protrusion (31) is arranged on the emitter metal layer (30), and the connection protrusion (31) penetrates the first contact hole (21) and contacts the semiconductor region (14).

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