Linkage circuit, clock signal duty cycle adjustment method and display panel

Abstract

The present application proposes a linkage circuit, a method for adjusting the duty cycle of a clock signal, and a display panel, which belong to the field of electronic circuit technology. The linkage circuit includes a first conversion circuit and a second conversion circuit, the first conversion circuit is used to convert the first clock square wave signal into a triangular wave signal, and the second conversion circuit is used to convert the triangular wave signal into a second clock square wave signal. The moment corresponding to the falling voltage threshold in the triangular wave signal corresponds to the moment corresponding to the rising edge of the second clock square wave signal, and the moment corresponding to the rising voltage threshold in the triangular wave signal corresponds to the moment corresponding to the falling edge of the second clock square wave signal. The rising voltage threshold is positively correlated with the difference between the turn-on voltage and the turn-off voltage, and the falling voltage threshold is positively correlated with the turn-on voltage. The linkage circuit can realize the linkage between the VGH voltage, the VGL voltage and the CLK Duty, so that the CLK Duty can be adjusted accordingly by adjusting the VGH voltage or the VGL voltage, which can realize the automated operation of the production line and improve the improvement efficiency.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a linkage circuit, a method for adjusting a clock signal duty cycle, and a display panel. Background Art

[0002] Due to manufacturing fluctuations during the actual display panel production process, defective products with display issues such as crosstalk and mura (uneven display) may be produced. These defective products can generally be improved by adjusting the VGH voltage (the turn-on voltage of the thin-film transistor), the VGL voltage (the turn-off voltage of the thin-film transistor), and the CLK duty cycle (the clock signal duty cycle).

[0003] However, since the VGH voltage and VGL voltage are controlled by the PMIC (power management chip) and the CLK Duty is controlled by the Tcon (timing controller), the two cannot be linked, and the automated operation of the production line cannot be achieved, requiring a lot of manpower and material resources for rework operations. Summary of the Invention

[0004] The main purpose of the embodiments of the present application is to propose a linkage circuit, a method for adjusting the clock signal duty cycle, and a display panel. The purpose is to achieve linkage between the VGH voltage, VGL voltage, and CLK Duty through the design of the linkage circuit, so that the CLK Duty can be adjusted accordingly by adjusting the VGH voltage or the VGL voltage, thereby realizing automated operation of the production line and improving improvement efficiency.

[0005] To achieve the above objectives, a first aspect of an embodiment of the present application provides a linkage circuit, comprising a first conversion circuit and a second conversion circuit; a first end of the first conversion circuit is used to receive a first clock square wave signal output by a gate drive circuit, a second end of the first conversion circuit is connected to a first end of the second conversion circuit, a second end and a third end of the second conversion circuit are both used to receive a turn-on voltage for turning on a thin film transistor, a fourth end of the second conversion circuit is used to receive a turn-off voltage for turning off the thin film transistor, and a fifth end of the second conversion circuit is connected to a corresponding scan line as a voltage output end;

[0006] The first conversion circuit is used to convert the first clock square wave signal into a triangle wave signal;

[0007] The second conversion circuit is used to convert the triangular wave signal into a second clock square wave signal, wherein the moment corresponding to the falling voltage threshold in the triangular wave signal corresponds to the moment corresponding to the rising edge of the second clock square wave signal, and the moment corresponding to the rising voltage threshold in the triangular wave signal corresponds to the moment corresponding to the falling edge of the second clock square wave signal, the rising voltage threshold is positively correlated with the difference between the turn-on voltage and the turn-off voltage, and the falling voltage threshold is positively correlated with the turn-on voltage.

[0008] In one embodiment of the present application, the first conversion circuit includes an integration circuit.

[0009] In one embodiment of the present application, the first conversion circuit includes an operational amplifier and an RC circuit; the RC circuit includes a first resistor and a first capacitor;

[0010] The first end of the first resistor is used to connect to the first clock square wave signal output by the gate drive circuit, the second end of the first resistor is connected to the negative input end of the operational amplifier, the second end of the second resistor is also connected to the first end of the first capacitor, the second end of the first capacitor is connected to the output end of the operational amplifier, the positive input end of the operational amplifier is grounded, and the output end of the operational amplifier is connected to the first end of the second conversion circuit.

[0011] In one embodiment of the present application, the second conversion circuit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor;

[0012] The gate of the first NMOS transistor is connected to the second end of the first conversion circuit, the source of the first NMOS transistor is used to access the shutdown voltage, and the drain of the first NMOS transistor is connected to the source of the second NMOS transistor and the source of the second NMOS transistor;

[0013] The gate of the second NMOS transistor is connected to the second end of the first conversion circuit, and the drain of the second NMOS transistor is connected to the voltage output end;

[0014] The gate of the third NMOS transistor is connected to the voltage output terminal, and the drain of the third NMOS transistor is used to access the turn-on voltage;

[0015] The gate of the first PMOS transistor is connected to the second end of the first conversion circuit, the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor and then connected to the voltage output end, and the source of the first PMOS transistor is connected to the drain of the second PMOS transistor and the source of the third PMOS transistor;

[0016] The gate of the second PMOS transistor is connected to the second end of the first conversion circuit, and the source of the second PMOS transistor is used to access the turn-on voltage;

[0017] The drain of the third PMOS transistor is grounded, and the gate of the third PMOS transistor is connected to the gate of the third NMOS transistor and then connected to the voltage output end.

[0018] In one embodiment of the present application, the second conversion circuit further includes a second resistor and a second capacitor;

[0019] A first end of the second resistor is connected to the drain of the third PMOS transistor, and a second end of the second resistor is grounded;

[0020] A first end of the second capacitor is connected to the voltage output end, and a second end of the second capacitor is grounded.

[0021] To achieve the above-mentioned object, a second aspect of an embodiment of the present application provides a method for adjusting the duty cycle of a clock signal, the method comprising:

[0022] Converting the first clock square wave signal output by the gate driving circuit into a triangular wave signal, wherein the triangular wave signal includes a rising voltage threshold and a falling voltage threshold;

[0023] Converting the triangular wave signal into a second clock square wave signal, wherein a falling voltage threshold in the triangular wave signal corresponds to a rising edge of the second clock square wave signal, and a rising voltage threshold in the triangular wave signal corresponds to a falling edge of the second clock square wave signal, the rising voltage threshold is positively correlated with a difference between a turn-on voltage of a turn-on thin film transistor and a turn-off voltage of a turn-off thin film transistor, and the falling voltage threshold is positively correlated with the turn-on voltage;

[0024] The turn-on voltage or the turn-off voltage is adjusted to correspondingly adjust the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is adjusted accordingly.

[0025] In one embodiment of the present application, adjusting the turn-on voltage or the turn-off voltage to correspondingly adjust the rising voltage threshold and the falling voltage threshold in the triangular wave signal so that the duty cycle of the second clock square wave signal is adjusted accordingly includes:

[0026] Keeping the turn-off voltage unchanged, adjusting the turn-on voltage, and accordingly adjusting the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is adjusted accordingly;

[0027] Alternatively, the turn-on voltage is kept unchanged, and the turn-off voltage is adjusted to correspondingly adjust the rising voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is adjusted accordingly.

[0028] In one embodiment of the present application, adjusting the turn-on voltage or the turn-off voltage to correspondingly adjust the rising voltage threshold and the falling voltage threshold in the triangular wave signal so that the duty cycle of the second clock square wave signal is adjusted accordingly includes:

[0029] Keeping the turn-off voltage unchanged, reducing the turn-on voltage, so as to correspondingly reduce the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is correspondingly reduced;

[0030] Keeping the turn-off voltage unchanged, increasing the turn-on voltage, so as to correspondingly increase the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is correspondingly increased;

[0031] or;

[0032] Keeping the turn-on voltage unchanged and increasing the turn-off voltage, so as to correspondingly reduce the rising voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is correspondingly reduced;

[0033] The turn-on voltage is kept unchanged, and the turn-off voltage is reduced to correspondingly increase the rising voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is correspondingly increased.

[0034] To achieve the above-mentioned objective, a third aspect of the embodiments of the present application provides a display panel, comprising:

[0035] Gate drive circuit;

[0036] The linkage circuit described in the first aspect of the embodiment of the present application is connected to the output end of the gate drive circuit.

[0037] To achieve the above-mentioned purpose, the fourth aspect of an embodiment of the present application proposes an electronic device, which includes a memory and a processor, the memory stores a computer program, and the processor implements the method described in the second aspect of the embodiment of the present application when executing the computer program.

[0038] In the technical solution provided in the embodiment of the present application, the linkage circuit includes a first conversion circuit and a second conversion circuit, wherein the first conversion circuit is used to receive the first clock square wave signal output by the gate drive circuit and convert the first clock square wave signal into a triangular wave signal. The second conversion circuit is connected to the first conversion circuit and is used to convert the triangular wave signal into a second clock square wave signal, wherein the time corresponding to the falling voltage threshold in the triangular wave signal corresponds to the time corresponding to the rising edge of the second clock square wave signal, the time corresponding to the rising voltage threshold in the triangular wave signal corresponds to the time corresponding to the falling edge of the second clock square wave signal, the rising voltage threshold is positively correlated with the difference between the turn-on voltage and the turn-off voltage, and the falling voltage threshold is positively correlated with the turn-on voltage. Through the designed linkage circuit, the linkage between the VGH voltage, the VGL voltage and the CLK Duty can be achieved, so that the CLK Duty can be adjusted accordingly by adjusting the VGH voltage or the VGL voltage, which can realize the automated operation of the production line and improve the improvement efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a structural block diagram of the linkage circuit provided in an embodiment of the present application;

[0040] Figure 2 1 is a waveform conversion diagram of a first clock square wave signal and a triangular wave signal provided in an embodiment of the present application;

[0041] Figure 3 The embodiment of the present application provides a waveform conversion diagram of a triangular wave signal and a second clock square wave signal;

[0042] Figure 4 is a circuit diagram of a linkage circuit provided in an embodiment of the present application;

[0043] Figure 5 is a flow chart of a method for adjusting the duty cycle of a clock signal provided in an embodiment of the present application;

[0044] Figure 6 This is a flowchart of the steps of adjusting the turn-on voltage or the turn-off voltage to adjust the rising voltage threshold and the falling voltage threshold in the triangular wave signal accordingly, so that the duty cycle of the second clock square wave signal is adjusted accordingly, according to an embodiment of the present application;

[0045] Figure 7 This is another flowchart of steps for adjusting the turn-on voltage or the turn-off voltage to correspondingly adjust the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is adjusted accordingly, provided by an embodiment of the present application;

[0046] Figure 8 is a structural block diagram of a display panel provided in an embodiment of the present application;

[0047] Figure 9 It is a structural diagram of an electronic device provided in an embodiment of the present application.

[0048] Description of reference numerals:

[0049] Linkage circuit-10; first conversion circuit-100; second conversion circuit-200; gate drive circuit-20; processor-901; memory-902; input / output interface-903; communication interface-904; bus-905. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0051] It should be noted that although the device schematics illustrate functional module divisions and the flowcharts illustrate logical sequences, in certain circumstances, the steps illustrated or described may be performed in a sequence that differs from the module divisions in the device or the sequence in the flowcharts. The terms "first," "second," and the like in the specification, claims, and drawings are used to distinguish similar objects and are not necessarily used to describe a specific sequence or precedence.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0053] Due to manufacturing fluctuations during the actual display panel production process, variations in film position within a single display panel can result in a single code not covering all film positions, resulting in a high rate of substandard products and significantly impacting product yield. Defects include H-crosstalk (H-crosstalk), H-mura (horizontal display unevenness), and V-mura (vertical display unevenness). A common approach to address this problem is to adjust the VGH voltage (threshold voltage for turning on the thin-film transistors) and CLK duty (clock signal duty cycle). For example, the typical settings are: VGH = 30V, VGL = -6, CLK duty = 47%. However, this setting may not cover all film positions. For example, a 27-inch FHD (Full High Definition) display exhibited a 10% H-mura defect at 100Hz. By adjusting the settings to: VGH = 24V, CLK duty = 45%, or VGL = -8, CLK duty = 49%, the product could be successfully upgraded and shipped.

[0054] However, since the VGH voltage and VGL voltage are controlled by the PMIC (power management chip) and the CLK Duty is controlled by the Tcon (timing controller), the two cannot be linked, and the automated operation of the production line cannot be achieved, requiring a large amount of manpower and material resources for rework operations.

[0055] Based on this, the present application proposes a linkage circuit, which aims to achieve linkage between VGH voltage and CLK Duty through the design of the linkage circuit, so that CLK Duty can be adjusted accordingly by adjusting the VGH voltage, thereby realizing automated operation of the production line and improving improvement efficiency.

[0056] Reference Figure 1 , Figure 1 This is a structural block diagram of the linkage circuit provided by the embodiment of the present application. Figure 1 As shown, the linkage circuit 10 includes a first conversion circuit 100 and a second conversion circuit 200; the first end of the first conversion circuit 100 is used to receive the first clock square wave signal output by the gate drive circuit, the second end of the first conversion circuit 100 is connected to the first end of the second conversion circuit 200, the second end and the third end of the second conversion circuit 200 are both used to receive the turn-on voltage (VGH) for turning on the thin film transistor, the fourth end of the second conversion circuit 200 is used to receive the turn-off voltage (VGL) for turning off the thin film transistor, and the fifth end of the second conversion circuit 200 is connected to the corresponding scan line as a voltage output end (Vout). Wherein:

[0057] The first conversion circuit 100 is used to convert the first clock square wave signal into a triangular wave signal; the second conversion circuit 200 is used to convert the triangular wave signal into a second clock square wave signal, wherein the moment corresponding to the falling voltage threshold in the triangular wave signal corresponds to the moment corresponding to the rising edge of the second clock square wave signal, the moment corresponding to the rising voltage threshold in the triangular wave signal corresponds to the moment corresponding to the falling edge of the second clock square wave signal, the rising voltage threshold is positively correlated with the difference between the turn-on voltage and the turn-off voltage, and the falling voltage threshold is positively correlated with the turn-on voltage.

[0058] Reference Figure 2 , Figure 2 : is a waveform conversion diagram of the first clock square wave signal and the triangle wave signal provided in the embodiment of the present application. Figure 2 As shown, the first clock square wave signal is the GDL signal (gate drive signal) output by the gate drive circuit. The first conversion circuit 100 is used to convert the first clock square wave signal into a triangular wave signal. The falling edge of the first clock square wave signal corresponds to the peak of the triangular wave, and the rising and falling edge of the first clock square wave signal corresponds to the trough of the triangular wave.

[0059] In one embodiment of the present application, the first conversion circuit 100 may use an integration circuit, such as an inverting integration circuit, an RC integration circuit, etc. That is, the first clock square wave signal can be converted into a triangle wave signal through the integration circuit.

[0060] Reference Figure 3 , Figure 3 Schematic diagram of waveform conversion between the triangle wave signal and the second clock square wave signal provided by the embodiment of the present application. Figure 3 As shown, the second conversion circuit 200 can convert the triangular wave signal converted by the first conversion circuit 100 into a second clock square wave signal. 下降 ) corresponds to the moment corresponding to the rising edge of the second clock square wave signal, and the rising voltage threshold (V 上升 ) corresponds to the time corresponding to the falling edge of the second clock square wave signal. The rising voltage threshold (V 上升 ) is positively correlated with the difference between the turn-on voltage (VGH) and the turn-off voltage (VGL). The falling voltage threshold (V 下降 ) is positively correlated with the turn-on voltage (VGH). That is, by adjusting the turn-on voltage (VGH) or the turn-off voltage (VGL), the rising voltage threshold (V 上升 ) and the falling voltage threshold (V 下降 Specifically, if the turn-on voltage (VGH) remains unchanged, the voltage threshold (V 下降 ) remains unchanged. At this time, if the turn-off voltage (VGL) is increased, the rising voltage threshold (V 上升 ) decreases, that is, the turn-off voltage (VGL) and the rising voltage threshold (V 上升 ) is negatively correlated. Keeping the turn-off voltage (VGL) unchanged, the rising voltage threshold (V 上升 ) and the falling voltage threshold (V 下降 ) are positively correlated.

[0061] In the embodiment of the present application, by connecting the turn-on voltage (VGH) and the turn-off voltage (VGL) to the second conversion circuit 200, the designed linkage circuit 10 can adjust the rising voltage threshold (V 上升 ) and the falling voltage threshold (V 下降 ), and due to the falling voltage threshold (V 下降 ) corresponds to the moment corresponding to the rising edge of the second clock square wave signal, and the rising voltage threshold (V 上升 ) corresponds to the moment corresponding to the falling edge of the second clock square wave signal, that is, the falling voltage threshold (V下降 ) and rising voltage threshold (V 上升 ) determines the clock signal duty cycle (CLK Duty) of the second clock square wave signal, thereby adjusting the rising voltage threshold (V 上升 ) and the falling voltage threshold (V 下降 ), the clock signal duty cycle (CLK Duty) of the second clock square wave signal will also change accordingly. That is, after adjusting the turn-on voltage (VGH) or the turn-off voltage (VGL), the clock signal duty cycle (CLK Duty) will also change accordingly. 下降 ) and the clock signal duty cycle (CLK Duty), without the need to separately control the turn-on voltage (VGH), the falling voltage threshold (V 下降 ) and the clock signal duty cycle (CLK Duty) are adjusted separately to improve the regulation efficiency, thereby improving the improvement efficiency.

[0062] Specifically, keeping the turn-off voltage (VGL) unchanged and increasing the turn-on voltage (VGH) can correspondingly increase the rising voltage threshold (V 上升 ) and the falling voltage threshold (V 下降 ), thereby increasing the clock signal duty cycle (CLK Duty) of the second clock square wave signal accordingly. That is, keeping the turn-off voltage (VGL) unchanged and increasing the turn-on voltage (VGH) can correspondingly increase the clock signal duty cycle (CLK Duty). Keeping the turn-off voltage (VGL) unchanged and reducing the turn-on voltage (VGH) can correspondingly reduce the rising voltage threshold (V 上升 ) and the falling voltage threshold (V 下降 ), thereby reducing the clock signal duty cycle (CLK Duty) of the second clock square wave signal accordingly, that is, keeping the turn-off voltage (VGL) unchanged, reducing the turn-on voltage (VGH) can reduce the clock signal duty cycle (CLK Duty) accordingly. Keeping the turn-on voltage (VGH) unchanged, the voltage threshold (V 下降 ) remains unchanged, reducing the turn-off voltage can correspondingly increase the rising voltage threshold (V 上升 ), thereby increasing the clock signal duty cycle (CLK Duty) of the second clock square wave signal accordingly. Keeping the turn-on voltage (VGH) unchanged, the voltage threshold (V 下降 ) remains unchanged, increasing the turn-off voltage can correspondingly reduce the rising voltage threshold (V 上升 ), thereby reducing the clock signal duty cycle (CLK Duty) of the second clock square wave signal accordingly.

[0063] Reference Figure 4 , Figure 4: is a circuit diagram of the linkage circuit provided in the embodiment of the present application. Figure 4 As shown, the first conversion circuit 100 includes an operational amplifier and an RC circuit. The RC circuit includes a first resistor R1 and a first capacitor C1. The first end of the first resistor R1 is used to receive the first clock square wave signal output by the gate drive circuit, the second end of the first resistor R1 is connected to the negative input terminal of the operational amplifier, the second end of the first resistor R1 is also connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to the output terminal of the operational amplifier, the positive input terminal of the operational amplifier is grounded, and the output terminal of the operational amplifier is connected to the first end of the second conversion circuit 200.

[0064] The second conversion circuit 200 includes: a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a first PMOS transistor PM1, a second PMOS transistor PM2, and a third PMOS transistor PM3. The gate of the first NMOS transistor NM1 is connected to the second terminal of the first conversion circuit 100, the source of the first NMOS transistor NM1 is connected to the shutdown voltage (VGL), and the drain of the first NMOS transistor NM1 is connected to the source of the second NMOS transistor NM2 and the source of the second NMOS transistor NM2. The gate of the second NMOS transistor NM2 is connected to the second terminal of the first conversion circuit 100, and the drain of the second NMOS transistor NM2 is connected to the voltage output terminal (Vout). The gate of the third NMOS transistor NM3 is connected to the voltage output terminal (Vout), and the drain of the third NMOS transistor NM3 is connected to the start-up voltage (VGH). The gate of the first PMOS transistor PM1 is connected to the second terminal of the first conversion circuit 100. The drain of the first PMOS transistor PM1 is connected to the drain of the second NMOS transistor NM2 and then to the voltage output terminal (Vout). The source of the first PMOS transistor PM1 is connected to the drain of the second PMOS transistor PM2 and the source of the third PMOS transistor PM3. The gate of the second PMOS transistor PM2 is connected to the second terminal of the first conversion circuit 100, and the source of the second PMOS transistor PM2 is connected to the turn-on voltage (VGH). The drain of the third PMOS transistor PM3 is grounded, and the gate of the third PMOS transistor PM3 is connected to the gate of the third NMOS transistor NM3 and then to the voltage output terminal (Vout).

[0065] Continue to refer to Figure 4 The second conversion circuit 200 further includes a second resistor R2 and a second capacitor C2. A first end of the second resistor R2 is connected to the drain of the third PMOS transistor PM3, and a second end of the second resistor R2 is grounded; a first end of the second capacitor C2 is connected to the voltage output terminal (Vout), and a second end of the second capacitor C2 is grounded.

[0066] In the present application, refer to Figure 4Initially, the positive input of the operational amplifier is grounded, resulting in no output. The potential at point C is at ground (i.e., 0). When the voltage of the first clock square wave signal is positive, current flows through the first resistor R1. Since the positive input of the operational amplifier is grounded, current cannot flow into it. Therefore, the current charges the first capacitor C1, causing the potential at point C to gradually rise.

[0067] When the voltage of the first clock square wave signal is negative, the current will reverse, the charge stored in the first capacitor C1 will be slowly released, and the potential at point C will slowly drop. And the rate at which the potential at point C rises and falls is determined by the delay generated by RC (resistance and capacitance). Finally, the first clock square wave signal passes Figure 4 After the first conversion circuit 100 shown, it can be converted into Figure 2 The triangle wave waveform shown in Figure 1 is shown in Figure 2. That is, the waveform of the potential change at point C is as follows: Figure 2 The triangle wave waveform is shown.

[0068] The triangular wave signal corresponding to the potential at point C serves as the input to the second conversion circuit 200, which is configured to convert the triangular wave signal into a second clock square wave signal. Specifically, when the input is at a low level, the first PMOS transistor PM1, the second PMOS transistor PM2, and the third NMOS transistor NM3 are turned on, while the first NMOS transistor NM1, the second NMOS transistor NM2, and the third PMOS transistor PM3 are turned off, and the voltage output terminal Vout outputs a high level. When the input is at a high level, because the second conversion circuit 200 provides a path from the voltage output terminal to ground, the first NMOS transistor NM1, the second NMOS transistor NM2, and the third PMOS transistor PM3 are turned on, while the first PMOS transistor PM1, the second PMOS transistor PM2, and the third NMOS transistor NM3 are turned off, and the voltage output terminal Vout outputs a low level.

[0069] Specifically, under initial conditions, the input of the second conversion circuit 200 is 0, and the voltage output terminal Vout outputs a high level. At this time, the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned off, and the third NMOS transistor NM3 is turned on. Figure 4 As shown, the potential at point C is 0, and when the voltage output terminal Vout outputs a high level, the third NMOS transistor NM3 is turned on, and the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned off. At this time, the voltage at point A is VGH-V th3 When the voltage at point C gradually increases, the gate voltages of the first NMOS transistor NM1 and the second NMOS transistor NM2 will also slowly increase. This is because the source of the first NMOS transistor NM1 is the cutoff voltage VGL (negative voltage), which is lower than the source voltage of the second NMOS transistor NM2 (i.e., lower than the voltage V at point A). A ). Therefore, the first NMOS transistor NM1 will turn on before the second NMOS transistor NM2. When the voltage at point C rises to Vth1 +VGL, the first NMOS transistor NM1 will gradually open, causing the voltage at point A to drop, accelerating the opening of the second NMOS transistor NM2. When the voltage at point C rises to V A +V th2 When the voltage output terminal Vout drops to the turn-off voltage VGL through the first NMOS transistor NM1 and the second NMOS transistor NM2, the third NMOS transistor NM3 will gradually turn off, which will accelerate the potential drop at point A, thereby accelerating the complete conduction of the first NMOS transistor NM1 and the second NMOS transistor NM2. Finally, the forward conduction voltage at point C can be obtained as: V C+ =V A +V th2 At the moment the second NMOS tube NM2 is turned on, the third NMOS tube NM3 and the first NMOS tube NM1 are connected in series, and the currents are equal. A =(R1 / R3+R1)*(VGH-VGL). Therefore, the forward voltage at point C is: V C+ =(R1 / R3+R1)*(VGH-VGL)+V th2 Among them, R1 is the resistance value of the first NMOS tube NM1, R3 is the resistance value of the third NMOS tube NM3, V th2 is the threshold voltage of the second NMOS transistor NM2. When point C is high, the voltage output terminal Vout outputs a low level. At this time, the third PMOS transistor PM3 is turned on, and the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned off. The voltage at point B is V th6 When the voltage at point C gradually decreases, the voltage at point C V C Before the voltage of point B is lower than the threshold voltage of the second PMOS transistor PM2, the voltage at point B is always V th6 When the voltage at point C drops to VGH-V th6 =V th5 When the second PMOS transistor PM2 is turned on, the voltage at point B gradually increases due to the conduction of the second PMOS transistor PM2. Since the source of the first PMOS transistor PM1 is point B, its voltage is lower than the source voltage of the second PMOS transistor PM2 (i.e., VGH). Therefore, the first PMOS transistor PM1 will be turned on later than the second PMOS transistor PM2. The voltage at point B increases, and the voltage at point C decreases. When the voltage at point B V B Subtract the voltage V at point C C Equal to the threshold voltage V of the first PMOS transistor PM1 th4When the voltage at point B increases, the first PMOS transistor PM1 will turn on, causing the voltage output terminal Vout to increase, and the third PMOS transistor PM3 will gradually turn off. The increase in the voltage at point B will accelerate the conduction of the first PMOS transistor PM1. Finally, the negative conduction voltage at point C can be obtained as: V C- =V B +V th4 At the moment when the first PMOS transistor PM1 is turned on, the second PMOS transistor PM2 and the third PMOS transistor PM3 are connected in series. Therefore, the voltage of B is: V B =(R6 / R5+R6)*VGH. Thus, the negative conduction voltage at point C is: V C- =(R6 / R5+R6)*VGH+V th4 Among them, R5 is the resistance value of the second PMOS transistor PM2, R6 is the resistance value of the third PMOS transistor PM3, V th4 is the threshold voltage of the first PMOS transistor PM1.

[0070] As mentioned above, when the voltage at point C gradually increases from 0 to the forward conduction voltage V C+ During this period, the voltage output terminal Vout outputs a continuous high level. When the voltage at point C continues to rise and exceeds the forward conduction voltage V at point C, C+ When the voltage at point C rises to the highest point and gradually drops to a level lower than the negative conduction voltage V at point C, the voltage output terminal Vout starts to become low. C- During this period, the voltage output terminal Vout outputs a low level. When the voltage at point C continues to drop to the lowest point and gradually rises to the forward conduction voltage V at point C, C+ During this period, the voltage output terminal Vout output is continuously high. That is, the forward conduction voltage V C+ is the rising voltage threshold in the triangle wave signal (V 上升 ), the negative conduction voltage V C- is the falling voltage threshold in the triangle wave signal (V 下降 ). At the rising voltage threshold (V 上升 ) to the falling voltage threshold (V 下降 ) period, the corresponding voltage output terminal Vout outputs a low level. At the falling voltage threshold (V 下降 ) to the rising voltage threshold (V 上升 ) period, the corresponding voltage output terminal Vout outputs a high level. Finally, the triangle wave signal corresponding to the potential at point C is generated by Figure 4 After the second conversion circuit 200 is shown, it can be converted into Figure 3 The second clock signal waveform is shown.

[0071] In the present application, refer to Figure 3 , the falling voltage threshold in the triangle wave signal (V下降 ) corresponds to the moment corresponding to the rising edge of the second clock square wave signal, and the rising voltage threshold (V 上升 ) corresponds to the time corresponding to the falling edge of the second clock square wave signal. That is, the falling voltage threshold (V 下降 ) and the rising voltage threshold (V 上升 ) determines the clock signal duty cycle (CLK Duty) of the second clock square wave signal. And according to the formula V C+ =(R1 / R3+R1)*(VGH-VGL)+V th2 , we can see that the rising voltage threshold (V 上升 ) is proportional to the difference between the turn-on voltage (VGH) and the turn-off voltage (VGL). According to the formula V C- =(R6 / R5+R6)*VGH+V th4 , we can see that the falling voltage threshold (V 下降 ) is proportional to the turn-on voltage (VGH). Therefore, in the embodiment of the present application, if the turn-on voltage (VGH) is kept unchanged, the voltage threshold (V 下降 ) remains unchanged. At this time, if the turn-off voltage (VGL) is increased, the rising voltage threshold (V 上升 ) will decrease, the clock signal duty cycle (CLK Duty) of the second clock square wave signal will decrease; if the shutdown voltage (VGL) is reduced, the rising voltage threshold (V 上升 ) will increase, the clock signal duty cycle (CLK Duty) of the second clock square wave signal will increase. Keeping the turn-off voltage (VGL) unchanged, at this time, if the turn-on voltage (VGH) is increased, the rising voltage threshold (V 上升 ) will increase, and the voltage threshold (V 下降 ) will increase, the clock signal duty cycle (CLK Duty) of the second clock square wave signal will increase; if the turn-on voltage (VGH) is reduced, the rising voltage threshold (V 上升 ) will decrease, the falling voltage threshold (V 下降 ) will decrease, and the clock signal duty cycle (CLK Duty) of the second clock square wave signal will decrease.

[0072] Reference Figure 5 , Figure 5 This is a flowchart of a method for adjusting the duty cycle of a clock signal provided in an embodiment of the present application, including but not limited to steps S510 to S530.

[0073] Step S510 , converting the first clock square wave signal output by the gate driving circuit into a triangular wave signal, wherein the triangular wave signal includes a rising voltage threshold and a falling voltage threshold.

[0074] In the embodiment of the present application, the first clock square wave signal output by the gate driving circuit is first converted into a triangular wave signal, wherein the triangular wave signal includes a rising voltage threshold (V 上升 ) and the falling voltage threshold (V 下降 ), and the moment corresponding to the falling edge of the first clock square wave signal corresponds to the moment corresponding to the peak of the triangular wave, the moment corresponding to the falling edge of the first clock square wave signal corresponds to the moment corresponding to the peak of the triangular wave, and the moment corresponding to the rising edge of the first clock square wave signal corresponds to the moment corresponding to the trough of the triangular wave.

[0075] In an embodiment of the present application, the first clock square wave signal output by the gate drive circuit can be first converted into a triangular wave signal through a conversion circuit, and the moment corresponding to the falling edge of the first clock square wave signal corresponds to the moment corresponding to the peak of the triangular wave, the moment corresponding to the falling edge of the first clock square wave signal corresponds to the moment corresponding to the peak of the triangular wave, and the moment corresponding to the rising and falling edge of the first clock square wave signal corresponds to the moment corresponding to the trough of the triangular wave.

[0076] In the embodiment of the present application, the conversion circuit may be the first conversion circuit 100 proposed in any embodiment of the present application. For example, the conversion circuit may be an integration circuit. It should be noted that in the embodiment of the present application, the first clock square wave signal output by the gate drive circuit may be converted into a triangular wave signal by other circuits such as an integration operation circuit. The embodiment of the present application does not limit the conversion method.

[0077] Step S520, converting the triangular wave signal into a second clock square wave signal, wherein the moment corresponding to the falling voltage threshold in the triangular wave signal corresponds to the moment corresponding to the rising edge of the second clock square wave signal, the moment corresponding to the rising voltage threshold in the triangular wave signal corresponds to the moment corresponding to the falling edge of the second clock square wave signal, the rising voltage threshold is positively correlated with the difference between the turn-on voltage of the thin film transistor and the turn-off voltage of the turn-off thin film transistor, and the falling voltage threshold is positively correlated with the turn-on voltage.

[0078] In the embodiment of the present application, after the first clock square wave signal output by the gate drive circuit is converted into a triangular wave signal, the triangular wave signal is further converted into a second clock square wave signal by a conversion circuit. 下降 ) corresponds to the moment corresponding to the rising edge of the second clock square wave signal, and the rising voltage threshold (V 上升 ) corresponds to the time corresponding to the falling edge of the second clock square wave signal. That is, during the conversion process, the falling voltage threshold (V 下降 ) and rising voltage threshold (V 上升) determines the clock signal duty cycle (CLK Duty) of the second clock square wave signal. And the conversion circuit is designed to turn on the thin film transistor's turn-off voltage (VGH) and turn off the thin film transistor's turn-off voltage (VGL) to determine the falling voltage threshold (V 下降 ) and rising voltage threshold (V 上升 Specifically, the rising voltage threshold (V 上升 ) is positively correlated with the difference between the turn-on voltage (VGH) of the thin film transistor and the turn-off voltage (VGL) of the thin film transistor. 下降 ) is positively correlated with the turn-on voltage (VGH), so by adjusting the turn-on voltage (VGH) or the turn-off voltage (VGL), the falling voltage threshold (V 下降 ) and rising voltage threshold (V 上升 ), so that the clock signal duty cycle (CLK Duty) of the second clock square wave signal can be further adjusted accordingly.

[0079] In the embodiment of the present application, the conversion circuit can be the second conversion circuit 200 proposed in any embodiment of the present application. It should be noted that the embodiment of the present application can also convert the triangle wave signal into the second clock square wave signal through other circuit forms, and the embodiment of the present application does not limit the conversion form.

[0080] In step S530 , the turn-on voltage or the turn-off voltage is adjusted to correspondingly adjust the rising voltage threshold and the falling voltage threshold in the triangle wave signal, so that the duty cycle (CLK Duty) of the second clock square wave signal is adjusted accordingly.

[0081] In the embodiment of the present application, in the conversion design process, the turn-on voltage (VGH) and turn-off voltage (VGL) of the thin film transistor are designed to determine the falling voltage threshold (V 下降 ) and rising voltage threshold (V 上升 ), and the falling voltage threshold (V 下降 ) and rising voltage threshold (V 上升 ) is used to determine the clock signal duty cycle (CLK Duty) of the second clock square wave signal, so that by adjusting the turn-on voltage (VGH) or the turn-off voltage (VGL), the rising voltage threshold (V 上升 ) and the falling voltage threshold (V 下降 ), so that the duty cycle (CLK Duty) of the second clock square wave signal is adjusted accordingly.

[0082] Reference Figure 6 , Figure 6This is a flowchart of the steps provided in an embodiment of the present application for adjusting the turn-on voltage or the turn-off voltage to accordingly adjust the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is adjusted accordingly, including but not limited to steps S610 to S620.

[0083] Step S610, keeping the turn-off voltage unchanged, adjusting the turn-on voltage to correspondingly adjust the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is adjusted accordingly;

[0084] Step S620 , keeping the turn-on voltage unchanged, and adjusting the turn-off voltage to correspondingly adjust the rising voltage threshold of the triangle wave signal, so that the duty cycle of the second clock square wave signal is adjusted accordingly.

[0085] In the embodiment of the present application, due to the rising voltage threshold (V 上升 ) is positively correlated with the difference between the turn-on voltage (VGH) of the thin film transistor and the turn-off voltage (VGL) of the thin film transistor. 下降 ) is positively correlated with the turn-on voltage (VGH), so by keeping the turn-off voltage (VGL) unchanged and adjusting the turn-on voltage (VGH), the rising voltage threshold (V 上升 ) and the falling voltage threshold (V 下降 ), so that the duty cycle of the second clock square wave signal is adjusted accordingly. Alternatively, by keeping the start voltage (VGH) unchanged and adjusting the turn-off voltage (VGL), the rising voltage threshold (V 上升 ), so that the duty cycle (CLK Duty) of the second clock square wave signal is adjusted accordingly.

[0086] Reference Figure 7 , Figure 7 This is another step flow chart provided by an embodiment of the present application for adjusting the turn-on voltage or the turn-off voltage to accordingly adjust the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is adjusted accordingly, including but not limited to steps S710 to S740.

[0087] Step S710, keeping the turn-off voltage unchanged and reducing the turn-on voltage to correspondingly reduce the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is correspondingly reduced;

[0088] Step S720, keeping the turn-off voltage unchanged, increasing the turn-on voltage to correspondingly increase the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is correspondingly increased;

[0089] or;

[0090] Step S730, keeping the turn-on voltage unchanged and increasing the turn-off voltage to correspondingly reduce the rising voltage threshold of the triangular wave signal, so that the duty cycle of the second clock square wave signal is correspondingly reduced;

[0091] In step S740 , the turn-on voltage is kept unchanged and the turn-off voltage is reduced to correspondingly increase the rising voltage threshold of the triangle wave signal, so that the duty cycle of the second clock square wave signal is correspondingly increased.

[0092] In the embodiment of the present application, due to the rising voltage threshold (V 上升 ) is positively correlated with the difference between the turn-on voltage (VGH) of the thin film transistor and the turn-off voltage (VGL) of the thin film transistor. 下降 ) is positively correlated with the turn-on voltage (VGH), so by keeping the turn-off voltage (VGL) unchanged and adjusting the turn-on voltage (VGH), the rising voltage threshold (V 上升 ) and the falling voltage threshold (V 下降 ), so that the duty cycle of the second clock square wave signal (CLK Duty) is adjusted accordingly. Specifically, by keeping the turn-off voltage (VGL) unchanged and increasing the turn-on voltage (VGH), the rising voltage threshold (V 上升 ) and the falling voltage threshold (V 下降 ), thereby increasing the duty cycle (CLK Duty) of the second clock square wave signal accordingly. Keeping the turn-off voltage (VGL) unchanged and reducing the turn-on voltage (VGH) can correspondingly reduce the rising voltage threshold (V 上升 ) and the falling voltage threshold (V 下降 ), thereby reducing the duty cycle (CLK Duty) of the second clock square wave signal accordingly. By keeping the start voltage (VGH) unchanged and adjusting the turn-off voltage (VGL), the rising voltage threshold (V 上升 ), so that the duty cycle (CLK Duty) of the second clock square wave signal is adjusted accordingly. Specifically, by keeping the start voltage (VGH) unchanged and increasing the turn-off voltage (VGL), the rising voltage threshold (V 上升 ), thereby reducing the duty cycle (CLK Duty) of the second clock square wave signal accordingly. Keeping the start voltage (VGH) unchanged and reducing the turn-off voltage (VGL) can increase the rising voltage threshold (V 上升 ), thereby increasing the duty cycle (CLK Duty) of the second clock square wave signal accordingly.

[0093] Reference Figure 8 An embodiment of the present application provides a display panel, comprising: a gate drive circuit 20 and a linkage circuit 10 provided in any embodiment of the present application, wherein the gate drive circuit 20 is configured to output a first clock square wave signal. The linkage circuit 10 is connected to the output end of the gate drive circuit 20, and is configured to convert the first clock square wave signal into a triangular wave signal through a first conversion circuit 100, and then convert the triangular wave signal into a second clock square wave signal through a second conversion circuit 200. Since the linkage circuit can achieve linkage between the VGH voltage, the VGL voltage, and the CLK Duty, the display panel can adjust the CLK Duty accordingly by adjusting the VGH voltage or the VGL voltage, thereby realizing automated operation of the production line and improving improvement efficiency.

[0094] The present application also provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the aforementioned method for adjusting the clock signal duty cycle when executing the computer program. The electronic device can be any smart terminal, such as a tablet computer or an in-vehicle computer.

[0095] See also Figure 9 , Figure 9 The hardware structure of an electronic device according to another embodiment is shown. The electronic device includes:

[0096] The processor 901 can be implemented as a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0097] The memory 902 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 902 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 902, and the processor 901 calls and executes the clock signal duty cycle adjustment method of the embodiment of the present application;

[0098] Input / output interface 903, used to implement information input and output;

[0099] Communication interface 904, used to implement communication interaction between this device and other devices, which can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WiFi, Bluetooth, etc.);

[0100] Bus 905 , which transmits information between various components of the device (e.g., processor 901 , memory 902 , input / output interface 903 , and communication interface 904 );

[0101] The processor 901 , the memory 902 , the input / output interface 903 and the communication interface 904 are connected to each other in communication within the device via a bus 905 .

[0102] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0103] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0104] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0105] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0106] The terms "first," "second," "third," "fourth," and the like (if any) in the specification of the present application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the numbers used in this manner are interchangeable where appropriate so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or apparatus.

[0107] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0108] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0109] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0110] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0111] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: various media that can store programs, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0112] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A linkage circuit, characterized in that: The device comprises a first conversion circuit and a second conversion circuit; the first end of the first conversion circuit is used to receive a first clock square wave signal output by a gate drive circuit, the second end of the first conversion circuit is connected to the first end of the second conversion circuit, the second end and the third end of the second conversion circuit are both used to receive a turn-on voltage for turning on a thin film transistor, the fourth end of the second conversion circuit is used to receive a turn-off voltage for turning off the thin film transistor, and the fifth end of the second conversion circuit is connected to a corresponding scan line as a voltage output end; The second conversion circuit further includes a second resistor and a second capacitor, wherein a first end of the second resistor is connected to the drain of the third PMOS transistor, and a second end of the second resistor is grounded; a first end of the second capacitor is connected to the voltage output end, and a second end of the second capacitor is grounded; The first conversion circuit is configured to convert the first clock square wave signal into a triangular wave signal, wherein a falling edge of the first clock square wave signal corresponds to a peak of the triangular wave signal, and a rising edge of the first clock square wave signal corresponds to a trough of the triangular wave signal. The second conversion circuit is used to convert the triangular wave signal into a second clock square wave signal, wherein the moment corresponding to the falling voltage threshold in the triangular wave signal corresponds to the moment corresponding to the rising edge of the second clock square wave signal, and the moment corresponding to the rising voltage threshold in the triangular wave signal corresponds to the moment corresponding to the falling edge of the second clock square wave signal, the rising voltage threshold is positively correlated with the difference between the turn-on voltage and the turn-off voltage, and the falling voltage threshold is positively correlated with the turn-on voltage.

2. The linkage circuit according to claim 1, characterized in that: The first conversion circuit includes an integration circuit.

3. The linkage circuit according to claim 1 or 2, characterized in that: The first conversion circuit includes an operational amplifier and an RC circuit; the RC circuit includes a first resistor and a first capacitor; The first end of the first resistor is used to access the first clock square wave signal output by the gate drive circuit, the second end of the first resistor is connected to the negative input terminal of the operational amplifier, the second end of the first resistor is also connected to the first end of the first capacitor, the second end of the first capacitor is connected to the output terminal of the operational amplifier, the positive input terminal of the operational amplifier is grounded, and the output terminal of the operational amplifier is connected to the first end of the second conversion circuit.

4. The linkage circuit according to claim 1, characterized in that: The second conversion circuit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; The gate of the first NMOS transistor is connected to the second end of the first conversion circuit, the source of the first NMOS transistor is used to access the shutdown voltage, and the drain of the first NMOS transistor is connected to the source of the second NMOS transistor and the source of the second NMOS transistor; The gate of the second NMOS transistor is connected to the second end of the first conversion circuit, and the drain of the second NMOS transistor is connected to the voltage output end; The gate of the third NMOS transistor is connected to the voltage output terminal, and the drain of the third NMOS transistor is used to access the turn-on voltage; The gate of the first PMOS transistor is connected to the second end of the first conversion circuit, the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor and then connected to the voltage output end, and the source of the first PMOS transistor is connected to the drain of the second PMOS transistor and the source of the third PMOS transistor; The gate of the second PMOS transistor is connected to the second end of the first conversion circuit, and the source of the second PMOS transistor is used to access the turn-on voltage; The drain of the third PMOS transistor is grounded, and the gate of the third PMOS transistor is connected to the gate of the third NMOS transistor and then connected to the voltage output end.

5. A method for adjusting the duty cycle of a clock signal, applied to the linkage circuit according to any one of claims 1 to 4, characterized in that: The method comprises: Converting a first clock square wave signal output by the gate drive circuit into a triangular wave signal, wherein the triangular wave signal includes a rising voltage threshold and a falling voltage threshold, wherein the time corresponding to the falling edge of the first clock square wave signal corresponds to the time corresponding to the peak of the triangular wave signal, and the time corresponding to the rising edge of the first clock square wave signal corresponds to the time corresponding to the trough of the triangular wave signal; Converting the triangular wave signal into a second clock square wave signal, wherein a falling voltage threshold in the triangular wave signal corresponds to a rising edge of the second clock square wave signal, and a rising voltage threshold in the triangular wave signal corresponds to a falling edge of the second clock square wave signal, the rising voltage threshold is positively correlated with a difference between a turn-on voltage of a turn-on thin film transistor and a turn-off voltage of a turn-off thin film transistor, and the falling voltage threshold is positively correlated with the turn-on voltage; The turn-on voltage or the turn-off voltage is adjusted to correspondingly adjust the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is adjusted accordingly.

6. The method according to claim 5, characterized in that The adjusting the turn-on voltage or the turn-off voltage to correspondingly adjust the rising voltage threshold and the falling voltage threshold in the triangular wave signal so that the duty cycle of the second clock square wave signal is adjusted accordingly includes: Keeping the turn-off voltage unchanged, adjusting the turn-on voltage, and accordingly adjusting the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is adjusted accordingly; Alternatively, the turn-on voltage is kept unchanged, and the turn-off voltage is adjusted to correspondingly adjust the rising voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is adjusted accordingly.

7. The method according to claim 5 or 6, characterized in that The adjusting the turn-on voltage or the turn-off voltage to correspondingly adjust the rising voltage threshold and the falling voltage threshold in the triangular wave signal so that the duty cycle of the second clock square wave signal is adjusted accordingly includes: Keeping the turn-off voltage unchanged, reducing the turn-on voltage, so as to correspondingly reduce the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is correspondingly reduced; Keeping the turn-off voltage unchanged, increasing the turn-on voltage, so as to correspondingly increase the rising voltage threshold and the falling voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is correspondingly increased; or; Keeping the turn-on voltage unchanged and increasing the turn-off voltage, so as to correspondingly reduce the rising voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is correspondingly reduced; The turn-on voltage is kept unchanged, and the turn-off voltage is reduced to correspondingly increase the rising voltage threshold in the triangular wave signal, so that the duty cycle of the second clock square wave signal is correspondingly increased.

8. A display panel, characterized in that: include: Gate drive circuit; The linkage circuit according to any one of claims 1 to 4, wherein the linkage circuit is connected to the output end of the gate drive circuit.

9. An electronic device, characterized in that: The electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 5 to 7 when executing the computer program.

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