A clock-controlled comparator applied to a successive approximation analog-to-digital converter

Abstract

The present invention belongs to the field of analog integrated circuit design, and specifically relates to a clock-controlled comparator applied to a successive approximation analog-to-digital converter. The present invention selects an FIA amplifier and a cascode FIA amplifier as the preamplifier stage, and utilizes the characteristics of stable output common-mode voltage, high g m / I D and good noise performance; at the same time, the connection mode of the cascode transistor gate in the cascode FIA is adjusted to increase its overdrive voltage and accelerate the amplification speed; and it is ensured that the sizes of all inverters in the preamplifier stage are in multiples of the sizes of the inverters in the corresponding stage delay circuit; and all inverters are powered by their respective corresponding floating energy storage capacitors. The above design ensures that when the process corner changes, the response time of the amplifier and the delay of the inverter chain will change in the same amplitude together, thereby eliminating the use of a complex delay adjustment system and enabling the comparator to achieve high-precision and high-speed performance in the SAR ADC.

Description

Technical Field

[0001] The present invention belongs to the field of analog integrated circuit design, and particularly relates to a clock-controlled comparator applied to a successive approximation analog-to-digital converter. Background Art

[0002] As a communication bridge between analog circuits and digital circuits, analog-to-digital converters (ADCs) play an important role in various fields. From digital multimedia to communication, and then to biomedical and sensing control, etc., ADCs are the key bridges connecting external analog signals and digital signals. Their performance indicators, such as speed, accuracy, and power consumption, directly determine the processing capabilities of the entire system. Therefore, these indicators of ADCs are highly demanded in various fields.

[0003] Currently, the mainstream ADC structures include flash ADCs, pipelined ADCs, successive approximation ADCs (SAR ADCs), and Sigma-Delta ADCs. They each have their own characteristics and advantages in terms of power consumption, speed, accuracy, and complexity, so they also have different application fields. Among them, SAR ADCs are favored due to their relatively simple architecture, low-power design, and hardware reuse characteristics. Compared with other structures, SAR ADCs only contain one analog module, so they are easy to implement in small-size processes and have a small power consumption area. The advantages of this structure make SAR ADCs more and more important in modern circuit design.

[0004] However, there are some challenges in implementing high-precision and high-speed SAR ADCs. Different from other ADCs, SAR ADCs use the successive approximation method to approximate the target signal, and the input signal of the comparator is often small, even less than 1 LSB. For high-precision ADCs, their LSB can be as low as dozens of microvolts (μV). At this time, the input signal will be very weak and is very easy to be overwhelmed by noise and offset voltage, resulting in incorrect results. Therefore, designing a high-performance comparator is the key to achieving an excellent SAR ADC.

[0005] To address the above problems, a general approach is to cascade multiple pre-amplifiers in front of the latch, allowing the pre-amplifier to amplify the tiny input signal for a period of time and then enabling the latch stage for regeneration. However, controlling the amplification duration of the pre-amplifier is crucial for simultaneously achieving high precision and high speed performance of the comparator: too short amplification duration may cause the input signal to be overwhelmed by offset voltage and noise, while too long amplification duration will slow down the speed of the comparator. In addition, under process corner variations, a complex system is usually required to adjust the delay to match the amplification time of the amplifier. Therefore, a comparator that can co-vary the amplification duration and delay needs to be designed to solve the above problems. Summary of the Invention

[0006] In view of the above problems or deficiencies, to solve the matching problem of the response time and reserved amplification time of the preamplifier under process corner variations, the present invention provides a clock-controlled comparator for a successive approximation analog-to-digital converter, based on a floating inverter amplifier (FIA).

[0007] In the digital circuit part of this paper, the high level used refers to "1" in the digital logic signal, and the voltage is the power supply voltage V DD , which is determined by the process used to be 1.8V, 3.3V or 5V, etc.; while the low level refers to "0" in the digital logic signal, and the voltage is the ground potential V GND , which is 0V. In the analog circuit part of this paper, the power supply voltage is represented by V DD , which is determined by the process used to be 1.8V, 3.3V or 5V, etc.; the ground potential is represented by V GND , which is 0V.

[0008] A clock-controlled comparator for a successive approximation analog-to-digital converter, based on a floating inverter amplifier (FIA), includes a pre-preamplifier stage, a regenerative latch stage, and a delay control circuit (as shown in Figure 2 ). The pre-preamplifier stage is connected to the regenerative latch stage, and the delay control circuit generates control signals to control the operation of each preamplifier in the pre-preamplifier stage and the regenerative latch stage respectively.

[0009] The pre-preamplifier stage includes N stages of FIA preamplifiers and 1 stage of cascode FIA preamplifier. After the N stages of FIA preamplifiers are cascaded, they are then connected to 1 stage of cascode FIA preamplifier (N is a natural number greater than or equal to 1). Different from the conventional design where all preamplification stages and latch stages are turned on simultaneously, in the present invention, the N + 1 stages of preamplifiers are turned on sequentially through clock control, reserving a certain time for the amplification of each stage, so that the signal is fully amplified before reaching the regenerative latch stage.

[0010] The delay control circuit is an inverter chain formed by cascading multiple inverters end to end. The inverter chain has a total of N + 2 segments, and the number of inverters in each segment is determined according to the required delay, and is used to generate N + 2 segments of delay: delay 1, delay 2... delay N + 2. Φ R1 is the initial signal to control the first stage of FIA preamplifier, and is supplemented by the cumulative generation corresponding to the N + 2 segments of delay: N delay control signals Φ R2 ... Φ Rn ... Φ RN+1 required by the pre-preamplifier stage, and 2 delay control signals Φ1, Φ2 required by the regenerative latch stage (as shown in Figure 3 ). The control signal for the nth stage of FIA preamplifier is Φ Rn, n ≤ N; the control signal of the cascode FIA preamplifier is Φ RN+1 .

[0011] Φ R1 The signal is initially "0". When a high-level "1" pulse arrives after a period of time, during the high-level period, Φ R1 The signal controls the first-stage FIA preamplifier to amplify. Φ R1 After passing through the first-stage inverter, the second control signal Φ R2 is obtained. Therefore, Φ R2 The high-level pulse signal of is delayed by delay 1 compared to the pulse signal of Φ R1 . During the high-level period, Φ R2 Controls the second-stage FIA preamplifier to amplify. And so on, the control signals Φ R1 , Φ R2 …Φ Rn …Φ RN , Φ RN+1 , Φ1, Φ2 are high in turn, enabling each preamplification stage and regeneration latch stage to be turned on in sequence to achieve preamplification and then latching of the input signal.

[0012] The operations and structures of the N-stage FIA preamplifiers are all exactly the same. The structure of the nth-stage FIA preamplifier (as shown in the appendix Figure 4 ) includes a floating energy storage capacitor C Rn , a power supply V DD for charging the capacitor, two push-pull transistor inverters used as gain stages, a common-mode feedback (CMFB) structure and a gain-boosting structure, as well as an output reset circuit and a CMFB reset circuit; C Rn is the corresponding capacitor in the nth-stage FIA preamplifier.

[0013] The specific structure of the FIA preamplifier is as follows: The push-pull transistor inverter between V IP and V ON and between V IN and V OP serves as the gain stage. The circuit is not powered by the power supply voltage V DD and the ground potential V GND , but instead uses a floating energy storage capacitor C Rn to replace V DD and V GND . Both the upper and lower plates of C Rn have a switch to select whether to connect to V DD and V GND for charging or connect to the circuit for power supply. The common-mode feedback circuit is at the two output terminals V ON and V OPTwo capacitors with the same capacitance value are connected in series. The average value of the differential output is generated between the two capacitors through capacitive voltage division, that is, the output common-mode voltage. The detected common-mode voltage is respectively connected back to the two output terminals through two identical inverters to form negative feedback. The node for detecting the common-mode voltage is connected to V through a switch CM and serves as the CMFB reset circuit. The gain boosting structure uses two inverters with opposite directions connected in parallel between the two output terminals to form a cross-coupled inverter pair. The two output terminals V ON and V OP are both connected to V through a switch CM respectively and serve as the output reset circuit.

[0014] Operating principle of the FIA preamplifier: For the nth-stage FIA preamplifier, when Φ Rn is at a low level and is at a high level, the FIA is in the reset stage at this time. The power supply V DD is connected to the upper plate of the floating energy storage capacitor C Rn , the lower plate of C Rn is connected to V GND , and the voltage difference across C Rn is charged to V DD ; the FIA output terminals V OP and V ON are both connected to the common-mode voltage V CM for reset; the detected voltage of the common-mode feedback circuit is connected to the common-mode voltage V CM for reset.

[0015] When Φ Rn is at a high level and is at a low level, the FIA is in the amplification stage at this time. The two ends of the floating energy storage capacitor C Rn are respectively disconnected from V DD and the ground, and instead act as the power supply of the FIA circuit. The upper plate serves as the power supply potential and the lower plate serves as the ground potential to supply power to all the inverters in the FIA preamplifier for amplification.

[0016] The difference in the first N stages lies only in that the signals controlling the amplification are respectively and sequentially corresponding to Φ R1 , Φ R2 …Φ Rn …Φ RN , and they are sequentially high pulse signals generated by the inverter chain in the delay control circuit.

[0017] All inverters in the nth - stage FIA pre - amplifier have a multiple relationship with the inverters in the nth segment of the delay delayn corresponding to the nth stage. At the same time, the inverters in the nth - stage FIA pre - amplifier and the inverters in the nth segment of the delay are all powered by floating energy - storage capacitors. These two design features ensure that the amplification time of the nth - stage FIA matches the corresponding delay delayn and changes proportionally with the process corner.

[0018] The multiple relationship means that if the NMOS size of the inverter in the nth - stage FIA pre - amplifier is W / L and the PMOS is k*W / L (k is the mobility ratio of NMOS and PMOS transistors, usually taken as 3; the aspect ratios of NMOS and PMOS in the FIA pre - amplifier are designed considering factors such as noise, gain, and bandwidth), then the inverter size in the nth segment of the delay is: the NMOS size is a*W / a*L and the PMOS is a*k*W / a*L (a≥0).

[0019] The cascode FIA pre - amplifier (as shown Figure 5 ) includes a floating energy - storage capacitor C RN+1 , a power supply V DD for charging the capacitor, and MOS transistors M1 - M8; where M1 and M2 are PMOS input transistors, M3 and M4 are NMOS input transistors, M5 and M6 are PMOS cascode transistors, and M7 and M8 are NMOS cascode transistors. The gates of M1 and M3 are interconnected as the positive - terminal input V IP of the pre - amplifier, the gates of M2 and M4 are interconnected as the negative - terminal input V IN of the pre - amplifier. The sources of M1 and M2 are connected to the capacitor C RN+1 through switches to act as the upper plate of the power - supply voltage, and the sources of M3 and M4 are connected to the capacitor C RN+1 through switches to act as the lower plate of the ground potential. The drain of M1 is connected to the source of M5, the drain of M2 is connected to the source of M6, the drain of M3 is connected to the source of M7, and the drain of M4 is connected to the source of M8. The drains of M5 and M7 are connected together as the positive - output terminal V OP of the pre - amplifier, and the drains of M6 and M8 are connected together as the negative - output terminal V ON of the pre - amplifier. Different from the traditional design where the gates of all four cascode transistors are connected to the common - mode voltage V CM , the gate of M5 is connected to the source of M8, the gate of M8 is connected to the source of M5, the gate of M7 is connected to the source of M6, and the gate of M6 is connected to the source of M7.

[0020] The control logic of the cascode FIA pre - amplifier:

[0021] When Φ RN+1 is at a low level, at this time the cascode FIA is in the reset stage, VDD is connected to the floating energy storage capacitor C RN+1 's upper plate, and C RN+1 's lower plate is connected to V GND ; the voltage difference across C RN+1 is charged to V DD ; the outputs V OP and V ON of the cascode FIA are both connected to the common-mode voltage V CM for resetting.

[0022] Φ RN+1 is at a high level. At this time, the cascode FIA is in the amplification stage, and the floating energy storage capacitor C RN+1 is disconnected from V DD and V GND respectively, and instead acts as the power supply of the FIA circuit. The upper plate serves as the power supply potential, and the lower plate serves as the ground potential to supply power to the cascode FIA for amplification.

[0023] Similar to the FIA preamplifier, the cascode FIA also uses push-pull transistors as its input pair transistors. The sizes of its input push-pull transistors M1 - M4 are in a multiple relationship with the corresponding inverter that generates the delay delayN + 1; all inverters are also powered by the floating energy storage capacitor of the cascode FIA itself, ensuring that the amplification time of the cascode FIA matches delayN + 1 and changes in the same amplitude with the process corner.

[0024] The described regenerative latch stage (as shown in Figure 6 ) includes input pair transistors PMOS transistors M1, M4, regeneration acceleration transistors PMOS transistors M2, M3, cross-coupled inverter transistors PMOS transistors M5, M6 and NMOS transistors M7, M8 and a reset switch NMOS transistor M9.

[0025] The regenerative latch stage is controlled by a regeneration start signal Φ1 and a regeneration acceleration signal Φ2. When the signal Φ R1 that controls the first stage of the pre-preamplifier stage is at a high level, the entire pre-preamplifier stage starts its amplification work, and the pre-preamplifier stage transfers the amplified signal to the input terminals V IN and V IP of the regenerative latch stage. Subsequently, the Φ1 signal becomes low level, controlling the short-circuit switch M9 to disconnect, causing the regenerative latch stage to start regeneration, that is, amplifying the two input voltages to V DD to V GND . After a delay of delay N + 2, the gate control signals Φ2 of M2 and M3 become low level, and M2 and M3 start to generate current, accelerating the regeneration speed of the regenerative latch stage. The delay between Φ1 and Φ2 is also generated by the corresponding section of inverters in the delay control circuit.

[0026] The regeneration function is realized by using a pair of inverters connected end to end (cross-coupled inverters) in the regeneration latch stage. Similarly to the FIA preamplifier, the sizes of the cross-coupled inverters M5 - M8 in the regeneration latch stage are in a multiple relationship with the sizes of the inverters that generate the delay delayN+2 respectively, ensuring that the regeneration time of the final latch stage matches delayN+2 and changes proportionally with the process corner.

[0027] Furthermore, the inverter is of push-pull structure, composed of a PMOS transistor and an NMOS transistor. The gates of the PMOS and NMOS are connected together as the input terminal of the inverter, and their drains are connected together as the output terminal of the inverter. The source and substrate of the PMOS are connected to the power supply voltage, and the source and substrate of the NMOS are connected to the ground potential. The push-pull structure inverter can be used for reverse amplification in analog circuits. The FIA in the present invention utilizes this characteristic. In digital circuits, the output of the inverter is the opposite value of the input, that is, when the input is a high voltage, the output is a low voltage, and vice versa. However, the output will be generated after a certain delay of the input, and this delay is the delay of the inverter. The present invention uses cascaded multiple inverters to generate the delay time.

[0028] The present invention selects the FIA amplifier and the cascode FIA amplifier as the pre-preamplifier stage, taking advantage of their characteristics of stable output common-mode voltage, high g m / I D high and good noise performance. At the same time, the connection method of the gate of the cascode transistor in the cascode FIA is adjusted to increase its overdrive voltage and accelerate the amplification speed. Then, the present invention utilizes the characteristic that both the main structure of the pre-preamplifier stage and the components of the delay control circuit are inverters, which means that the response time of the preamplifier and the delay in the delay generation circuit are both related to the size of the inverter. Therefore, while ensuring that the sizes of all inverters in the pre-preamplifier stage are in a multiple relationship with the sizes of the inverters in the corresponding delay circuits, all inverters are powered by their respective corresponding floating energy storage capacitors. The above design can ensure that when the process corner changes, the response time of the preamplifier and the delay of the delay circuit will change proportionally together. Such a design can, while eliminating the use of a complex delay adjustment system, make the reserved delay match the response time of the amplifier, enabling the comparator to achieve high-precision and high-speed performance in the SAR ADC.

[0029] In summary, the present invention designs a comparator capable of jointly varying the amplification duration and delay, solving the matching problem of the response time of the preamplifier and the reserved amplification time under process corner changes, providing a basis for the realization of high-precision and high-speed SAR ADCs. Brief Description of the Drawings

[0030] Figure 1 It is a schematic diagram of the traditional FIA structure.

[0031] Figure 2 This is the overall architecture schematic diagram of the present invention.

[0032] Figure 3 This is the corresponding timing schematic diagram of the delay control circuit, the preamplifier stage, and the regenerative latch stage in the present invention.

[0033] Figure 4 This is the structural schematic diagram of the FIA preamplifier in the present invention.

[0034] Figure 5 This is the structural schematic diagram of the cascode FIA preamplifier in the present invention.

[0035] Figure 6 This is the structural schematic diagram of the regenerative latch stage in the present invention.

[0036] Figure 7 This is the schematic diagram of the overall circuit structure and the delay circuit of the embodiment. Detailed implementation manners

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and preferred embodiments.

[0038] In a specific circuit embodiment (Appendix Figure 7 ), N is selected as 2, that is, the preamplifier stage is composed of two-stage FIA and one-stage cascode FIA. The delay control circuit is formed by cascading multiple inverters end to end. The delay control circuit generates multiple signals to turn on the three-stage preamplifiers in sequence, reserves 200 ps for the amplification of each stage, can amplify the input signal by 100 dB, and can effectively reduce the input equivalent offset voltage and noise to the microvolt level.

[0039] Among them, the control signals of the first two-stage FIA preamplifiers are Φ R1 and Φ R2 , the control signal of the cascode FIA is Φ R3 , and the regeneration start and regeneration acceleration signals of the regenerative latch stage are Φ1 and Φ2 respectively. The control signals Φ R1 , Φ R2 , Φ R3 , Φ1, and Φ2 are high in sequence to control the start operation of the preamplifier stage and the regenerative latch stage respectively.

[0040] According to the above description, the specific design of this embodiment is as follows:

[0041] The total number of inverters in the inverter segment corresponding to delay1 is 6, and their sizes are 1 times, 1 times, 2 times, 2 times, 4 times, and 4 times the size of the inverter in the first-stage FIA preamplifier structure respectively.

[0042] There are 6 inverters in the inverter stage corresponding to delay2, and their sizes are 1 times, 1 times, 2 times, 2 times, 4 times, and 4 times the size of the inverter in the 2nd-stage FIA preamplifier structure respectively.

[0043] There are 5 inverters in the inverter stage corresponding to delay3, and their sizes are 1 times, 1 times, 2 times, 2 times, and 2 times the size of the inverter in the cascode FIA preamplifier structure respectively.

[0044] There are 4 inverters in the inverter stage corresponding to delay4, and their sizes are 0.5 times, 0.5 times, 1 times, and 1 times the size of the cross-coupled inverter in the regenerative latch stage respectively.

[0045] The above design ensures that the amplification time of the first-stage, second-stage FIA preamplifiers, cascode FIA preamplifier, and regenerative latch stage matches the control signals Φ R1 , Φ R2 , Φ R3 , Φ1, and Φ2 generated by the delay control system by making the sizes of the inverters in the corresponding inverter stage in a multiple relationship with the sizes of the inverters in the corresponding preamplifier or regenerative latch stage.

[0046] As can be seen from the above embodiments, the present invention uses the push-pull transistors as the amplification basis of the FIA amplifier, which is the same as the inverter structure in the delay system. Therefore, as long as their sizes are designed in proportion, when the process corner changes, the response time of the amplifier and the delay of the inverter chain change in the same proportion. This design can match the reserved delay and the response time of the amplifier while eliminating the use of a complex delay adjustment system, enabling the comparator to achieve high-precision and high-speed performance in the SAR ADC.

Claims

1. A clock-controlled comparator applied to a successive approximation analog-to-digital converter, characterized in that: It includes a pre - amplifier stage, a regenerative latch stage, and a delay control circuit; the pre - amplifier stage is connected to the regenerative latch stage, and the delay control circuit generates control signals to control the operation of each pre - amplifier in the pre - amplifier stage and the regenerative latch stage respectively; The pre - amplifier stage includes N FIA pre - amplifiers and one cascode FIA pre - amplifier. The N FIA pre - amplifiers are cascaded and then connected to the cascode FIA pre - amplifier, where N is a natural number greater than or equal to 1; the N + 1 pre - amplifiers are sequentially turned on by clock control; The delay control circuit is an inverter chain formed by connecting multiple inverters in series end to end; the inverter chain has a total of N + 2 segments, and the number of inverters in each segment is determined by the required delay, and is used to generate N + 2 segments of delay respectively: delay 1, delay2... delay N + 2; Φ R1 is the initial signal that controls the first-stage FIA preamplifier, and is supplemented by the cumulative generation corresponding to the N + 2 segments of delay: N delay control signals Φ R2 ... Φ Rn ... Φ RN+1 , and 2 delay control signals Φ1, Φ2 required for the regenerative latch stage; the control signal of the nth-stage FIA preamplifier is Φ Rn , where n ≤ N; the control signal of the cascode FIA preamplifier is Φ RN+1 ; Φ R1 The signal is initially 0. When a high-level pulse of 1 arrives, during the high-level period, Φ R1 the signal controls the first-stage FIA preamplifier for amplification, Φ R1 and the second control signal Φ is obtained through the first-stage inverter R2 , so R2 the high-level pulse signal of Φ is delayed by delay 1 compared to the pulse signal of Φ R1 . During the high-level period, Φ R2 controls the second-stage FIA preamplifier for amplification; and so on. The control signals Φ R1 , Φ R2 …Φ Rn …Φ RN , Φ RN+1 , Φ1, Φ2 are high in sequence, enabling each preamplification stage and regeneration latch stage to be turned on in sequence, realizing the preamplification and then latching of the input signal. The operation and structure of the N-stage FIA preamplifier are exactly the same. The nth-stage FIA preamplifier includes a floating energy storage capacitor C Rn , a power supply V for charging the capacitor DD , two push-pull transistor inverters used as gain stages, a common-mode feedback CMFB structure and a gain-boosting structure, and an output reset circuit and a CMFB reset circuit; C Rn is the corresponding capacitor in the nth-stage FIA preamplifier; The specific structure of the FIA preamplifier is as follows: V IP to V ON and V IN to V OP The push-pull transistor inverter between them serves as the gain stage. The circuit is not powered by the power supply voltage V DD and the ground potential V GND Instead, a floating energy storage capacitor C Rn is used to replace V DD and V GND ; Both the upper and lower plates of C Rn have a switch to select whether to connect to V DD and V GND for charging or to connect to the circuit for power supply; The common-mode feedback circuit connects two capacitors with the same capacitance in series between the two output terminals V ON and V OP to generate the average value of the differential output between the two capacitors through capacitive voltage division, that is, the output common-mode voltage. The detected common-mode voltage is respectively connected back to the two output terminals through two identical inverters to form negative feedback; The node for detecting the common-mode voltage is connected to V CM through a switch as the CMFB reset circuit; The gain boosting structure uses two inverters with opposite directions connected in parallel between the two output terminals to form a cross-coupled inverter pair; Both of the two output terminals V ON and V OP are respectively connected to V CM through a switch as the output reset circuit; All the inverters in the nth - stage FIA pre - amplifier have a multiple relationship with the inverters in the nth segment of the corresponding delay delay n. At the same time, all the inverters in the nth - stage FIA pre - amplifier and the inverters in the nth segment are powered by floating energy - storage capacitors; The multiple relationship means that: if the NMOS size of the inverter in the nth - stage FIA pre - amplifier is W / L and the PMOS is k*W / L, then the inverter size in the nth segment of the inverter has: NMOS size a*W / a*L, PMOS a*k*W / a*L, where a≥0; k is the mobility ratio of NMOS and PMOS transistors; The cascode FIA preamplifier includes a floating energy storage capacitor C RN+1 , a power supply V for charging the capacitor DD , and MOS transistors M1 - M8; among them, M1 and M2 are PMOS input transistors, M3 and M4 are NMOS input transistors, M5 and M6 are PMOS cascode transistors, and M7 and M8 are NMOS cascode transistors; the gates of M1 and M3 are interconnected as the positive - terminal input V IP of the preamplifier, the gates of M2 and M4 are interconnected as the negative - terminal input V IN of the preamplifier, the sources of M1 and M2 are connected to the capacitor C through switches RN+1 which acts as the upper plate of the power - supply voltage, the sources of M3 and M4 are connected to the capacitor C through switches RN+1 which acts as the lower plate of the ground potential; the drain of M1 is connected to the source of M5, the drain of M2 is connected to the source of M6, the drain of M3 is connected to the source of M7, and the drain of M4 is connected to the source of M8; the drains of M5 and M7 are connected together as the positive - output terminal V OP of the preamplifier, the drains of M6 and M8 are connected together as the negative - output terminal V ON of the preamplifier; the gate of M5 is connected to the source of M8, the gate of M8 is connected to the source of M5, the gate of M7 is connected to the source of M6, and the gate of M6 is connected to the source of M7; Similarly to the FIA pre - amplifier, the cascode FIA also uses push - pull transistors as its input pair transistors. The size of its input push - pull transistors M1 - M4 has a multiple relationship with the corresponding inverter that generates the delay delay N + 1; all the inverters are also powered by the floating energy - storage capacitors of the cascode FIA itself, ensuring that the amplification time of the cascode FIA matches delay N + 1 and changes in the same amplitude with process corners; The regenerative latch stage includes input pair transistors PMOS transistors M1, M4, regenerative acceleration transistors PMOS transistors M2, M3, cross - coupled inverter transistors PMOS transistors M5, M6 and NMOS transistors M7, M8, and a reset switch NMOS transistor M9; The regenerative latch stage is controlled by a regeneration start signal Φ1 and a regeneration acceleration signal Φ2. When Φ R1 is at a high level, the entire preamplifier stage starts its amplification operation. The preamplifier stage transfers the amplified signal to the input terminals V IN and V IP of the regenerative latch stage; subsequently, the Φ1 signal becomes low, controlling the short - circuit switch M9 to open, enabling the regenerative latch stage to start regeneration, that is, amplifying the two input voltages to V DD to V GND respectively; after a delay of delay N + 2, the gate control signal Φ2 of M2 and M3 becomes low, and M2 and M3 start to generate current, accelerating the regeneration speed of the regenerative latch stage. The delay between Φ1 and Φ2 is also generated by the corresponding segment of inverters in the delay control circuit; In the regenerative latch stage, a cross - coupled inverter connected end - to - end is used to achieve the regeneration function. Similarly to the FIA pre - amplifier, the size of the cross - coupled inverters M5 - M8 in the regenerative latch stage has a multiple relationship with the size of the corresponding inverter that generates the delay delayN + 2, ensuring that the regeneration time of the final latch stage matches delayN + 2 and changes in the same amplitude with process corners.

2. The clock - controlled comparator applied to a successive - approximation analog - to - digital converter as claimed in claim 1, characterized in that: The operating principle of the FIA preamplifier: For the nth-stage FIA preamplifier, Φ Rn is at a low level, is at a high level. At this time, the FIA is in the reset stage, and the power supply V DD is connected to the upper plate of the floating energy storage capacitor C Rn , and the lower plate of C Rn is connected to V GND . The voltage difference across C Rn is charged to V DD ; The output terminals V OP and V ON of the FIA are both connected to the common-mode voltage V CM for reset; The detection voltage of the common-mode feedback circuit is connected to the common-mode voltage V CM for reset; Φ Rn is at a high level, when it is at a low level, at this time the FIA is in the amplification stage, and the floating energy storage capacitor C Rn is disconnected from V DD and ground at both ends respectively, and instead acts as the power supply of the FIA circuit. The upper plate serves as the power supply potential, and the lower plate serves as the ground potential, supplying power to all inverters in the FIA preamplifier for amplification; The difference between the first N levels lies only in that the signals to be controlled for amplification correspond one by one in sequence to Φ R1 , Φ R2 …Φ Rn …Φ RN , which are high-level pulse signals generated in sequence by the inverter chain in the delay control circuit.

3. The clock - controlled comparator applied to a successive - approximation analog - to - digital converter as claimed in claim 1, characterized in that: The control logic of the cascode FIA pre - amplifier: Φ RN+1 When it is at a low level, the cascode FIA is in the reset stage, and V DD is connected to the upper plate of the floating energy storage capacitor C RN+1 , and the lower plate of C RN+1 is connected to V GND . The voltage difference across C RN+1 is charged to V DD . The output terminals V OP and V ON of the cascode FIA are both connected to the common-mode voltage V CM for resetting; Φ RN+1 When it is at a high level, the cascode FIA is in the amplification stage, and both ends of the floating energy storage capacitor C RN+1 are disconnected from V DD and V GND respectively, and instead act as the power supply of the FIA circuit. The upper plate serves as the power supply potential, and the lower plate serves as the ground potential to supply power to the cascode FIA for amplification.

4. The clock - controlled comparator applied to a successive - approximation analog - to - digital converter as claimed in claim 1, characterized in that: The inverter is of a push - pull structure, composed of a PMOS transistor and an NMOS transistor. The gates of the PMOS and NMOS are connected as the input of the inverter, and their drains are connected as the output of the inverter; the source and substrate of the PMOS are connected to the power supply voltage, and the source and substrate of the NMOS are connected to the ground potential.

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