A heterogeneous integrated optoelectronic chip based on an optical penetration substrate channel

Abstract

The present invention discloses a heterogeneous integrated optoelectronic chip based on an optically penetrating substrate channel, which includes a multi-layer stacked optoelectronic chip based on several substrates of the same or different types. A number of optoelectronic devices are provided on each layer of the optoelectronic chip. There is at least one pair of optically penetrating substrate channels with an interlayer coupling structure provided between the optoelectronic chip layers, so as to establish an optical interconnection between at least one pair of optoelectronic devices on different layers; the interlayer coupling structure includes a coupling grating with a high alignment tolerance, and a metal high-reflection film can be fabricated on the cladding at a certain distance from the coupling grating to achieve highly efficient coupling in one direction. The present invention solves the technical difficulties of silicon-based III-V heterogeneous integration and 3D multi-layer chip stacking. It realizes optical interconnection between multi-layer chips through optically penetrating substrate channels, and at the same time enables the front electrodes of one or more optoelectronic chips to be used for interconnection with electrical chips, avoiding the electrically penetrating substrate channels (TSVs) with high manufacturing difficulty.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic chips, and particularly to a heterogeneous integrated optoelectronic chip based on an optical penetration substrate channel. Background Art

[0002] Currently, data centers / intelligent computing systems are all composed of thousands of servers connected through fiber optic networks. In addition to the core computing power chips in the servers, the high-speed optical switching and interconnection network between a large number of computing power chips or servers is the key to the overall computing power improvement and efficient utilization of intelligent computing / supercomputing systems. To reduce the volume, energy consumption, and cost of intelligent computing system devices, the existing technology applies the advanced wafer-level packaging technology based on chiplets in the field of large-scale integrated circuits to optical chips and optoelectronic integrated circuits on a chip, including through-silicon via (TSV) and re-distribution layer (RDL) technologies, etc., enabling the front side of the silicon optical chip to be integrated with III-V lasers, and at the same time, through the through-silicon via (TSV) as an electrical penetration substrate channel, its back side can be electrically interconnected and integrated with an electrical computing power chip.

[0003] In terms of heterogeneous integration of silicon-based III-V compound semiconductors, there are mainly three technologies currently adopted:

[0004] One is the III-V / SOI (Silicon-on-Insulator) bonding technology based on evanescent wave coupling. However, its defects are that its manufacturing process is complex, the III-V wafer size is mismatched with the Si wafer size, and most of the III-V materials in most areas are etched and wasted. Coupled with the lattice mismatch and thermal expansion coefficient mismatch between the III-V semiconductor and Si, there are problems with yield and reliability.

[0005] The second is to directly grow III-V quantum dot materials on a silicon wafer. However, its defects are that a very thick buffer layer and defect filtering layer need to be grown before growing quantum dots on silicon. In this way, the III-V waveguide and the Si waveguide cannot use evanescent wave coupling, but can only use butt coupling. It is necessary to grow III-V gain materials in etched trenches, and it is necessary to precisely control the growth conditions. It requires more than 20 layers of masks and more than a hundred processing steps. It is very difficult to control the laser performance and yield, and the cost is high.

[0006] Third, it is the end-face coupling technology based on flip-chip bonding. However, the defect is that it is difficult to achieve the required alignment accuracy for strongly confined small-mode field waveguides such as SOI. In addition, for wafer-level packaging, the locally protruding III-V chips hinder the surface planarization of the silicon photonics chip, and also hinder the interconnection between the SOI surface electrode and the electrical chip or interposer, which is not compatible with the wafer-level CMOS advanced packaging process. Summary of the Invention

[0007] The object of the present invention is to provide a heterogeneous integrated optoelectronic chip based on an optical through-substrate channel, and propose an optical through-substrate channel structure (referred to as optical TSV, Optical Through-Substrate Via) for 3D integration of multilayer optoelectronic chips in a wafer-level system-on-chip, while solving the technical difficulties of silicon-based III-V heterogeneous integration and 3D multilayer chip stacking interconnection. Through the advanced packaging technology of chiplet integration, the optical transceiver interconnection chip and electrical chips such as GPU / NPU are integrated on a wafer-level system-on-chip. Not only are the electro-optical and optoelectronic conversions of the GPU / NPU ports integrated inside the optical chip, which greatly improves the chip integration and significantly reduces the system size, but also through the innovative optical TSV, the optical signal penetrates the InP and Si substrates, achieving high-efficiency and high-tolerance optical coupling between the III-V waveguide layer and the SOI or SiN layer, while avoiding flip-chip bonding between the III-V chip and the SiN / SOI chip, and leaving the front electrode layers of these two chips for electrical interconnection with the electrical chip or RDL or PCB, thus avoiding the use of conventional electrical TSVs with high process difficulty on the silicon photonics chip.

[0008] To achieve the above object, the present invention provides a heterogeneous integrated optoelectronic chip based on an optical through-substrate channel, including a multilayer stacked optoelectronic chip based on several substrates of the same or different types. A number of optoelectronic devices and optical waveguides are provided on each layer of the optoelectronic chip. At least one pair of different-layer optoelectronic chips are each provided with an interlayer coupling structure. There is an optical through-substrate channel through which light can propagate between the interlayer coupling structures of the at least one pair of optoelectronic chips. The optical through-substrate channel penetrates at least one substrate. The first interlayer coupling structure in the first-layer optoelectronic chip based on the first substrate converts the light propagating along the optical waveguide in the plane of this layer of optoelectronic chip into light propagating along the optical through-substrate channel through a reflection or diffraction mechanism. The second interlayer coupling structure in the second-layer optoelectronic chip based on the second substrate converts the light propagating along the optical through-substrate channel into light propagating along the optical waveguide in the plane of this layer of optoelectronic chip through a reflection or diffraction mechanism.

[0009] Preferably, the first-layer optoelectronic chip based on the first substrate includes at least one of an optical signal emitting device, an optical amplifier, an optical modulator, an optical detector, and a passive optical waveguide interconnect device. The interlayer coupling structure of this layer of optoelectronic chip is a coupling grating or a mirror composed of an inclined etched surface;

[0010] The second-layer optoelectronic chip based on the second substrate includes at least one of a passive optical waveguide interconnect device, an optical modulator, and an optical signal receiver. The interlayer coupling structure of this layer of optoelectronic chip is a coupling grating or a mirror composed of an inclined etched surface.

[0011] Preferably, the first-layer optoelectronic chip and the second-layer optoelectronic chip are coupled back-to-back, and the back surface of the first substrate contacts or bonds with the back surface of the second substrate. The contact surface of one or both substrates is a smooth surface or coated with an optical antireflection film.

[0012] Preferably, the first-layer optoelectronic chip and the second-layer optoelectronic chip are coupled face-up. The back surface of the first substrate contacts the front surface of the second-layer optoelectronic chip, and the back surface of the first substrate is a smooth surface or coated with an optical antireflection film.

[0013] Preferably, the first substrate is InP, GaAs, or a compound semiconductor material, and the second substrate is Si, SiO2, quartz, or an organic substrate material.

[0014] Preferably, the first interlayer coupling structure is a chirped collimating grating, such that the light coupled into the optical through-substrate channel is a parallel beam of light, and by optimizing the design of the grating etching depth and the gradually changing duty cycle, a gradually changing grating coupling coefficient is obtained, such that the light emitted into the optical through-substrate channel has a certain optical field distribution, meeting the conditions of large alignment tolerance and large coupling efficiency.

[0015] Preferably, a metal high-reflection film is deposited on the upper surface of the chirped collimating grating as a metal mirror. The metal high-reflection film has a certain distance from the grating, such that the light directly diffracted by the chirped collimating grating into the optical through-substrate channel diffracts upward from the grating and then is reflected by the metal high-reflection film into the optical through-substrate channel, and the two beams of light can interfere constructively, making the light emitted into the optical through-substrate channel the strongest.

[0016] Preferably, the first interlayer coupling structure is an etched surface placed at a specific angle, such that when light is incident from the waveguide to the etched surface, total reflection occurs and the light penetrates the substrate.

[0017] Preferably, the second interlayer coupling structure is a chirped focusing grating, which focuses the optical signal received from the optical through-substrate channel to the optical signal receiving point on the second-layer optoelectronic chip, and by optimizing the design of the grating etching depth and the gradually changing duty cycle, the receiving coupling efficiency is maximized.

[0018] Preferably, a metal high-reflection film is deposited on the surface of the chirped focusing grating cladding as a metal mirror. There is a certain distance between the metal high-reflection film and the chirped focusing grating, such that the light directly diffracted from the optical penetration substrate channel through the chirped focusing grating to the optical signal receiving point and the light energy that penetrates the grating, is reflected by the metal high-reflection film and then diffracted by the chirped focusing grating to the optical signal receiving point are in phase and coherent, making the light coupled to the optical signal receiving point the strongest.

[0019] The present invention adopts the above-mentioned heterogeneous integrated optoelectronic chip based on an optical penetration substrate channel, which has the following advantages:

[0020] The heterogeneous integration and 3D interconnection scheme based on optical TSV proposed by the present invention has high flexibility and versatility. Each chip or wafer can be manufactured using mature processes respectively, and then undergo 3D heterogeneous integration and interlayer coupling after testing. Moreover, compared with other heterogeneous integration bonding methods, the process is simpler and the alignment tolerance is larger, thus greatly improving the yield of heterogeneous integration and on-chip systems. Compared with the full-wafer quantum dot epitaxial growth method, the scheme of the present invention uses mature processes, greatly reducing the complexity and difficulty of epitaxy and post-processes, significantly improving the utilization efficiency of the InP epitaxial area, reducing the manufacturing difficulty of large-area wafer-level interconnection, and thus significantly reducing costs. Moreover, through the interlayer interconnection of optical TSVs, the front electrode of the SOI chip can be conveniently flip-chip bonded to the interposer, realizing high-speed electrical interconnection with electrical drive, computing power, and switching chips, avoiding the use of high-difficulty traditional electrical TSV via processes on silicon optical chips. The front electrode of the upright InP chip can also be conveniently used for direct electrical connection with external circuits such as electrical drive chips, without the need for fan-out transfer through the precious active silicon optical chip.

[0021] Due to the extremely strong flexibility and universality of the interlayer optical interconnection and three-dimensional heterogeneous integration through the substrate of the present invention, it can become a standard multi-functional optoelectronic integration platform, which can not only be used for heterogeneous integrated optoelectronic chips, but also for the multi-layer stacked interconnection integration of electrical computing power chips with optical transceiver ports.

[0022] The technical solution of the present invention will be further described in detail below through the accompanying drawings and embodiments. Description of the Drawings

[0023] Figure 1 It is a schematic structural diagram of Embodiment 1 of the present invention;

[0024] Figure 2 It is a top view of the InP chip coupling grating in Embodiment 1 of the present invention, where P is the end point of the emission optical waveguide;

[0025] Figure 3 This is a top view of the silicon photonics chip coupling grating in the first embodiment of the present invention, where Q is the end point of the receiving optical waveguide;

[0026] Figure 4 This is a schematic structural diagram of the second embodiment of the present invention;

[0027] Figure 5 This is a schematic structural diagram of the third embodiment of the present invention.

[0028] Reference numerals: 100, InP chip drive circuit; 101, packaging substrate; 102, solder ball array; 103, electrical through-hole; 104, SiO2 layer; 105, silicon waveguide layer; 106, SiN waveguide; 107, silicon substrate; 108, SiN wafer silicon substrate; 109, SOI wafer silicon substrate; 110, InP substrate; 111, InP waveguide layer; 112, main board PCB; 113, intermediate transfer layer; 114, optical signal input port; 115, optical signal output port; 20, power monitor; 30, laser; 400, InP chip side interlayer coupling reflecting surface; 401, InP chip side interlayer coupling grating; 402, silicon photonics chip side interlayer coupling grating one; 411, SiN waveguide interlayer coupling grating one; 412, silicon photonics chip side interlayer coupling grating two; 421, SiN waveguide interlayer coupling grating two; 422, silicon photonics chip side interlayer coupling grating three; 50, metal mirror; 500, through-substrate channel; 501, through-substrate channel one; 502, through-substrate channel two; 503, through-substrate channel three; 60, high-speed detector; 70, silicon waveguide device; 80, high-speed modulator. Detailed implementation manners

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and shown in the accompanying drawings here can be arranged and designed in various different configurations. The specific structure needs to be determined according to the specific functions and material characteristics of the chip, etc. The specific selection and design calculation methods adopt the existing technologies in the art, so no detailed description will be given here.

[0030] Embodiment 1

[0031] As Figure 1As shown in the figure, it is a schematic diagram of a heterogeneous integration and interconnection solution based on optical TSV penetrating InP and Si substrates. The structure from top to bottom is as follows: InP chip drive circuit 100, electrical through-hole 103, metal mirror 50, InP waveguide layer 111, InP substrate 110, silicon substrate 107, SiO2 layer 104, silicon waveguide layer 105, metal mirror 50, solder ball array 102, and packaging substrate 101;

[0032] Among them, a power monitor 20, a laser 30, and an InP chip side interlayer coupling grating 401 are provided in the InP waveguide layer 111, and a silicon photonic chip side interlayer coupling grating 402, a high-speed modulator 80, a silicon waveguide device 70, and a high-speed detector 60 are provided in the silicon waveguide layer.

[0033] In the first embodiment, for the optoelectronic chips on the InP substrate and the Si substrate, a back-to-back coupling method is selected, that is, the back surfaces of the InP substrate and the Si substrate are bonded to each other in contact.

[0034] First, the InP chip is fabricated on a semi-insulating (Semi-Insulating) or doped InP substrate through mature III-V semiconductor processes, including mature processes such as quantum well / quantum dot epitaxial growth, waveguide etching, interlayer coupling grating fabrication, SiO2 insulating layer deposition, Via window opening, and metal electrode deposition.

[0035] According to the system function requirements, in addition to the laser, the InP active devices can also include diode structures such as modulators, amplifiers, and detectors. Their p and n electrodes are fabricated on the upper surface of the chip. Therefore, the usually required ground electrode is not deposited on the back surface of the chip, enabling light to penetrate the substrate. A metal mirror is fabricated on the top of the grating while depositing the metal electrode on the upper surface of the chip. Similarly, high-speed modulators, high-speed Ge / Si detectors, arrayed waveguide grating wavelength division multiplexing / router and other active and passive devices, as well as interlayer coupling gratings, are fabricated on the SOI wafer.

[0036] The polished back surfaces of the SOI chip and the InP chip are aligned and fixed back-to-back, grating-to-grating, as Figure 1 shown. One implementation method is to use molecular covalent bonding. A layer of SiO2 with a thickness of a few nanometers is grown on the back surfaces of the Si chip and the III-V chip substrate respectively, and the two are brought close together and bonded together by the van der Waals force between molecules. Adhesive bonding can also be used, using an organic substance (such as DVS-BCB) to bond the silicon chip and the III-V chip together. Since it is a bond between two flat polished substrates without pattern processing on the surface, their bond is more firm and reliable than the traditional chip front-side flip-chip method.

[0037] In this embodiment, the light emitted from the laser 30 in the InP chip and propagating along the InP waveguide is converted into a parallel light beam emitted in a direction nearly perpendicular to the substrate by the InP interlayer coupling grating 401, and sequentially penetrates the InP substrate 110 and the silicon substrate 107 of the SOI chip along the optical through-substrate channel 501, and then is interconnected to devices such as the high-speed modulator 80, the silicon waveguide device 70, and the high-speed detector 60 on the SOI chip through the interlayer coupling grating 402 on the SOI waveguide.

[0038] As Figure 2 shown, the light emitted from the waveguide end point P, diffracted by the grating, and finally emitted into the optical through-substrate channel is close to a parallel light beam. Through the design of the chirped collimating grating by apodization, the grating etching depth and the gradually changing duty cycle are optimized to obtain a gradually changing grating coupling coefficient, so that the light emitted into the optical through-substrate channel has a certain optical field distribution, the emitted beam size is large and collimated, so that a large alignment tolerance can be obtained, and passive alignment can be used.

[0039] Because the grating diffraction inevitably also emits upward from the chip, based on the idea of optical TSV emitting toward the substrate, we can conveniently deposit a metal mirror on the upper surface of the chip, thus avoiding the stepped blazed grating tooth surface that requires two-step etching with more complex processes, and improving the diffraction directivity and the efficiency of emitting toward the substrate. The metal high-reflection film has a certain distance from the grating, so that the light directly diffracted by the chirped collimating grating into the optical through-substrate channel and the light diffracted upward from the grating and then reflected by the metal high-reflection film into the optical through-substrate channel can be in phase and coherent, making the light emitted into the optical through-substrate channel the strongest.

[0040] Similarly, we can design the chirped focusing coupling grating and the surface metal high-reflection film on the SOI waveguide plane. By optimizing the grating etching depth and the gradually changing duty cycle, a gradually changing grating coupling coefficient is obtained, and the incident collimated light is efficiently focused on the input port Q of the SOI modulator waveguide, as Figure 3 shown. In addition, the distance between the metal high-reflection film and the grating is optimized, so that the light directly diffracted from the optical through-substrate channel through the chirped focusing grating to the optical signal receiving point Q and the light passing through the grating, then reflected by the metal high-reflection film, and then diffracted by the chirped focusing grating to the optical signal receiving point can be in phase and coherent, making the light coupled to the optical signal receiving point the strongest, thus realizing high-efficiency interlayer coupling interconnection.

[0041] In the above embodiment, the optical path difference of the light emitted from the waveguide end point P on the InP chip, diffracted by different grating teeth of the InP side interlayer coupling grating, then emitted into the optical through-substrate channel, and then diffracted by different grating teeth of the silicon photonics chip side interlayer coupling grating through the through-substrate channel and then reaching the focusing point Q on the silicon optical waveguide plane is an integer multiple of the optical wavelength.

[0042] Example 2:

[0043] In the above Example 1, the inter-layer coupling grating 401 on the InP chip side can be replaced by an inter-layer coupling reflecting surface 400 on the InP chip side. As Figure 4 shown, the inter-layer coupling reflecting surface 400 on the InP chip side can be fabricated by a local wet chemical etching method to obtain a smooth total reflection surface along a certain crystal orientation angle. In this embodiment, the light propagating along the InP waveguide emitted from the laser 30 in the InP chip is reflected by the InP inter-layer coupling reflecting surface 400 and then exits through the substrate channel 500 at a certain divergence angle towards the substrate, penetrates the InP substrate 110 and the silicon substrate 107 of the SOI chip in sequence along the penetrating substrate channel, and then is diffracted and focused onto the input port Q of the SOI optical waveguide by the inter-layer coupling grating 402 on the SOI waveguide, as Figure 3 shown, and then interconnected to devices such as the high-speed modulator 80, silicon waveguide device 70, and high-speed detector 60 on the SOI chip. By designing the position of each grating tooth of the coupling grating on the SOI waveguide plane, the optical path difference between the light that travels from the total reflection mirror R on the InP chip through the penetrating substrate channel to the silicon optical chip and is diffracted by different grating teeth and then reaches the focal point Q on the silicon optical waveguide plane is an integer multiple of the optical wavelength, so that the inter-layer coupling grating has a chirped imaging function, that is, imaging the position R point of the total reflection mirror on the InP chip to the light wave input point Q on the silicon optical chip. By optimizing the grating etching depth and the gradually changing duty cycle, a gradually changing grating coupling coefficient is obtained. In addition, the distance between the metal mirror 50 and the grating is optimized, so that the light directly diffracted from the optical penetrating substrate channel through the chirped focusing grating to the optical signal receiving point Q and the light that penetrates the grating, is reflected by the metal high-reflection film, and then diffracted by the chirped imaging grating to the optical signal receiving point Q can interfere constructively, making the light coupled to the optical signal receiving point the strongest, thus achieving high-efficiency inter-layer coupling interconnection.

[0044] Example 3

[0045] Since SOI silicon photonics chips usually require processing with a process below 130 nm, the chip size based on Stepper precision lithography is usually limited within a reticle area of 26 mm × 33 mm. To achieve a larger area or even a wafer-scale system-on-chip, it can be realized by the method of stitching and exposing multiple reticles. However, this will lead to a multiple increase in the number of exposures. Moreover, due to the small size of the SOI waveguide, the stitching error will cause additional interconnect losses, with high manufacturing difficulty and a decrease in the yield. Multiple reticles will also lead to a sharp increase in costs. To solve this problem, a silicon-based Si3N4 (abbreviated as SiN) or SiO2 (PLC) passive waveguide platform with a simple process can be used to achieve large-area optical interconnection at the wafer scale or even beyond the wafer scale, which only requires one step or very few lithography processes, with low precision requirements. Even a PLC platform using contact lithography or an optical backplane platform made of organic materials can be used to significantly reduce costs.

[0046] As Figure 5 shown, it is a multi-layer stacked heterogeneous integration and coupled interconnection scheme based on three waveguide material platforms of InP, SiN, and SOI. The structure from top to bottom is as follows: InP chip driving circuit 100, electrical through-hole 103, metal mirror 50, InP waveguide layer 111, InP substrate 110, SiN waveguide 106, SiN wafer silicon substrate 108, SOI wafer silicon substrate 109, SiO2 layer 104, silicon waveguide layer 105, metal mirror 50, solder ball array 102, intermediate transfer layer 113, solder ball array 102, main board PCB 112;

[0047] Among them, the InP waveguide layer includes a power monitor 20, a laser 30, and an InP chip side interlayer coupling grating 401. The SiN waveguide 106 is provided with SiN passive waveguide devices and SiN waveguide interlayer coupling gratings. The silicon waveguide layer 105 includes a silicon photonics chip side interlayer coupling grating, a high-speed modulator 80, silicon waveguide devices 70, and a high-speed detector 60;

[0048] Among them, the SiN waveguide interlayer coupling grating includes a SiN waveguide interlayer coupling grating one 411, a SiN waveguide interlayer coupling grating two 421, etc.;

[0049] Among them, the silicon photonics chip side interlayer coupling grating includes a silicon photonics chip side interlayer coupling grating one 402, a silicon photonics chip side interlayer coupling grating two 412, a silicon photonics chip side interlayer coupling grating three 422, etc.;

[0050] One end of the SiN waveguide layer is an optical signal input port 114, and the other end is an optical signal output port 115;

[0051] In the third embodiment of the multi-layer stack based on three waveguide material platforms, a large-area silicon-based SiN passive waveguide wafer will serve as the optical substrate and be fixed by back-to-back bonding of two silicon substrates with the SOI active silicon photonics chip. The two inter-layer coupling gratings on the SiN waveguide and the SOI waveguide are used for interconnection. The substrate of the InP chip is bonded to the SiO2 upper cladding that has been planarized by CMP on the front side of the SiN waveguide wafer. The light emitted by the laser 30 in the InP chip and propagating along the InP waveguide is converted into a parallel beam emitted in a direction nearly perpendicular to the substrate through the InP inter-layer coupling grating 401, and sequentially penetrates the InP substrate 110, the SiN waveguide 106 and its Si substrate 108, and the Si substrate 109 of the SOI chip along the through-substrate channel one 501. Then, it is interconnected to devices such as the high-speed modulator 80 and the silicon waveguide device 70 on the SOI chip through the inter-layer coupling grating one 402 on the SOI waveguide, and then diffracted to the through-substrate channel two 502 through the inter-layer coupling grating two 412 on the silicon photonics chip side, sequentially penetrating the Si substrate 109 of the SOI chip and the Si substrate 108 of the SiN waveguide, and then coupled to the SiN waveguide 106 through the inter-layer coupling grating one 411 on the SiN wafer. Through the large-area multi-node interconnection network of the SiN waveguide layer, it is sent to the on-chip remote node from the port 115. The optical signal emitted by the remote node enters from the port 114 in the SiN waveguide layer 106, is coupled to the through-substrate channel three 503 through the inter-layer coupling grating two 421 on the SiN waveguide side, sequentially penetrating the Si substrate 108 of the SiN waveguide and the Si substrate 109 of the SOI chip, and then coupled to the high-speed detector 60 on the SOI chip through the inter-layer coupling grating three 422, which converts it into an electrical signal. The propagation direction of the optical signal in the multi-layer chip is as shown by the arrows. The physical boundaries for penetrating the substrate do not need to be fabricated for each of the optical through-substrate channels 501, 502, 503. Instead, they are defined by the design of the inter-layer couplers at both ends, which are easier to fabricate than electrical TSVs. The substrates of each wafer can be thinned appropriately as needed. Anti-reflection (AR) dielectric films can be deposited on the SiN waveguide wafer before depositing the SiO2 lower cladding and after depositing the SiO2 upper cladding respectively to reduce the reflection loss of the inter-layer interconnection. As needed, passive devices such as low-loss and low-crosstalk arrayed waveguide grating wavelength division multiplexers / router and splitters can also be fabricated on the SiN waveguide layer. The SiN waveguide can also be replaced by a SiO2 waveguide or an organic material waveguide, or can be directly fabricated on the SOI chip wafer.

[0052] By using a semi-insulating or undoped InP substrate and a silicon substrate, the optical propagation loss of the optical penetration substrate channel of the present invention can achieve ultra-low loss. For example, the transmission loss of a 600-micron-thick semi-insulating InP substrate measured experimentally is only 0.3 dB. Since the optical signal exits or enters from the substrate direction, it is convenient to deposit a metal mirror film above the grating on the front side of the chip to achieve high-efficiency coupling in a single direction. The loss of the optimized coupling grating can theoretically be as low as below 0.5 dB. Based on the principle of apodized imaging, by optimizing the etching depth and the tapered duty cycle of the grating to obtain a tapered grating coupling coefficient, the diffraction light field that originally exponentially decreases along the waveguide propagation direction on the grating is trimmed into a shape close to Gaussian, and can propagate in a conformal and collimated manner when penetrating the substrate, with a diameter that can be as large as dozens of microns, so that a large alignment tolerance can be obtained.

[0053] Therefore, the present invention adopts a heterogeneous integrated optoelectronic chip based on an optical penetration substrate channel, and proposes an optical penetration substrate channel structure for 3D integration of multi-layer photon chips for wafer-level on-chip system applications, while solving the technical difficulties of silicon-based III-V heterogeneous integration and 3D multi-layer chip stacking. Through the advanced packaging technology of chiplet integration, the optical transceiver interconnection chip and electrical chips such as GPU / NPU are integrated on the wafer-level on-chip. Not only are the electro-optical and opto-electronic conversions of the GPU / NPU ports integrated inside the optical chip, which greatly improves the chip integration and significantly reduces the system size. Through innovative optical TSVs, the optical signal penetrates the InP and Si substrates, while achieving high-efficiency and high-tolerance optical coupling between the III-V waveguide layer and the SOI or SiN layer, avoiding flip-chip bonding between the III-V chip and the SiN / SOI chip, and leaving the front electrode layers of these two chips for electrical interconnection with the electrical chip or RDL / PCB, thus avoiding the use of traditional electrical TSVs with high process difficulty on the silicon optical chip.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the embodiments, those of ordinary skill in the art should understand that they can still modify or equivalently replace the technical solutions of the present invention, and these modifications or equivalent replacements cannot make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A heterogeneous integrated optoelectronic chip based on an optically penetrating substrate channel, characterized by: The invention relates to a multi-layer stacked optoelectronic chip based on several substrates of the same or different types, wherein each layer of the optoelectronic chip is provided with several optoelectronic devices and optical waveguides, and at least one pair of optoelectronic chips of different layers are respectively provided with an interlayer coupling structure, and an optically penetrating substrate channel through which light can propagate exists between the interlayer coupling structures of the at least one pair of optoelectronic chips, and the first layer of the optoelectronic chip and the second layer of the optoelectronic chip in the at least one pair of optoelectronic chips are coupled back to back, that is, the back surface of the first substrate and the back surface of the second substrate are in contact with or bonded to each other, and the optically penetrating substrate channel penetrates at least two substrates, wherein the first layer of the optoelectronic chip based on the first substrate is provided with an optically penetrating substrate channel through which light can propagate. An interlayer coupling structure is provided, which converts light propagating along the optical waveguide within the plane of the optoelectronic chip layer into light propagating along the optical penetrating substrate channel in the first substrate through a reflection or diffraction mechanism. The first interlayer coupling structure is a chirped collimating grating. A gradually varying grating coupling coefficient is obtained by optimizing the grating etching depth and the gradually varying duty cycle. The diffracted light field on the grating, which originally decreases exponentially along the waveguide propagation direction, is clipped into a nearly Gaussian shape. When penetrating the substrate, the diffracted light field is propagated in a conformal and collimated manner, and the emitted light beam is large and collimated, achieving a required alignment tolerance. The light is converted by the interlayer coupling grating into a parallel light beam emitted in a direction nearly perpendicular to the substrate. The second interlayer coupling structure in the second layer of optoelectronic chip based on the second substrate converts the light propagating along the optically penetrating substrate channel in the second substrate into light propagating along the optical waveguide in the plane of the optoelectronic chip layer through a reflection or diffraction mechanism; the front electrode of the first layer of optoelectronic chip is directly electrically connected to the external circuit, and the front electrode of the second layer of optoelectronic chip is flip-chip bonded to the adapter substrate to achieve high-speed electrical interconnection with the electric drive, computing power and switching chips, and realize interlayer signal transmission through the optically penetrating substrate channel, thereby avoiding the difficult traditional electrical TSV through-hole process.

2. The heterogeneous integrated optoelectronic chip based on optically penetrating substrate channels according to claim 1, characterized in that: The first layer of optoelectronic chips based on the first substrate comprises at least one of an optical signal transmitting device, an optical amplifier device, an optical modulator, an optical detector, and a passive optical waveguide interconnect device, and the interlayer coupling structure of the optoelectronic chips is a coupling grating or a reflector composed of an inclined etched surface; The second layer of optoelectronic chips based on the second substrate includes at least one of a passive optical waveguide interconnect device, an optical modulator, and an optical signal receiver. The interlayer coupling structure of the optoelectronic chips is a coupling grating or a reflector composed of an inclined etched surface.

3. The heterogeneous integrated optoelectronic chip based on optically penetrating substrate channels according to claim 1, characterized in that: The first layer of optoelectronic chips and the second layer of optoelectronic chips are coupled back to back, the back surface of the first substrate and the back surface of the second substrate are in contact or bonded with each other, and the contact surface of one or both substrates is a smooth surface or coated with an optical antireflection film.

4. The heterogeneous integrated optoelectronic chip based on optically penetrating substrate channels according to claim 1, characterized in that: The third layer of optoelectronic chips is coupled face-on with the first layer of optoelectronic chips. The back surface of the third substrate of the third layer of optoelectronic chips contacts the front surface of the first layer of optoelectronic chips. The back surface of the third substrate is smooth or coated with an optical anti-reflection film.

5. The heterogeneous integrated optoelectronic chip based on optically penetrating substrate channels according to claim 1, characterized in that: The first substrate is InP, GaAs or a compound semiconductor material, and the second substrate is Si, SiO2, quartz or an organic substrate material.

6. The heterogeneous integrated optoelectronic chip based on optically penetrating substrate channels according to claim 1, characterized in that: The chirped collimating grating makes the light coupled to the optically penetrating substrate channel a beam of parallel light, and by optimizing the design of the grating etching depth and the gradual change of the duty cycle, a gradual change of the grating coupling coefficient is obtained, so that the light emitted into the optically penetrating substrate channel has a certain light field distribution, and the diffraction light field on the grating that decreases exponentially along the waveguide propagation direction is cut into a nearly Gaussian shape with a diameter as large as tens of microns, meeting the conditions of large alignment tolerance and high coupling efficiency.

7. The heterogeneous integrated optoelectronic chip based on optically penetrating substrate channels according to claim 6, characterized in that: A layer of metal high-reflection film is deposited on the upper surface of the chirped collimating grating as a metal reflector. The metal high-reflection film is at a certain distance from the grating, so that the light directly diffracted by the chirped collimating grating into the optically transparent substrate channel and the light diffracted above the grating and then reflected by the metal high-reflection film into the optically transparent substrate channel can be constructively coherent, making the light emitted into the optically transparent substrate channel the strongest.

8. The heterogeneous integrated optoelectronic chip based on optically penetrating substrate channels according to claim 1, characterized in that: The first interlayer coupling structure is an etched surface placed at a specific angle, so that light incident from the waveguide to the etched surface is totally reflected and penetrates the substrate.

9. The heterogeneous integrated optoelectronic chip based on optically penetrating substrate channels according to claim 1, characterized in that: The second interlayer coupling structure is a chirped focusing grating, which focuses the optical signal received from the optically penetrating substrate channel to the optical signal receiving point on the second layer of optoelectronic chip, and maximizes the receiving coupling efficiency by optimizing the grating etching depth and the gradual duty cycle.

10. The heterogeneous integrated optoelectronic chip based on optically penetrating substrate channels according to claim 9, characterized in that: A layer of metal high-reflection film is deposited on the surface of the chirped focusing grating cladding as a metal reflector. The metal high-reflection film is at a certain distance from the chirped focusing grating, so that the light directly diffracted from the optical penetration substrate channel through the chirped focusing grating to the optical signal receiving point and the light that penetrates the grating, is reflected by the metal high-reflection film, and then diffracted through the chirped focusing grating to the optical signal receiving point can be constructively coherent, making the light coupled to the optical signal receiving point the strongest.

Images