USB communication method and device

Abstract

This specification discloses a USB communication method and device. The USB communication method includes: an FPGA chip obtains an input clock signal, an indication signal and a direction signal sent by a USB chip, the indication signal is used to indicate the target data to be communicated, and the direction signal is used to indicate the data transmission direction of the target data; through a multi-mode clock manager MMCM set in the FPGA chip, the input clock signal is latched to obtain a global clock signal; based on the global clock signal, the input clock signal is latched to obtain latched data; according to the latched data, the global clock signal is compensated to obtain a target clock signal; and USB communication is performed with the USB chip according to the target clock signal, the indication signal and the direction signal. This solution implements the USB communication protocol based on FPGA and USB physical layer chip, reducing the complexity and production cost of USB communication hardware.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and more particularly to a USB communication method and device. Background Art

[0002] Universal Serial Bus (USB) is an external bus standard that aims to regulate the connection and communication between computers and external devices. It has the characteristics of plug-and-play, hot-swap, and high-speed data transmission. With the development of technology, the standard version is constantly updated to meet the growing demand for data transmission.

[0003] Currently, most USB communication protocols are implemented based on an additional central processing unit (CPU), which provides the protocol layer to users in the form of microprocessor firmware. Users only need to control the data interface to easily complete USB data communication.

[0004] Due to the hardware characteristics of the CPU, it is usually necessary to set up the external circuit of the microprocessor in the hardware device to achieve USB communication. The setting process of this hardware circuit is relatively complicated, the production cost is high, the flexibility of use is relatively low, and it is difficult to meet user needs.

[0005] Therefore, how to reduce the hardware complexity and production cost of USB communication is an issue that needs to be addressed urgently. Summary of the invention

[0006] This specification provides a USB communication method and device to partially solve the above problems existing in the prior art.

[0007] This manual adopts the following technical solutions:

[0008] This specification provides a USB communication method, wherein a universal serial bus USB chip and a field programmable gate array FPGA chip are deployed on a target device, and the target device communicates with a USB device through the FPGA chip and the USB chip, including:

[0009] The FPGA chip obtains an input clock signal, an indication signal and a direction signal sent by the USB chip, wherein the indication signal is used to indicate target data to be communicated, and the direction signal is used to indicate a data transmission direction of the target data;

[0010] The input clock signal is latched by a multi-mode clock manager MMCM provided in the FPGA chip to obtain a global clock signal;

[0011] Based on the global clock signal, latching the input clock signal to obtain latched data;

[0012] Compensating the global clock signal according to the latched data to obtain a target clock signal;

[0013] USB communication is performed with the USB chip according to the target clock signal, the indication signal and the direction signal.

[0014] Optionally, the USB chip includes: a universal serial bus physical layer USB PHY chip, the USB PHY chip is connected to the FPGA chip via a ULPI interface, and the ULPI interface is obtained by the USB PHY chip converting the USB standard interface of the USB PHY chip.

[0015] Optionally, the relative distance difference between the signal lines of the ULPI interface is less than a preset distance difference.

[0016] Optionally, the deviation between the delays of the global clock signal reaching various locations in the FPGA chip is less than a preset deviation.

[0017] Optionally, before compensating the global clock signal according to the latched data to obtain the target clock signal, the method further includes:

[0018] Determining whether the number of latches performed by the global clock signal on the input clock signal is greater than a preset number of latches;

[0019] Compensating the global clock signal according to the latched data specifically includes:

[0020] If the number of latching times of the input clock signal by the global clock signal is greater than the preset number of latching times, the global clock signal is compensated according to the latched data.

[0021] Optionally, the latched data includes a plurality of register values;

[0022] Compensating the global clock signal according to the latched data to obtain a target clock signal specifically includes:

[0023] If the proportion of the target register value in the latched data is less than a first preset proportion, the global clock signal is adjusted in the reverse direction.

[0024] Optionally, compensating the global clock signal according to the latched data to obtain a target clock signal specifically includes:

[0025] If the proportion of the target register value in the latched data is greater than a second preset proportion, the global clock signal is positively adjusted, wherein the second preset proportion is greater than the first preset proportion.

[0026] Optionally, compensating the global clock signal according to the latched data to obtain a target clock signal specifically includes:

[0027] If the proportion of the target register value in the latched data is greater than the first preset proportion and less than the second preset proportion, the global clock signal is used as the target clock signal.

[0028] This specification provides a USB communication device, including:

[0029] An acquisition module, used for acquiring an input clock signal, an indication signal and a direction signal sent by the USB chip, wherein the indication signal is used for indicating target data to be communicated, and the direction signal is used for indicating a data transmission direction of the target data;

[0030] A first latch module is used to latch the input clock signal through a multi-mode clock manager MMCM set in the FPGA chip to obtain a global clock signal;

[0031] A second latch module, configured to latch the input clock signal based on the global clock signal to obtain latched data;

[0032] A compensation module, used for compensating the global clock signal according to the latched data to obtain a target clock signal;

[0033] A communication module is used to perform USB communication with the USB chip according to the target clock signal, the indication signal and the direction signal.

[0034] This specification provides a computer-readable storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned USB communication method is implemented.

[0035] At least one of the above technical solutions adopted in this specification can achieve the following beneficial effects:

[0036] It can be seen from the above method that in the USB communication method provided in this specification, USB communication can be implemented based on FPGA chip. Compared with the current method of communicating through a microprocessor, the external circuit of the FPGA chip is simple and the overall cost is low. The protocol layer code can be changed to reduce the hardware complexity and production cost of USB communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of this specification and constitute a part of this specification. The illustrative embodiments and descriptions of this specification are used to explain this specification and do not constitute an improper limitation on this specification. In the drawings:

[0038] Figure 1 A flowchart of a USB communication method provided in this specification;

[0039] Figure 2 A circuit architecture diagram of USB communication provided in this manual;

[0040] Figure 3 A schematic diagram of the overall architecture of phase compensation provided in this specification;

[0041] Figure 4 A signal schematic diagram of phase compensation provided in this specification;

[0042] Figure 5 A schematic diagram of a phase compensation process provided in this specification;

[0043] Figure 6 This is a schematic diagram of a USB communication device provided in this manual. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of this specification more clear, the technical solutions of this specification will be clearly and completely described below in combination with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of this specification, not all of them. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0045] The technical solutions provided by the embodiments of this specification are described in detail below in conjunction with the accompanying drawings.

[0046] Figure 1 A flow chart of a USB communication method provided in this specification includes the following steps:

[0047] S101: The FPGA chip obtains an input clock signal, an indication signal and a direction signal sent by the USB chip, wherein the indication signal is used to indicate target data to be communicated, and the direction signal is used to indicate a data transmission direction of the target data.

[0048] At present, most USB communication protocols are implemented based on CPU processors. Some manufacturers provide a complete solution, providing the protocol layer to users in the form of microprocessor firmware. Users only need to control the data interface to complete USB data communication. This solution is simple to implement, but the hardware circuit is relatively complex, the cost is high when mass-produced, and users cannot modify the protocol layer code, so the flexibility of use is low.

[0049] Based on this, this specification provides a USB communication method, which is based on a field programmable gate array (FPGA) chip and uses only one USB physical layer chip to realize USB data communication. The complex protocol layer is implemented through FPGA firmware without the need for an additional microprocessor (CPU). The hardware circuit of this solution is extremely simple, low cost and highly flexible in design.

[0050] The USB chip and the FPGA chip are deployed on the target device, and the target device communicates with the USB device through the FPGA chip and the USB chip.

[0051] In this specification, USB chip may refer to USB Physical Layer (USBPHY) chip, target device may include output devices such as communication machine, computer, data acquisition device, image acquisition device, etc., USB device may refer to input device for communication with target device, and USB device is connected to target device through USB connection. For ease of understanding, this specification provides a circuit architecture diagram of USB communication, such as Figure 2 shown.

[0052] Figure 2 This is a circuit architecture diagram of USB communication provided in this manual.

[0053] Among them, IBUF is the input buffer inside the FPGA chip, OBUF is the output buffer inside the FPGA, and IOBUF is the input / output buffer inside the FPGA. TX FIFO is a buffer for storing data to be sent. RX FIFO is a buffer for storing received data.

[0054] The USB chip (USB PHY chip) can convert the USB standard interface (including VBUS / ID / TX / RX / GND) into a universal low pin count interface (ULPI) interface, whose interfaces include: ULPI_CLK60 / RESET / STP / NXT / DIR / DAT[7:0], so as to facilitate data transmission between the USB chip and the FPGA chip.

[0055] In the USB standard interface, the ID interface refers to a device or interface used to scan or read identity documents or other identification documents. TX stands for Transmit, and the TX interface is an external antenna interface, which means that this is where the signal is sent. RX stands for Receiver, which is the abbreviation of the serial communication receiving port. It is usually used to receive data transmitted by external devices, such as reading data from sensors. GND is the abbreviation of the ground terminal of the wire, representing the ground wire or the 0 wire. On a circuit diagram or circuit board, GND is the common terminal, and for the power supply, GND is usually the negative pole. It ensures that the current in the circuit can flow back to the power supply to form a complete circuit loop.

[0056] The USB chip is connected to the FPGA via the ULPI interface. The USB PHY chip provides the FPGA with a clock signal (ULPI_CLK60), an indication signal (ULPI_NXT), and a direction signal (ULPI_DIR). The indication signal is used to indicate the target data to be communicated, and the direction signal is used to indicate the data transmission direction of the target data, that is, whether the target data is transmitted from the USB chip to the FPGA chip or from the FPGA chip to the USB chip.

[0057] The FPGA chip provides a reset signal (ULPI_RESET) to the USB chip and a stop signal (ULPI_STP) to the USB chip. The data between the USB chip and the FPGA chip is transmitted through a bidirectional 8-bit data interface (ULPI_DAT[7:0]), and the transmission direction is determined by ULPI_DIR.

[0058] During USB communication, the FPGA chip can obtain the clock signal sent by the USB chip as the input clock signal, which can be expressed as ULPI_CLK60. At the same time, it can also obtain the indication signal and direction signal. Among them, the FPGA chip implements the protocol layer data packaging, parsing, ring card and other functions of the USB protocol through the internally deployed USB core, as well as the transmission synchronization, token, handshake and data packet sending and receiving, and obtaining device ID information in the protocol. The USB core interface is a UTMI interface, and the UTMI to ULPI module is also required for conversion to communicate with the USBPHY chip.

[0059] S102: The input clock signal is latched by the multi-mode clock manager MMCM provided in the FPGA chip to obtain a global clock signal.

[0060] In this specification, the ULPI interface for communication between the FPGA and the USB chip needs to complete bidirectional data transmission and alignment of multi-bit parallel data with the clock. A stable and efficient ULPI interface data transmission is the key.

[0061] The alignment of multi-bit parallel data in FPGA is generally achieved by using development tools to constrain the timing and position of logic. The implementation is highly complex and has poor stability, and is easily affected by the external environment (such as voltage, temperature, etc.). Therefore, this specification uses the phase adjustment function of the Mixed-Mode Clock Manager (MMCM) IP core inside the FPGA chip, combined with the position constraints of key registers, to achieve automatic real-time alignment of ULPI clock, data and global clock.

[0062] Specifically, the FPGA chip is provided with MMCM and a global clock buffer (Global Clock Buffer, BUFG). After the FPGA chip receives the input clock signal ULPI_CLK60 from the USB chip, ULPI_CLK60 will enter the MMCM for latching, and the output of the MMCM will reach each position in the FPGA chip through the BUFG, thereby obtaining the global clock signal (ULPI_CLK60_G).

[0063] Among them, the deviation between the delays of ULPI_CLK60_G reaching each position in the FPGA chip is less than the preset delay. In other words, the delay of ULPI_CLK60_G as a global clock reaching each position in the FPGA chip is almost the same, which can ensure its timing stability. The above preset delay can be set according to the actual situation, and this manual does not make specific restrictions on this.

[0064] S103: Based on the global clock signal, latch the input clock signal to obtain latched data.

[0065] S104: Compensating the global clock signal according to the latched data to obtain a target clock signal.

[0066] Because ULPI_CLK60_G and ULPI_CLK60 have a phase difference due to routing delay, and this phase difference will be different every time the firmware is compiled and powered on, and will also change with the changes in the FPGA chip power supply voltage and operating temperature, resulting in phase uncertainty between ULPI_CLK60_G and the ULPI chip input and output signals (ULPI_DIR / STP / NXT / DAT[7:0]). If the delay is large, ULPI_CLK60_G cannot guarantee that it can correctly latch the ULPI signal every time, causing USB connection failure.

[0067] Therefore, it is necessary to perform phase compensation on ULPI_CLK60_G to ensure that the global clock signal is synchronized with the input clock signal. For ease of understanding, this specification provides a schematic diagram of the overall architecture of phase compensation, such as Figure 3 shown.

[0068] Figure 3 A schematic diagram of the overall architecture of phase compensation provided in this specification.

[0069] Among them, for the hardware circuit of the FPGA chip, the relative distance difference of each signal line of the ULPI interface on the circuit board can be made smaller than the preset distance difference during the circuit design process. The preset distance difference can be 20 mil, thereby minimizing the phase difference between ULPI_CLK60_G and ULPI_CLK60 caused by routing reasons.

[0070] In addition, the first-level latch of the ULPI input and output signals (ULPI_DIR / STP / NXT / DAT[7:0]) latched by ULPI_CLK60_G can be placed in the FPGA's IO bank (IOB). The IOB is very close to the IO to ensure that its delay is small.

[0071] The FPGA chip can use the MMCM IP core set therein to lock ULPI_CLK60, and then output the global clock ULPI_CLK60_G. And the MMCM IP core enables the automatic output clock phase adjustment function. The interface signals of the MMCM output phase automatic adjustment function include psclk, psen, psincdec and psdone. Among them, psclk is the phase adjustment reference clock; psen is the phase adjustment enable, and each time it is set high, a phase adjustment is performed; psincdec is the phase adjustment direction indication signal, a low level is a reverse phase adjustment, and a high level is a forward phase adjustment; psdone is the phase adjustment completion flag.

[0072] Furthermore, the FPGA can use ULPI_CLK60_G to latch ULPI_CLK60 and obtain the latched data. This register is also stored in the IOB to ensure that the delay of ULPI_CLK60 is small.

[0073] In this specification, the latch data may include the latch times and the latch value of ULPI_CLK60_G latching ULPI_CLK60, and then ULPI_CLK60_G is compensated based on the latch data to obtain a compensated target clock signal. For ease of understanding, this specification provides a signal schematic diagram of phase compensation, such as Figure 4 shown.

[0074] Figure 4 A signal diagram of phase compensation provided in this specification.

[0075] Among them, a preset latching number (such as 2000 times) can be set in advance. Before performing phase compensation on ULPI_CLK60_G, it can be determined whether the latching number of the global clock signal latching the input clock signal is greater than the preset latching number. If so, phase compensation can be performed.

[0076] Specifically, if the latched values ​​are almost all 0, it proves that ULPI_CLK60_G is delayed by half a cycle compared to ULPI_CLK60, and then the phase adjustment unit is started to adjust ULPI_CLK60_G in a positive direction (psincdec=1, psen is set high for one cycle).

[0077] If the latched values ​​are almost all 1, it proves that ULPI_CLK60_G is ahead of ULPI_CLK60 by half a cycle, and then the phase adjustment unit is started to adjust ULPI_CLK60_G in the opposite direction (psincdec=0, psen is set high for one cycle).

[0078] Theoretically, if the final ULPI_CLK60 and ULPI_CLK60_G phases are synchronized, then due to the metastable state of the register, the latched register value has a probability of about 50% being '0' or '1'. Therefore, the present invention sets the confidence interval to [800-1200], that is, when the number of '0' occurrences is less than 800 (<40%), the reverse phase adjustment is started; conversely, if the number of '0' occurrences is greater than 1200 (>60%), the forward phase adjustment is started; when the number of '0' outputs is within the confidence interval (>40%, <60%), it proves that the phases of ULPI_CLK60 and ULPI_CLK60_G are basically consistent, and the phase adjustment is completed;

[0079] For ease of understanding, this specification provides a flow chart of phase compensation, such as Figure 5 shown.

[0080] Figure 5 The following is a flow chart of a phase compensation process provided in this specification.

[0081] Among them, the register value "0" can be used as the target register value. If the proportion of the target register value in the latched data is less than the first preset proportion, ULPI_CLK60_G is adjusted in the reverse direction. If the proportion of the target register value in the latched data is greater than the second preset proportion, ULPI_CLK60_G is adjusted in the forward direction. If the proportion of the target register value in the latched data is greater than the first preset proportion and less than the second preset proportion, it means that the phase difference of ULPI_CLK60_G is low. At this time, ULPI_CLK60_G can be adjusted and used as the target clock signal. Among them, the above-mentioned first preset proportion can be set to 40%, and the second preset proportion can be set to 60%.

[0082] Of course, the register value "1" can also be used as the target register value for adjustment. The adjustment method is the same as when the register value "0" is used as the target register value, but the adjustment direction is opposite. This manual will not go into details about this.

[0083] S105: Perform USB communication with the USB chip according to the target clock signal, the indication signal and the direction signal.

[0084] After completing the phase compensation of ULPI_CLK60_G, the target clock signal can be obtained. At this time, the phase adjustment is completed, and the FPGA can output the USB core reset signal to start the USB core to enter the synchronization state, and the USB connection is officially established.

[0085] The FPGA chip communicates with the USB chip under the target clock signal, determines the data to be communicated based on the indication signal, and determines the data transmission direction based on the direction information, thereby realizing data transmission between the target device and the USB device.

[0086] During this process, FPGA still monitors the synchronization status of ULPI_CLK60_G and ULPI_CLK60 in real time, and makes synchronization adjustments at any time according to the latched value to ensure that the synchronization status is not affected by changes in the external environment.

[0087] From the above method, it can be seen that this solution only uses one USB physical layer chip to realize USB data communication. The complex protocol layer is implemented through FPGA firmware without the need for an additional microprocessor. The hardware circuit of this solution is extremely simple, low cost and high design flexibility.

[0088] Moreover, this solution is not affected by changes in external conditions (voltage, temperature, etc.), and can ensure stable transmission of the ULPI interface.

[0089] In addition, this solution was tested on Kintex-7 series FPGA and USB3320 chip. If the phase automatic compensation technology proposed in this invention is not adopted, the USB connection sometimes fails to be established. However, with the phase automatic compensation technology proposed in this invention, the USB connection can be guaranteed to be successfully established in all operations such as repeated firmware compilation, system power on and off, and reset for more than 48 hours.

[0090] The above are one or more USB communication methods implemented in this specification. Based on the same idea, this specification also provides corresponding USB communication devices, such as Figure 6 shown.

[0091] Figure 6 A schematic diagram of a USB communication device provided for this specification includes:

[0092] An acquisition module 601 is used to acquire an input clock signal, an indication signal and a direction signal sent by a USB chip, wherein the indication signal is used to indicate target data to be communicated, and the direction signal is used to indicate a data transmission direction of the target data;

[0093] A first latch module 602 is used to latch the input clock signal through a multi-mode clock manager MMCM provided in the FPGA chip to obtain a global clock signal;

[0094] A second latch module 603, configured to latch the input clock signal based on the global clock signal to obtain latched data;

[0095] A compensation module 604, configured to compensate the global clock signal according to the latched data to obtain a target clock signal;

[0096] The communication module 605 is used to perform USB communication with the USB chip according to the target clock signal, the indication signal and the direction signal.

[0097] Optionally, the USB chip includes: a universal serial bus physical layer USB PHY chip, the USB PHY chip is connected to the FPGA chip via a ULPI interface, and the ULPI interface is obtained by the USB PHY chip converting the USB standard interface of the USB PHY chip.

[0098] Optionally, the relative distance difference between the signal lines of the ULPI interface is less than a preset distance difference.

[0099] Optionally, the deviation between the delays of the global clock signal reaching various locations in the FPGA chip is less than a preset deviation.

[0100] Optionally, before compensating the global clock signal according to the latched data to obtain the target clock signal, the compensation module 604 is further used to determine whether the number of latches of the input clock signal by the global clock signal is greater than a preset number of latches;

[0101] The compensation module 604 is specifically configured to compensate the global clock signal according to the latch data if the number of latches performed by the global clock signal to latch the input clock signal is greater than the preset number of latches.

[0102] Optionally, the latched data includes a plurality of register values;

[0103] The compensation module 604 is specifically configured to reversely adjust the global clock signal if a proportion of the target register value in the latched data is less than a first preset proportion.

[0104] Optionally, the compensation module 604 is specifically used to positively adjust the global clock signal if a proportion of the target register value in the latched data is greater than a second preset proportion, wherein the second preset proportion is greater than the first preset proportion.

[0105] Optionally, the compensation module 604 is specifically configured to use the global clock signal as the target clock signal if a proportion of the target register value in the latched data is greater than the first preset proportion and less than the second preset proportion.

[0106] This specification also provides a computer-readable storage medium, which stores a computer program, which can be used to execute the above Figure 1 A USB communication method is provided.

[0107] For the improvement of a technology, it can be clearly distinguished whether it is a hardware improvement (for example, improvement of the circuit structure of diodes, transistors, switches, etc.) or a software improvement (improvement of the method flow). However, with the development of technology, many improvements of the method flow today can be regarded as direct improvements of the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that the improvement of a method flow cannot be implemented with a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming themselves, without having to ask chip manufacturers to design and make dedicated integrated circuit chips. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0108] The controller can be implemented in any appropriate manner, for example, the controller can take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) that can be executed by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in a purely computer-readable program code manner, the controller can be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, this controller can be considered as a hardware component, and the devices included therein for implementing various functions can also be regarded as structures within the hardware component. Or even, the devices for implementing various functions can be regarded as both software modules for implementing the method and structures within the hardware component.

[0109] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0110] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0111] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0112] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0113] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0114] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0115] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0116] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0117] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0118] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0119] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0120] This specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0121] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0122] The above description is only an embodiment of the present specification and is not intended to limit the present specification. For those skilled in the art, the present specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification shall be included in the scope of the claims of the present specification.

Claims

1. A USB communication method, characterized in that: A universal serial bus USB chip and a field programmable gate array FPGA chip are deployed on a target device, and the target device communicates with a USB device through the FPGA chip and the USB chip, including: The FPGA chip obtains an input clock signal, an indication signal and a direction signal sent by the USB chip, wherein the indication signal is used to indicate target data to be communicated, and the direction signal is used to indicate a data transmission direction of the target data; The input clock signal is latched by a multi-mode clock manager MMCM provided in the FPGA chip to obtain a global clock signal; Based on the global clock signal, latching the input clock signal to obtain latched data; According to the latched data, the global clock signal is compensated to obtain a target clock signal; wherein the latched data includes a plurality of register values; if the proportion of the target register value in the latched data is less than a first preset proportion, the global clock signal is reversely adjusted; if the proportion of the target register value in the latched data is greater than a second preset proportion, the global clock signal is forwardly adjusted; if the proportion of the target register value in the latched data is greater than the first preset proportion and less than the second preset proportion, the global clock signal is used as the target clock signal; wherein the second preset proportion is greater than the first preset proportion; USB communication is performed with the USB chip according to the target clock signal, the indication signal and the direction signal.

2. The method according to claim 1, characterized in that The USB chip comprises: a universal serial bus physical layer USBPHY chip, the USB PHY chip is connected to the FPGA chip via a ULPI interface, and the ULPI interface is obtained by converting the USB standard interface of the USB PHY chip by the USBPHY chip.

3. The method according to claim 2, characterized in that The relative distance difference between the signal lines of the ULPI interface is less than the preset distance difference.

4. The method according to claim 1, characterized in that The deviation between the delays of the global clock signal reaching various locations in the FPGA chip is less than a preset deviation.

5. The method according to claim 1, characterized in that Before compensating the global clock signal according to the latched data to obtain the target clock signal, the method further includes: Determining whether the number of latches performed by the global clock signal on the input clock signal is greater than a preset number of latches; Compensating the global clock signal according to the latched data specifically includes: If the number of latching times of the input clock signal by the global clock signal is greater than the preset number of latching times, the global clock signal is compensated according to the latched data.

6. A USB communication device, characterized in that: include: An acquisition module, used for acquiring an input clock signal, an indication signal and a direction signal sent by the USB chip, wherein the indication signal is used for indicating target data to be communicated, and the direction signal is used for indicating a data transmission direction of the target data; A first latch module is used to latch the input clock signal through a multi-mode clock manager MMCM set in the FPGA chip to obtain a global clock signal; A second latch module, configured to latch the input clock signal based on the global clock signal to obtain latched data; A compensation module, configured to compensate the global clock signal according to the latched data to obtain a target clock signal; wherein the latched data includes a plurality of register values; if the proportion of the target register value in the latched data is less than a first preset proportion, the global clock signal is reversely adjusted; if the proportion of the target register value in the latched data is greater than a second preset proportion, the global clock signal is forwardly adjusted; if the proportion of the target register value in the latched data is greater than the first preset proportion and less than the second preset proportion, the global clock signal is used as the target clock signal; wherein the second preset proportion is greater than the first preset proportion; A communication module is used to perform USB communication with the USB chip according to the target clock signal, the indication signal and the direction signal.

7. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

Images