Electronic packaging and method of manufacturing the same

Abstract

The present invention provides an electronic package and a method for manufacturing the same. The electronic package includes an external structure formed on a first side of a circuit structure, and at least one circuit component electrically connected to the circuit structure and at least one electronic component electrically connected to the circuit structure are arranged on a second side of the circuit structure, and the circuit component and the electronic component are coated with a coating layer, wherein the CTE of the circuit component and the coating layer are both greater than the CTE of the circuit structure, and the CTE of the circuit structure is greater than the CTE of the external structure, so as to avoid excessive difference in CTE between the two sides of the circuit structure, thereby avoiding the problem of warping of the electronic package.

Description

Technical Field

[0001] The invention relates to a semiconductor packaging process, and in particular to an electronic packaging component capable of preventing warping during the process, a packaging substrate and a manufacturing method thereof. Background Art

[0002] With the vigorous development of the electronics industry, electronic products tend to be thinner, lighter and smaller in shape, and their functions are moving towards high performance, high functionality and high speed.

[0003] There are many technologies currently used in the field of chip packaging, such as chip scale package (CSP), direct chip attached (DCA) or multi-chip module (MCM).

[0004] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a semiconductor package 1 using conventional wafer-level packaging technology. Figure 1 As shown, the semiconductor package 1 includes: a coating layer 15, a semiconductor chip 11 embedded in the coating layer 15, a plurality of conductive pillars 13 embedded in the coating layer 15, and a wiring structure 10 arranged on the coating layer 15, and the wiring structure 10 electrically connects the semiconductor chip 11 and the conductive pillars 13, and forms a plurality of solder balls 19 on the lower side of the conductive pillars 13 for connecting to a circuit board (not shown), wherein the upper side of the wiring structure 10 can be configured with a packaging module as required, which includes a semiconductor chip 16 and a packaging layer 18 covering the semiconductor chip 16.

[0005] In the conventional process of the semiconductor package 1 , the conductive pillar 13 needs to penetrate the cladding layer 15 , and thus a through hole needs to be formed through the cladding layer 15 by laser, and then a copper pillar needs to be electroplated in the through hole.

[0006] However, the encapsulation layer 15 needs to encapsulate the semiconductor chip 11, so the encapsulation layer 15 needs to have a certain thickness, so that the perforation required for the conductive column 13 needs to have a certain depth. Therefore, the perforation under laser burning will produce a wider perforation, resulting in a lower depth-to-width ratio of the conductive column 13, and thus a high-density conductive column 13 cannot be arranged.

[0007] Furthermore, the insulating layer of the wiring structure 10 adopts Ajinomoto build-up film (ABF), which causes the CTE difference between the wiring structure 10 and the coating layer 15 to vary too much. Therefore, during the process, when the semiconductor package 1 undergoes multiple processes with changing ambient temperatures, the semiconductor package 1 is prone to deformation and warping due to the insufficient strength of the wiring structure 10, which in turn causes the solder ball 19 to detach or break.

[0008] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the invention

[0009] In view of the above-mentioned defects of the prior art, an object of the present invention is to provide an electronic package and a method for manufacturing the same, which can at least partially solve the problems in the art.

[0010] The electronic package of the present invention comprises: a circuit structure having a first side and a second side opposite to each other, and the circuit structure comprises at least one first dielectric layer and a first circuit layer arranged on the first dielectric layer; an external structure arranged on the first side of the circuit structure, and the external structure comprises a second dielectric layer formed on the first dielectric layer and a conductor embedded in the second dielectric layer and electrically connected to the first circuit layer, and the thermal expansion coefficient of the first dielectric layer is greater than the thermal expansion coefficient of the second dielectric layer; a circuit component arranged on the second side of the circuit structure to electrically connect the first circuit layer , wherein the circuit component includes an insulating film body having a plurality of through holes and a conductive layer formed in the through holes, so that the conductive layer contacts the first circuit layer to electrically connect the first circuit layer, and the thermal expansion coefficient of the insulating film body is greater than the thermal expansion coefficient of the first dielectric layer; an electronic component, which is arranged on the second side of the circuit structure to electrically connect the first circuit layer; and a covering layer, which is arranged on the second side of the circuit structure to cover the circuit component and the electronic component, and the conductive layer is exposed on the covering layer, wherein the thermal expansion coefficient of the covering layer is greater than the thermal expansion coefficient of the first dielectric layer.

[0011] The present invention also provides a method for manufacturing an electronic package, comprising: providing a coreless circuit structure, wherein the circuit structure has a first side and a second side opposite to each other, and the circuit structure includes at least one first dielectric layer and a first circuit layer disposed on the first dielectric layer; forming an external structure on the first side of the circuit structure, and the external structure includes a second dielectric layer formed on the first dielectric layer and a conductor embedded in the second dielectric layer and electrically connected to the first circuit layer, wherein the thermal expansion coefficient of the first dielectric layer is greater than the thermal expansion coefficient of the second dielectric layer; arranging a circuit component on the second side of the circuit structure so that the circuit component is electrically connected The circuit structure is connected to the first circuit layer, wherein the circuit component includes an insulating film body having a plurality of through holes and a conductive layer formed in the through holes, so that the conductive layer contacts the first circuit layer to electrically connect the first circuit layer, and the thermal expansion coefficient of the insulating film body is greater than the thermal expansion coefficient of the first dielectric layer; an electronic component is arranged on the second side of the circuit structure, so that the electronic component is electrically connected to the first circuit layer; and a covering layer is formed on the second side of the circuit structure, so that the covering layer covers the circuit component and the electronic component, and the conductive layer is exposed from the covering layer, wherein the thermal expansion coefficient of the covering layer is greater than the thermal expansion coefficient of the first dielectric layer.

[0012] In the aforementioned electronic package and its manufacturing method, the thermal expansion coefficient of the insulating film body is greater than the thermal expansion coefficient of the coating layer.

[0013] In the aforementioned electronic package and its manufacturing method, a conductive element electrically connecting the conductive layer and the first circuit layer is disposed in the through hole.

[0014] The aforementioned electronic package and its manufacturing method also include forming a second circuit layer on the cladding layer so that the second circuit layer is electrically connected to the conductive layer.

[0015] The aforementioned electronic package and its manufacturing method also include forming a second circuit layer on the second dielectric layer so that the second circuit layer is electrically connected to the conductor.

[0016] As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly rely on the configuration of the circuit component to meet the high aspect ratio requirement of the conductive layer in the coating layer. Therefore, compared with the prior art, the manufacturing method of the present invention does not need to perform drilling operations on the coating layer, and the required conductive path can be obtained through the conductive layer, thereby being able to arrange high-density through-holes.

[0017] Furthermore, the CTE of each layer of the electronic package is configured to increase or decrease gradually, that is, the second dielectric layer with the smallest CTE is configured on the first side of the circuit structure, and the insulating film body with the largest CTE is configured on the second side of the circuit structure, so as to avoid excessive difference in CTE between the first side and the second side of the circuit structure. Therefore, compared with the prior art, when the electronic package undergoes multiple processes of ambient temperature changes, the insulating film body can serve as a stress enhancement structure to effectively avoid deformation and warping of the electronic package, thereby avoiding problems such as detachment or breakage of the solder ball. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The cross-sectional view is a schematic diagram of a conventional method for manufacturing a semiconductor package.

[0019] FIG. 2A to FIG. 2H It is a cross-sectional schematic diagram of the method for manufacturing the electronic package of the present invention.

[0020] Figure 3 for Figure 2H A cross-sectional schematic diagram of the subsequent process.

[0021] The reference numerals are as follows:

[0022] 1 Semiconductor Package

[0023] 10 Wiring Structure

[0024] 11,16,31,32 semiconductor chips

[0025] 13 Conductive pillars

[0026] 15,25 cladding layer

[0027] 18,33 Encapsulation Layer

[0028] 19,29 solder balls

[0029] 2 Electronic packaging

[0030] 2a Package substrate

[0031] 2b Line Components

[0032] 20 Electronic components

[0033] 20a Active surface

[0034] 20b Non-active surface

[0035] 200 Electrode Pads

[0036] 201 Conductive bump

[0037] 202 Primer

[0038] 21 Line structure

[0039] 21a First side

[0040] 21b Second side

[0041] 211 First circuit layer

[0042] 212 first dielectric layer

[0043] 22 Insulation film

[0044] 220 Piercing

[0045] 23 Conductive layer

[0046] 24 External structure

[0047] 240 Second dielectric layer

[0048] 241 Conductor

[0049] 26 Second circuit layer

[0050] 260 Conductive blind vias

[0051] 27 Conductive element

[0052] 28 Insulation protection layer

[0053] 280,380 openings

[0054] 3 Encapsulation Module

[0055] 30 Carrier substrate

[0056] 300 wiring layers

[0057] 310,320 wire

[0058] 8 Support

[0059] 9 Bearing

[0060] 90 plate body

[0061] 91 seed layer

[0062] 92 Metal Layer

[0063] D Width

[0064] H1,H2 height DETAILED DESCRIPTION

[0065] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0066] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be produced by the present invention, should still fall within the scope of the technical contents disclosed in the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0067] FIG. 2A to FIG. 2H It is a cross-sectional schematic diagram of a method for manufacturing an electronic package 2 of the present invention.

[0068] like Figure 2A As shown, a carrier 9 is provided to symmetrically form a circuit structure 21 on two opposite sides of the carrier 9 .

[0069] In this embodiment, the carrier 9 is a temporary carrier, which may be a plate having metal layers on opposite sides, such as a copper foil substrate. The surface of the plate 90 has a metal layer 92 , and a seed layer 91 is formed on the metal layer 92 .

[0070] Furthermore, the circuit structure 21 includes a plurality of first dielectric layers 212 and a plurality of first circuit layers 211 formed on each of the first dielectric layers 212, so that a portion of the first circuit layer 211 of the circuit structure 21 is exposed on the first dielectric layer 212 of the second side 21b. For example, the first circuit layer 211 adopts a circuit redistribution layer (RDL) specification, and the first dielectric layer 212 is a dielectric material of Ajinomoto build-up film (ABF), and its coefficient of thermal expansion (CTE) is 13 to 17 ppm / °C.

[0071] In addition, each of the circuit structures 21 is coreless and defines a first side 21 a and a second side 21 b opposite to each other, and the circuit structure 21 is bonded to the seed layer 91 via the first side 21 a .

[0072] In addition, the first circuit layer 211 is manufactured by electroplating metal (such as copper) or other methods using a build-up process, and its line width / line spacing (L / S) is about 10 / 10 microns (um). For example, the innermost first circuit layer 211 is formed by electroplating the seed layer 91. It should be understood that by using the build-up process, the number of layers of the first dielectric layer 212 of the plurality of circuit structures 21 can be designed according to the needs to manufacture the required number of first circuit layers 211.

[0073] like Figure 2B As shown, the board 90 and the metal layer 92 thereon are removed to retain the seed layer 91 on the first side 21 a of the circuit structure 21 .

[0074] like Figure 2C As shown, a support member 8 is provided to symmetrically combine the circuit structure 21 on two opposite sides of the support member 8, so that the seed layer 91 is exposed. Next, the seed layer 91 is removed to expose the first side 21a of the circuit structure 21.

[0075] In this embodiment, the support member 8 is a thermal release film, and the second side 21b of the circuit structure 21 is pressed onto the support member 8. For example, the first circuit layer 211 of the second side 21b of the circuit structure 21 is embedded in the support member 8.

[0076] like Figure 2D As shown, an external structure 24 is formed on the first side 21 a of the circuit structure 21 to serve as the packaging substrate 2 a.

[0077] In this embodiment, the external structure 24 includes a second dielectric layer 240 formed on the first dielectric layer 212 and a conductor 241 combined with the second dielectric layer 240, so that the conductor 241 is electrically connected to the first circuit layer 211. For example, the external structure 24 is manufactured by a patterning process, so that a plurality of openings are formed in the second dielectric layer 240 by exposure and development, and then the conductor 241 is electroplated in the plurality of openings, so that the conductor 241 can be a copper column of RDL specification and embedded in the second dielectric layer 240, so that the surface of the conductor 241 is flush with or lower than the surface of the second dielectric layer 240.

[0078] Furthermore, the second dielectric layer 240 is formed of a material such as polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials. For example, the second dielectric layer 240 is PP material, and its CTE is 10ppm / °C.

[0079] like Figure 2EAs shown, the support member 8 is heated to separate the support member 8 from the packaging substrate 2a.

[0080] In this embodiment, a pyrolytic film is used as the support member 8 , and the circuit structure 21 is respectively disposed on two opposite sides of the support member 8 , so as to facilitate mass production.

[0081] like Figure 2F As shown, at least one circuit component 2 b is disposed on a portion of the surface of the second side 21 b of the circuit structure 21 , so that the circuit component 2 b is electrically connected to the first circuit layer 211 .

[0082] In this embodiment, the circuit component 2b includes an insulating film body 22 having a plurality of through-holes 220 and a conductive layer 23 formed in the through-holes 220, so that the conductive layer 23 contacts the first circuit layer 211 to electrically connect the first circuit layer 211. For example, the insulating film body 22 is made of a dielectric material such as PI material, and a plurality of PI films are stacked on top of each other, and a plurality of through-holes 220 are formed by drilling, and then copper material is electroplated on the wall surface of the through-hole 220 to serve as the conductive layer 23, so as to complete the circuit component 2b.

[0083] Furthermore, the circuit component 2 b is first manufactured, and then the circuit component 2 b is bonded to the first dielectric layer 212 , so that a portion of the surface of the first circuit layer 211 is exposed to the through hole 220 .

[0084] In addition, the material forming the second dielectric layer 240 is different from the material forming the insulating film body 22. For example, the insulating film body 22 is a PI material, and its CTE is 40 ppm / °C.

[0085] like Figure 2G As shown, at least one electronic component 20 is placed on a partial surface of the second side 21b of the circuit structure 21, and then a coating layer 25 is formed on the second side 21b of the circuit structure 21, so that the coating layer 25 covers the circuit component 2b and the electronic component 20, and the conductive layer 23 is exposed on the coating layer 25.

[0086] The electronic component 20 is an active component, a passive component or a combination of the two, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor or an inductor.

[0087] In this embodiment, the electronic component 20 is a semiconductor chip having an active surface 20a and an inactive surface 20b opposite to each other. The active surface 20a has a plurality of electrode pads 200, so that the electronic component 20 uses a flip-chip method with its active surface 20a to electrically connect the electrode pads 200 and the first circuit layer 211 through a plurality of conductive bumps 201 such as solder material (solder paste or solder balls), and the plurality of conductive bumps 201 can be coated with a primer 202 as required.

[0088] Furthermore, a single conductive element 27 such as solder material (solder paste or solder ball) may also be disposed in the through hole 220, so that the conductive element 27 contacts the first circuit layer 211 and the conductive layer 23, so that the conductive element 27 serves as a solder column with a relatively low height (i.e., lower than the through hole 220). For example, the conductive element 27 in a solder ball state may be placed on the first circuit layer 211 in the through hole 220, and then the conductive bump 201 and the conductive element 27 may be reflowed, so that the conductive element 27 in a reflowed state contacts the conductive layer 23, wherein the width D of the through hole 220 is 35 microns, which is larger than the ball diameter of the conductive element 27 in a solder ball state (e.g., 25 microns), so as to facilitate the placement of the conductive element 27 in a solder ball state.

[0089] In addition, a height H1 of the first dielectric layer 212 of the circuit component 2b relative to the second side 21b of the circuit structure 21 is higher than a height H2 of the first dielectric layer 212 of the electronic component 20 relative to the second side 21b of the circuit structure 21, so that the circuit component 2b has a high aspect ratio to meet the high aspect ratio requirement of the conductive layer 23 in the encapsulation layer 25.

[0090] The coating layer 25 is an insulating material, such as polyimide (PI), dry film, epoxy resin packaging colloid or packaging material (molding compound), which can be formed on the second side 21b of the circuit structure 21 by lamination or molding. For example, the coating layer 25 is epoxy resin packaging material (EMC), and its CTE is 10-25ppm / ℃.

[0091] In this embodiment, a part of the material of the coating layer 25 can be removed by a flattening process, such as etching or grinding, so that the upper surface of the coating layer 25 is flush with the surface of the circuit component 2b (or the insulating film body 22). For example, the coating layer 25 is filled into the through hole 220 to cover the conductive element 27, and the coating layer 25 covers the inactive surface 20b of the electronic component 20, so that the coating layer 25 is not exposed to the outside of the electronic component 20.

[0092] like Figure 2H As shown, a second circuit layer 26 is formed on the cladding layer 25 and the insulating film 22 , so that the second circuit layer 26 is electrically connected to the conductive layer 23 , so as to form the electronic package 2 .

[0093] The second circuit layer 26 extends into the cladding layer 25 to form a conductive blind hole 260 , so that the conductive blind hole 260 contacts the inactive surface 20 b of the electronic component 20 for grounding or heat dissipation of the electronic component 20 .

[0094] In this embodiment, an insulating protective layer 28 such as a solder mask may be formed on the cladding layer 25 and the insulating film 22. Figure 3 As shown, the insulating protective layer 28 has a plurality of openings 280, 380 exposing the second circuit layer 26, so as to form a plurality of solder balls 29 such as solder balls on the second circuit layer 26 in a portion of the openings 280, so as to connect another package module 3. For example, a portion of the openings 380 of the insulating protective layer 28 is used as a heat dissipation hole to correspond to the non-active surface 20b of the electronic component 20.

[0095] Furthermore, the packaging module 3 includes a carrier substrate 30 having a wiring layer 300, a plurality of semiconductor chips 31, 32 disposed on the carrier substrate 30 and stacked on each other, and a packaging layer 33 covering the plurality of semiconductor chips 31, 32, and the semiconductor chips 31, 32 are electrically connected to the wiring layer 300. For example, the plurality of semiconductor chips 31, 32 are electrically connected to the wiring layer 300 by a plurality of wires 310, 320 in a wire bonding manner. It should be understood that there are many embodiments of the packaging module 3, and they are not limited to the above.

[0096] In addition, the second circuit layer 26 can also be formed on the second dielectric layer 240 of the external structure 24 as required, so that the second circuit layer 26 is electrically connected to the conductor 241, and an insulating protective layer 28 such as a solder mask can be formed on the external structure 24 and the second circuit layer 26, so that the opening 280 of the insulating protective layer 28 exposes the second circuit layer 26 to combine multiple solder balls 29 for the electronic package 2 to be connected to a circuit board (not shown).

[0097] Therefore, the manufacturing method of the present invention mainly relies on the manufacturing method of the circuit component 2b, such as stacking multiple PI films and forming the conductive layer 23, to meet the high aspect ratio requirement of the conductive layer 23 in the coating layer 25. Therefore, compared with the prior art, the manufacturing method of the present invention does not need to perform drilling operations on the coating layer 25, and can obtain the required conductive path through the conductive layer 23, thereby arranging a high-density through-hole 220.

[0098] Furthermore, the insulating film body 22 of the circuit component 2b is made of a material with a very high glass transition temperature (Tg), such as PP material, to ensure that the circuit component 2b has the required thermal resistance.

[0099] In addition, the electronic package 2 adopts a coreless type by means of the circuit structure 21, so as to obtain a thinner package substrate 2a.

[0100] In addition, by configuring the CTE of each layer of the electronic package to increase or decrease gradually, that is, the CTE (second highest) of the encapsulation layer 25 (EMC), the CTE (second smallest) of the first dielectric layer 212 (ABF), the CTE (smallest) of the second dielectric layer 240 (PP) and the CTE (largest) of the insulating film 22 (PI), it is possible to avoid excessive changes in the CTE difference between the first side 21a and the second side 21b of the circuit structure 21. Therefore, compared with the prior art, when the electronic package 2 undergoes multiple processes of ambient temperature changes, the insulating film 22 can serve as a stress enhancement structure to effectively avoid deformation and warping of the electronic package 2, thereby avoiding problems such as detachment or breakage of the solder ball 29.

[0101] The present invention also provides an electronic package 2 , comprising: a circuit structure 21 , an external structure 24 , at least one circuit component 2 b , at least one electronic element 20 and a coating layer 25 .

[0102] The circuit structure 21 has a first side 21 a and a second side 21 b opposite to each other, wherein the circuit structure 21 includes at least a first dielectric layer 212 and a first circuit layer 211 disposed on the first dielectric layer 212 .

[0103] The external structure 24 is disposed on the first side 21a of the circuit structure 21, and the external structure 24 includes a second dielectric layer 240 formed on the first dielectric layer 212 and a conductor 241 embedded in the second dielectric layer 240 and electrically connected to the first circuit layer 211, and the thermal expansion coefficient of the first dielectric layer 212 is greater than the thermal expansion coefficient of the second dielectric layer 240.

[0104] The circuit component 2b is arranged on the second side 21b of the circuit structure 21 to electrically connect the first circuit layer 211, wherein the circuit component 2b includes an insulating film body 22 having a plurality of through-holes 220 and a conductive layer 23 formed in the through-holes 220, so that the conductive layer 23 contacts the first circuit layer 211 to electrically connect the first circuit layer 211, and the thermal expansion coefficient of the insulating film body 22 is greater than the thermal expansion coefficient of the first dielectric layer 212.

[0105] The electronic component 20 is disposed on the second side 21 b of the circuit structure 21 to be electrically connected to the first circuit layer 211 .

[0106] The coating layer 25 is disposed on the second side 21 b of the circuit structure 21 to cover the circuit assembly 2 b and the electronic component 20 , and the conductive layer 23 is exposed from the coating layer 25 , wherein the thermal expansion coefficient of the coating layer 25 is greater than the thermal expansion coefficient of the first dielectric layer 212 .

[0107] In one embodiment, the thermal expansion coefficient of the insulating film 22 is greater than the thermal expansion coefficient of the coating layer 25 .

[0108] In one embodiment, a conductive element 27 electrically connecting the conductive layer 23 and the first circuit layer 211 is disposed in the through hole 220 .

[0109] In one embodiment, the electronic package 2 further includes a second circuit layer 26 formed on the covering layer 25 and electrically connected to the conductive layer 23 .

[0110] In one embodiment, the electronic package 2 further includes a second circuit layer 26 formed on the second dielectric layer 240 and electrically connected to the conductor 241 .

[0111] In summary, the electronic package and its manufacturing method of the present invention, by configuring the circuit component, can meet the high aspect ratio requirement of the conductive layer in the coating layer. Therefore, the manufacturing method of the present invention does not need to perform drilling operations on the coating layer, and can obtain the required conductive path through the conductive layer, thereby being able to arrange high-density through-holes.

[0112] Furthermore, the CTE of each layer of the electronic package is configured to increase or decrease gradually, that is, the second dielectric layer with the smallest CTE is configured on the first side of the circuit structure, and the insulating film body with the largest CTE is configured on the second side of the circuit structure, so as to avoid excessive difference in CTE between the first side and the second side of the circuit structure. Therefore, compared with the prior art, when the electronic package undergoes multiple processes of ambient temperature changes, the insulating film body can serve as a stress enhancement structure to effectively avoid deformation and warping of the electronic package.

[0113] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. An electronic package, comprising: A circuit structure having a first side and a second side opposite to each other, and the circuit structure comprises at least a first dielectric layer and a first circuit layer disposed on the first dielectric layer; An external structure is disposed on the first side of the circuit structure, and the external structure includes a second dielectric layer formed on the first dielectric layer and a conductor embedded in the second dielectric layer and electrically connected to the first circuit layer, and the thermal expansion coefficient of the first dielectric layer is greater than the thermal expansion coefficient of the second dielectric layer; A circuit component is disposed on the second side of the circuit structure to electrically connect the first circuit layer, wherein the circuit component comprises an insulating film having a plurality of through holes and a conductive layer formed on the wall surface of the through holes, so that the conductive layer contacts the first circuit layer to electrically connect the first circuit layer, and the thermal expansion coefficient of the insulating film is greater than the thermal expansion coefficient of the first dielectric layer; an electronic component disposed on the second side of the circuit structure to be electrically connected to the first circuit layer; and The coating layer is filled in the through hole and is arranged on the second side of the circuit structure to cover the circuit component and the electronic element, and the conductive layer is exposed on the coating layer, wherein the thermal expansion coefficient of the coating layer is greater than the thermal expansion coefficient of the first dielectric layer.

2. The electronic package of claim 1, wherein: The thermal expansion coefficient of the insulating film body is greater than the thermal expansion coefficient of the coating layer.

3. The electronic package of claim 1, wherein: A conductive element electrically connecting the conductive layer and the first circuit layer is disposed in the through hole.

4. The electronic package of claim 1, wherein: The electronic package also includes a second circuit layer formed on the covering layer and electrically connected to the conductive layer.

5. The electronic package of claim 1, wherein: The electronic package also includes a second circuit layer formed on the second dielectric layer and electrically connected to the conductor.

6. A method for manufacturing an electronic package, comprising: A core-less circuit structure is provided, wherein the circuit structure has a first side and a second side opposite to each other, and the circuit structure comprises at least one first dielectric layer and a first circuit layer disposed on the first dielectric layer; An external connection structure is formed on the first side of the circuit structure, wherein the external connection structure includes a second dielectric layer formed on the first dielectric layer and a conductor embedded in the second dielectric layer and electrically connected to the first circuit layer, and the thermal expansion coefficient of the first dielectric layer is greater than the thermal expansion coefficient of the second dielectric layer; The circuit assembly is arranged on the second side of the circuit structure so that the circuit assembly is electrically connected to the first circuit layer, wherein the circuit assembly comprises an insulating film having a plurality of through holes and a conductive layer formed on the wall surface of the through holes so that the conductive layer contacts the first circuit layer to electrically connect to the first circuit layer, and the thermal expansion coefficient of the insulating film is greater than the thermal expansion coefficient of the first dielectric layer; Disposing an electronic component on the second side of the circuit structure so that the electronic component is electrically connected to the first circuit layer; and Fill the through hole with a coating layer and form the coating layer on the second side of the circuit structure so that the coating layer covers the circuit component and the electronic element and the conductive layer is exposed on the coating layer, wherein the thermal expansion coefficient of the coating layer is greater than the thermal expansion coefficient of the first dielectric layer.

7. The method for manufacturing an electronic package as claimed in claim 6, wherein: The thermal expansion coefficient of the insulating film body is greater than the thermal expansion coefficient of the coating layer.

8. The method for manufacturing an electronic package as claimed in claim 6, wherein: A conductive element electrically connecting the conductive layer and the first circuit layer is disposed in the through hole.

9. The method for manufacturing an electronic package as claimed in claim 6, wherein: The manufacturing method includes forming a second circuit layer on the cladding layer, and making the second circuit layer electrically connected to the conductive layer.

10. The method for manufacturing an electronic package according to claim 6, wherein: The manufacturing method also includes forming a second circuit layer on the second dielectric layer, so that the second circuit layer is electrically connected to the conductor.

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