An artificial intelligence chip access system and its construction method, operator calling method

Abstract

The present application discloses an artificial intelligence chip access system and its construction method, operator calling method and equipment, storage medium and computer program product. The artificial intelligence chip access system includes: a unified interface layer, including a unified interface for calling operators; a public processing layer, used to implement the common logical operations of different types of artificial intelligence chips calling operators; a chip processing layer, including processing modules corresponding to different types of artificial intelligence chips, and the processing modules are used to implement the unique logical operations of the corresponding types of artificial intelligence chips calling operators. The present application uses a unified interface of operators to enable the same operator to be called in the same way on different types of artificial intelligence chips, extracts the common logical operations of operators through a public processing layer, and implements code reuse for different types of artificial intelligence chips to implement operator functions, thereby improving the development efficiency of newly connected artificial intelligence chips and the access efficiency of artificial intelligence chips.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more specifically, to an artificial intelligence chip access system and a construction method thereof, an operator calling method and device, a storage medium, and a computer program product. Background Art

[0002] With the rise of artificial intelligence, different types of AI (Artificial Intelligence) chips use their own API (Application Programming Interface) interfaces or their own programming languages. In addition, there are many differences, such as instruction sets, computing architectures, etc., which leads to a lot of time and effort when deploying and optimizing algorithms on different hardware, and a large cost and time when connecting to the AI ​​framework. In related technologies, when different types of artificial intelligence chips are connected to the AI ​​framework, they need to be developed separately for different types of artificial intelligence chips, and the efficiency of connecting to artificial intelligence chips is low.

[0003] Therefore, how to improve the access efficiency of artificial intelligence chips is a technical problem that technicians in this field need to solve. Summary of the invention

[0004] The purpose of this application is to provide an artificial intelligence chip access system and its construction method, operator calling method and equipment, storage medium and computer program product, which improve the access efficiency of artificial intelligence chips.

[0005] To achieve the above objectives, the present application provides an artificial intelligence chip access system, including:

[0006] Unified interface layer, including the unified interface for calling operators;

[0007] The common processing layer is used to implement the common logic operations of different types of artificial intelligence chips calling the operators;

[0008] The chip processing layer includes processing modules corresponding to different types of artificial intelligence chips, and the processing modules are used to implement the unique logical operations of the corresponding type of artificial intelligence chips calling the operators.

[0009] Among them, the processing module includes a conversion unit and a logic processing unit. The conversion unit is used to convert the data transmitted by the common processing layer into a data type supported by the corresponding type of artificial intelligence chip, and the logic processing unit is used to implement the corresponding type of artificial intelligence chip calling the unique logical operation of the operator based on the converted data.

[0010] The logic processing unit includes an application programming interface or a kernel function of the operator.

[0011] The data transmitted from the common processing layer to the chip processing layer includes input data information and output data information, wherein the input data information includes any one or a combination of several items in the shape, window step, and dimension of the input array, and the output data information includes any one or a combination of several items in the shape, window step, and dimension of the output array.

[0012] The operator includes any one or a combination of any two of a convolution operator, a matrix multiplication operator, and an activation operator.

[0013] Among them, the data types of the input data and output data of the unified interface are general data types that are independent of the data types supported by different types of artificial intelligence chips.

[0014] The common logic operation includes a type conversion operation and / or an error information judgment operation.

[0015] To achieve the above objectives, the present application provides a method for constructing an artificial intelligence chip access system, including:

[0016] Create a unified interface for calling operators for different types of AI chips, and build a unified interface layer based on the unified interfaces corresponding to different operators;

[0017] Extract the common logic operations of different types of AI chip call operators, and build a common processing layer based on the common logic operations corresponding to different operators;

[0018] Based on the unique logical operations of different types of artificial intelligence chips calling operators, processing modules corresponding to different types of artificial intelligence chips are constructed, and chip processing layers are constructed based on the processing modules corresponding to different types of artificial intelligence chips.

[0019] Among them, the processing modules corresponding to different types of artificial intelligence chips are constructed based on the unique logical operations of different types of artificial intelligence chips calling operators, including:

[0020] Constructing conversion units corresponding to different types of artificial intelligence chips; wherein the conversion unit is used to convert the data input by the common processing layer into a data type supported by the corresponding type of artificial intelligence chip;

[0021] Constructing logic processing units corresponding to different types of artificial intelligence chips; wherein the logic processing units are used to implement the unique logic operations of the corresponding type of artificial intelligence chips calling the operators based on the converted data;

[0022] Based on the conversion units and logic processing units corresponding to different types of artificial intelligence chips, processing modules corresponding to different types of artificial intelligence chips are constructed.

[0023] Among them, it also includes:

[0024] When there is an artificial intelligence chip newly connected to the artificial intelligence chip access system, determining the target type of the artificial intelligence chip;

[0025] Constructing a processing module corresponding to the target type of artificial intelligence chip based on the unique logical operation of the artificial intelligence chip calling operator of the target type;

[0026] Add the processing module corresponding to the artificial intelligence chip of the target type to the chip processing layer.

[0027] Among them, constructing a processing module corresponding to the target type of artificial intelligence chip based on the unique logical operation of the artificial intelligence chip calling operator of the target type includes:

[0028] Constructing a conversion unit corresponding to the target type of artificial intelligence chip; wherein the conversion unit is used to convert the data passed by the public processing layer into a data type supported by the target type of artificial intelligence chip;

[0029] Construct a logic processing unit corresponding to the target type of artificial intelligence chip; wherein the logic processing unit is used to implement the unique logic operation of the target type of artificial intelligence chip calling the operator based on the converted data.

[0030] To achieve the above purpose, the present application provides an operator calling method, which is applied to the above-mentioned artificial intelligence chip access system, including:

[0031] When the target operator of the target type of artificial intelligence chip needs to be called, the unified interface corresponding to the target operator in the unified interface layer is called;

[0032] Executing the common logic operation of the target operator in the common processing layer;

[0033] In the chip processing layer, the processing module corresponding to the artificial intelligence chip of the target type is used to convert the data transmitted from the public processing layer into the data type supported by the artificial intelligence chip of the target type, and determine whether there is an application programming interface corresponding to the target operator in the artificial intelligence chip of the target type. If so, the application programming interface corresponding to the target operator is called based on the converted data; if not, the kernel function corresponding to the target operator is called based on the converted data; wherein the application programming interface or kernel function corresponding to the target operator is used to implement the unique logical operation of the artificial intelligence chip of the target type calling the target operator.

[0034] To achieve the above objectives, the present application provides an electronic device, including:

[0035] Memory for storing computer programs;

[0036] A processor is used to implement the steps of the method for constructing the artificial intelligence chip access system or the method for calling the operator as described above when executing the computer program.

[0037] To achieve the above-mentioned objectives, the present application provides a non-volatile storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the construction method or operator calling method of the above-mentioned artificial intelligence chip access system are implemented.

[0038] To achieve the above-mentioned objectives, the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the construction method or operator calling method of the above-mentioned artificial intelligence chip access system.

[0039] From the above scheme, it can be seen that an artificial intelligence chip access system provided by the present application includes: a unified interface layer, including a unified interface for calling operators; a common processing layer, used to implement common logical operations of different types of artificial intelligence chips calling the operators; a chip processing layer, including processing modules corresponding to different types of artificial intelligence chips, and the processing modules are used to implement the unique logical operations of the corresponding types of artificial intelligence chips calling the operators.

[0040] It can be seen that the artificial intelligence chip access system provided by this application enables the same operator to be called in the same way on different types of artificial intelligence chips through the unified interface of the operator, and extracts the common logical operation of the operator through the common processing layer, so as to realize the code reuse of different types of artificial intelligence chips to realize the operator function, improve the development efficiency of newly connected artificial intelligence chips, improve the access efficiency of artificial intelligence chips, reduce the development cost and maintenance cost of newly connected artificial intelligence chips, and improve the scalability of artificial intelligence chip access system. This application also discloses a construction method of artificial intelligence chip access system, an operator calling method, an electronic device, a non-volatile storage medium and a computer program product, which can also achieve the above technical effects.

[0041] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. The drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific implementation methods, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:

[0043] Figure 1 This is a structural diagram of an artificial intelligence chip access system according to an exemplary embodiment;

[0044] Figure 2 This is a flow chart of a method for constructing an artificial intelligence chip access system according to an exemplary embodiment;

[0045] Figure 3 is a flowchart of an operator calling method according to an exemplary embodiment;

[0046] Figure 4 is a flowchart of calling an operator according to an exemplary embodiment;

[0047] Figure 5 The figure is a structural diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. In addition, in the embodiments of the present application, "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0049] This embodiment provides an artificial intelligence chip access system, such as Figure 1 As shown, including:

[0050] Unified interface layer, including the unified interface for calling operators;

[0051] The public processing layer is used to implement the public logic operations of different types of artificial intelligence chips calling the operators;

[0052] The chip processing layer includes processing modules corresponding to different types of artificial intelligence chips, and the processing modules are used to implement the unique logical operations of the corresponding type of artificial intelligence chips calling the operators.

[0053] In the specific implementation, a unified set of operator interfaces is defined, that is, the same operators of different types of artificial intelligence chips are called through a unified interface. The operators may include convolution operators, matrix multiplication operators, activation operators, etc.

[0054] As an optional implementation, the data types of the input data and output data of the unified interface are general data types that are independent of the data types supported by different types of artificial intelligence chips. In a specific implementation, the data types transmitted by the unified interface are general data types that do not include the data types of the back-end artificial intelligence chips, making the back-end artificial intelligence chips transparent to the front-end interface and achieving decoupling of the front-end and back-end.

[0055] Furthermore, in order to facilitate data processing, input data and output data can be passed through arrays. For example, the pseudo code of the unified interface is as follows: void OperatorName(const DataArray& input, DataArray &output). The interface format is relatively simple, which is convenient for front-end encapsulation and calling, and also convenient for unified registration of many front-end registration mechanisms. Among them, the DataArray data structure is as follows:

[0056] stuct DataArray {

[0057] size_t nSize; / / array size;

[0058] DataValue* pData; / / array pointer, pointing to data;

[0059] DataType type; / / Data type, corresponding to the type of each data;

[0060] }

[0061] DataArray can contain any number of arbitrary data types. In this way, the interface is simplified. At the same time, the C language interface is used to solve the problems caused by cross-compiler and cross-platform, and it can be dynamically loaded as a dynamic library by different programs.

[0062] Use a Union to store different data, and add multiple data types as needed:

[0063] Union DataValue {

[0064] UTensor* pTensor;

[0065] float floatValue;

[0066] … …

[0067] int64_t int64_value;

[0068] }

[0069] You can use enumeration to define data types, corresponding to the various data of DataValue:

[0070] Enum DataType {

[0071] TYPE_INVALID = 0,

[0072] TYPE_UTENSORHANDLE = 1,

[0073] TYPE_FLOAT = 2,

[0074] … …

[0075] TYPE_LONG

[0076] }

[0077] Encapsulation of Tensor (array) information:

[0078] Struct UTensor {

[0079] Void* pData; / / tensor data storage pointer;

[0080] size_t* pStride; / / stride information pointer;

[0081] size_t* pShape; / / shape information pointer;

[0082] … …

[0083] int nDims; / / dimensions;

[0084] }

[0085] For the input and output of an operator, the meaning of the corresponding position parameters and the parameter types can be defined in advance by formulating the same interface. Take a simple summation operator add as an example. There are two inputs. The first input is the first number to be added, and the data type is UTensor. The second input is the second number to be added, and the data type is UTensor. There is one output, and the data type is UTensor. Through the above definition, two UTensors can be obtained from the input, and the addition operation can be performed. The result is placed on the output to complete the entire operation.

[0086] In the public processing layer, through the definition of the operator, each input of the operator is obtained and parsed, and then general logical operations are performed. The general logical operations may include type conversion operations, error information judgment operations, etc.

[0087] As an optional embodiment, the data transmitted from the common processing layer to the chip processing layer includes input data information and output data information, wherein the input data information includes any one or a combination of several items in the shape, window step, and dimension of the input array, and the output data information includes any one or a combination of several items in the shape, window step, and dimension of the output array.

[0088] In the public processing layer, some data types are abstracted, usually including the descriptors required when calling the API of each AI chip or the information required when calling the kernel (kernel function), such as the shape of the input array and the output array, the window step (stride), and the dimension. Different types of AI chips have different processing logics. The required information can be extracted and encapsulated into the public class (XXXDescriptor). Different types of AI chips use the same name to implement their own encapsulation, so that different types of AI chips can be used. This information is passed to the AI ​​chip by calling the interface provided by the chip processing layer.

[0089] For example, the implementation of the public class is as follows:

[0090] <typename T>

[0091] class TensorDescriptor {

[0092] public:

[0093] / / You can directly pass shape, stride, dimension information, or pass UTensor and get it from UTenor internally;

[0094] TensorDescriptor(int64_t* pShape, int64_t* pStride, int nDim);

[0095] TensorDescriptor(UTensor* pUT);

[0096] / / Each chip only needs to implement its own specialized version;

[0097] T getDescriptor();

[0098] / / Get the location of the nNumth data; since the stride, logical sequence number and physical storage location are not necessarily consistent;

[0099] / / This information is usually needed in the kernel. Similarly, other functions can be added to implement common functions.

[0100] size_t position(size_t nNum);

[0101] }

[0102] It can be seen that the unified interface layer and the public processing layer are public parts, which are decoupled from the artificial intelligence chip and only need to be implemented once.

[0103] In the chip processing layer, the information transmitted from the public processing layer is used to implement the unique logical operations of different types of artificial intelligence chip calling operators through the processing modules corresponding to different types of artificial intelligence chips.

[0104] As an optional implementation, the processing module includes a conversion unit and a logic processing unit. The conversion unit is used to convert the data transmitted from the common processing layer into a data type supported by the corresponding type of artificial intelligence chip, and the logic processing unit is used to implement the corresponding type of artificial intelligence chip to call the unique logical operation of the operator based on the converted data.

[0105] In a specific implementation, the conversion unit receives the data passed in by the public processing layer, reorganizes it into the data type supported by the corresponding type of artificial intelligence chip, and the logic processing unit calls the application programming interface or kernel function corresponding to the operator. For an operator, if the artificial intelligence chip supports the application programming interface corresponding to the operator, the logic processing unit can directly call the application programming interface. If it does not support it, it is necessary to create a corresponding kernel function to implement the unique logical operation of the artificial intelligence chip calling the operator. The conversion unit can be optimized according to the characteristics of different types of artificial intelligence chips, converting general operators into efficient hardware instructions or kernel function calls, thereby improving the execution efficiency of the algorithm on specific hardware.

[0106] It can be seen that the chip processing layer is tightly coupled with the artificial intelligence chip and needs to be implemented separately for the artificial intelligence chip. This needs to be implemented for each type of artificial intelligence chip that is connected.

[0107] Through the above three-layer architecture, a unified interface of operators is provided to the outside world, which is easy to call. Different types of artificial intelligence chips share the unified interface layer and the public processing layer. Each operator only needs to implement the unified interface layer and the public processing layer once, which improves development efficiency and reduces maintenance manpower and costs. Due to the use of the public processing layer, a general optimization solution can be used, and all chips can benefit from modifying them at one time. In addition, the chip processing layer only needs to implement the unique logical operations of each artificial intelligence chip, which simplifies the development difficulty and workload. When compiling, specify the backend device name to compile and generate the executable library corresponding to the backend.

[0108] It can be seen that the artificial intelligence chip access system provided in the embodiment of the present application enables the same operator to be called in the same way on different types of artificial intelligence chips through the unified interface of the operator, and extracts the common logical operations of the operator through the common processing layer, thereby realizing code reuse for operator functions of different types of artificial intelligence chips, improving the development efficiency of newly accessed artificial intelligence chips, improving the access efficiency of artificial intelligence chips, reducing the development cost and maintenance cost of newly accessed artificial intelligence chips, and improving the scalability of the artificial intelligence chip access system.

[0109] This embodiment provides a method for constructing an artificial intelligence chip access system. Figure 2 As shown, including:

[0110] S101: Create a unified interface for calling operators for different types of artificial intelligence chips, and build a unified interface layer based on the unified interfaces corresponding to different operators;

[0111] S102: extracting common logic operations of different types of artificial intelligence chips calling operators, and building a common processing layer based on the common logic operations corresponding to different operators;

[0112] S103: Construct processing modules corresponding to different types of artificial intelligence chips based on the unique logical operations of different types of artificial intelligence chip calling operators, and construct a chip processing layer based on the processing modules corresponding to different types of artificial intelligence chips.

[0113] In the specific implementation, firstly, a unified interface layer is constructed, which includes unified interfaces corresponding to different operators, and the same operators of different types of artificial intelligence chips can be called through the unified interface. Secondly, the common logical operations of different types of artificial intelligence chips calling operators are extracted to construct a common processing layer. Then, a chip processing layer is constructed, which includes processing modules corresponding to different types of artificial intelligence chips, and the processing modules are used to implement the unique logical operations of the corresponding types of artificial intelligence chips calling operators.

[0114] As an optional implementation, processing modules corresponding to different types of artificial intelligence chips are constructed based on the unique logical operations of different types of artificial intelligence chips calling operators, including: constructing conversion units corresponding to different types of artificial intelligence chips; wherein the conversion units are used to convert the data transmitted by the common processing layer into the data type supported by the corresponding type of artificial intelligence chip; constructing logical processing units corresponding to different types of artificial intelligence chips; wherein the logical processing units are used to implement the unique logical operations of the corresponding type of artificial intelligence chip calling the operator based on the converted data; and constructing processing modules corresponding to different types of artificial intelligence chips based on the conversion units and logical processing units corresponding to different types of artificial intelligence chips.

[0115] In a specific implementation, when constructing processing modules corresponding to different types of artificial intelligence chips, first construct a conversion unit, which is used to convert the data passed in by the common processing layer into the data type supported by the corresponding type of artificial intelligence chip, and then construct a logic processing unit, which is used to implement the unique logic operation of the corresponding type of artificial intelligence chip calling the operator based on the converted data. The logic processing unit may include the application programming interface or kernel function of the operator.

[0116] As an optional implementation, it also includes: when there is an artificial intelligence chip newly connected to the artificial intelligence chip access system, determining the target type of the artificial intelligence chip; constructing a processing module corresponding to the target type of artificial intelligence chip based on the unique logical operation of the artificial intelligence chip calling operator of the target type; and adding the processing module corresponding to the target type of artificial intelligence chip to the chip processing layer.

[0117] In a specific implementation, when there is an AI chip newly connected to the AI ​​chip access system, the target type of the newly connected AI chip is determined, and a processing module corresponding to the target type of AI chip is constructed based on the unique logical operation of the target type of AI chip calling operator, and it is added to the chip processing layer. It can be seen that when an AI chip is newly connected to the AI ​​chip access system, only the corresponding processing module needs to be implemented, that is, only the unique logical operation of its calling operator needs to be implemented, which improves the scalability of the AI ​​chip access system.

[0118] As an optional implementation, a processing module corresponding to the target type of artificial intelligence chip is constructed based on the unique logical operation of the target type of artificial intelligence chip calling the operator, including: constructing a conversion unit corresponding to the target type of artificial intelligence chip; wherein the conversion unit is used to convert the data transmitted by the public processing layer into a data type supported by the target type of artificial intelligence chip; constructing a logical processing unit corresponding to the target type of artificial intelligence chip; wherein the logical processing unit is used to implement the unique logical operation of the target type of artificial intelligence chip calling the operator based on the converted data.

[0119] In a specific implementation, when implementing the processing module corresponding to the target type of artificial intelligence chip, first construct a conversion unit, which is used to convert the data passed in by the common processing layer into the data type supported by the target type of artificial intelligence chip, and then construct a logic processing unit, which is used to implement the unique logic operation of the target type of artificial intelligence chip calling operator based on the converted data.

[0120] As an optional implementation, constructing a logical processing unit corresponding to the target type of artificial intelligence chip includes: determining whether the target type of artificial intelligence chip supports the application programming interface of the operator; if so, constructing a logical processing unit corresponding to the target type of artificial intelligence chip based on the application programming interface; if not, constructing a kernel function for the target type of artificial intelligence chip to call the operator, and constructing a logical processing unit corresponding to the target type of artificial intelligence chip based on the kernel function.

[0121] In the specific implementation, for a certain operator, if the target type of AI chip supports its corresponding application programming interface, the function of the operator can be implemented by calling the application programming interface, without the need to develop additional logic, thus improving the access efficiency of the AI ​​chip. If it is not supported, it is necessary to develop a separate kernel function to implement the operator.

[0122] This embodiment provides an operator calling method, such as Figure 3 As shown, including:

[0123] S201: When it is necessary to call a target operator of an artificial intelligence chip of a target type, call a unified interface corresponding to the target operator in the unified interface layer;

[0124] S202: Execute the common logic operation of the target operator in the common processing layer;

[0125] S203: In the chip processing layer, using the processing module corresponding to the artificial intelligence chip of the target type, convert the data transmitted from the public processing layer into a data type supported by the artificial intelligence chip of the target type, and determine whether there is an application programming interface corresponding to the target operator in the artificial intelligence chip of the target type; if so, call the application programming interface corresponding to the target operator based on the converted data; if not, call the kernel function corresponding to the target operator based on the converted data; wherein, the application programming interface or kernel function corresponding to the target operator is used to implement the unique logical operation of the artificial intelligence chip of the target type calling the target operator.

[0126] This embodiment is applied to the artificial intelligence chip access system provided by the above embodiment. In the specific implementation, when the target operator of the target type artificial intelligence chip needs to be called, the unified interface corresponding to the target operator in the unified interface layer is called, the public logic operation of the target operator is executed in the public processing layer, and the processing module corresponding to the target type artificial intelligence chip is called in the chip processing layer. The data transmitted from the public processing layer is converted into the data type supported by the target type artificial intelligence chip through the conversion unit in the processing module. The logic processing unit in the processing module determines whether there is an application programming interface corresponding to the target operator in the target type artificial intelligence chip. If so, the application programming interface corresponding to the target operator is called based on the converted data. If not, the kernel function corresponding to the target operator is called based on the converted data.

[0127] The flowchart of calling the operator is as follows Figure 4 As shown, the following steps are included:

[0128] Step 1: Call an operator interface;

[0129] Step 2: Public processing;

[0130] Step 3: Call the AI ​​chip’s unique implementation;

[0131] Step 4: Do some internal processing;

[0132] Step 5: If there is an API for the corresponding chip, some descriptors are usually required, which can be obtained from the encapsulated public class (YYYDescriptor);

[0133] Step 6: Call the API provided by the chip to perform operations;

[0134] Step 7: If there is no corresponding chip API, call your own kernel implementation. Usually the kernel needs the physical location corresponding to the logical location, or some other information, which can also be obtained from the public class (YYYDescriptor). The public class (YYYDescriptor) here needs to be implemented with the same name for each chip, and the compilation option determines which one to use.

[0135] Taking the call of the convolution operator conv2d as an example, the pseudo code is as follows:

[0136] void conv2d(const DataArray& input, DataArray & output)

[0137] {

[0138] / / Parse the input and output, check for unset parameters, and fill in default values ​​for unset ones;

[0139] assert(input[0].type == TYPE_UTENSORHANDLE)

[0140] assert(input[1].type == TYPE_UTENSORHANDLE)

[0141] assert(input[2].type == TYPE_UTENSORHANDLE)

[0142] UTensor* x = input[0].as<UTensor*> ();

[0143] UTensor* w = input[1].as<UTensor*> ();

[0144] UTensor* b = input[2].as<UTensor*> ();

[0145] vector<int64_t> *dilation_long = (*input[3]);

[0146] … …

[0147] UTensor* y = output[0].as<UTensor*> ();

[0148] … …

[0149] / / Use unified descriptor encapsulation;

[0150] TensorDescriptor x_d(x);

[0151] TensorDescriptor w_d(w);

[0152] TensorDescriptor y_d(y);

[0153] … …

[0154] / / Error checking;

[0155] CHECK(x->ndim == 4, "conv2d only supports 4D!");

[0156] / / Type check, if it does not meet the requirements, do type conversion;

[0157] …

[0158] / / Call chip implementation, each chip has its own implementation;

[0159] / / Specify and link the implementation of the specified chip through the compilation options during compilation;

[0160] Conv2d_inner(x, x_d,w, w_d ,b,dilation_long,…, y, y_d);

[0161] }

[0162] / / Cuda version implements pseudo code, some contents can also be encapsulated;

[0163] Conv2d_inner(UTensor* x, TensorDescriptor tx_desc,UTensor* w,TensorDescriptor tx_desc, UTensor* b, vector <long>dilation_long,…,UTensor* y, TensorDescriptor y_desc) {

[0164] / / Prepare data for calling the API;

[0165] … …

[0166] CHECK(cudnnConvolutionForward(handle, &alpha, tx_desc, x->data, w_desc,…, w->data, y_desc, y->data, ));

[0167] }

[0168] Based on the hardware implementation of the above program module, and in order to implement the method of the embodiment of the present application, the embodiment of the present application also provides an electronic device, Figure 5 FIG. 1 is a structural diagram of an electronic device according to an exemplary embodiment. Figure 5 As shown, the electronic equipment includes:

[0169] Communication interface 1, capable of exchanging information with other devices such as network devices;

[0170] The processor 2 is connected to the communication interface 1 to realize information interaction with other devices, and is used to execute the construction method or operator calling method of the artificial intelligence chip access system provided by one or more technical solutions when running the computer program. The computer program is stored in the memory 3.

[0171] Of course, in actual application, the various components in the electronic device are coupled together through the bus system 4. It can be understood that the bus system 4 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 4 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 5 Various buses are labeled as bus system 4.

[0172] The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program used to operate on the electronic device.

[0173] It can be understood that the memory 3 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAMbus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory 3 described in the embodiments of the present application is intended to include but is not limited to these and any other suitable types of memories.

[0174] The method disclosed in the above embodiment of the present application can be applied to the processor 2, or implemented by the processor 2. The processor 2 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 2 or the instruction in the form of software. The above processor 2 may be a general-purpose processor, a DSP, or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 2 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. In combination with the steps of the method disclosed in the embodiment of the present application, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in the memory 3, and the processor 2 reads the program in the memory 3 and completes the steps of the above method in combination with its hardware.

[0175] When the processor 2 executes the program, the corresponding processes in the various methods of the embodiments of the present application are implemented, which will not be repeated here for the sake of brevity.

[0176] In an exemplary embodiment, the embodiment of the present application further provides a non-volatile storage medium storing a computer program, which can be executed by the processor 2 to complete the steps of the aforementioned method.

[0177] In an exemplary embodiment, the present application also provides a computer program product, including a computer program, which is executed by the processor 2 to complete the steps of the aforementioned method.

[0178] A person of ordinary skill in the art can understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to computer program instructions, and the aforementioned computer program can be stored in a non-volatile storage medium. When the computer program is executed, it executes the steps of the above-mentioned method embodiment. Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the embodiment of the present application can be essentially or partly embodied in the form of a software product, which is stored in a non-volatile storage medium and includes a number of instructions for an electronic device (which can be a personal computer, a server, a network device, etc.) to execute all or part of the methods described in each embodiment of the present application.

[0179] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.< / long>

Claims

1. An artificial intelligence chip access system, characterized in that: include: Unified interface layer, including the unified interface for calling operators; The public processing layer is used to implement the public logic operations of different types of artificial intelligence chips calling the operators; The chip processing layer includes processing modules corresponding to different types of artificial intelligence chips, and the processing modules are used to implement the unique logical operations of the corresponding type of artificial intelligence chip calling the operator; The processing module includes a conversion unit and a logic processing unit. The conversion unit is used to convert the data input by the common processing layer into a data type supported by the corresponding type of artificial intelligence chip. The logic processing unit is used to implement the unique logic operation of the corresponding type of artificial intelligence chip calling the operator based on the converted data. Among them, the data types of the input data and output data of the unified interface are general data types that are independent of the data types supported by different types of artificial intelligence chips, thereby realizing the decoupling of the back-end artificial intelligence chip and the front-end unified interface.

2. The artificial intelligence chip access system according to claim 1, characterized in that: The logic processing unit includes an application programming interface or a kernel function of the operator.

3. The artificial intelligence chip access system according to claim 1, characterized in that: The data transmitted from the common processing layer to the chip processing layer includes input data information and output data information. The input data information includes the shape, window step, and any one or a combination of several items of the input array, and the output data information includes the shape, window step, and any one or a combination of several items of the output array.

4. The artificial intelligence chip access system according to claim 1, characterized in that: The operator includes any one or a combination of any several of a convolution operator, a matrix multiplication operator, and an activation operator.

5. The artificial intelligence chip access system according to claim 1, characterized in that: The common logic operation includes a type conversion operation and / or an error information judgment operation.

6. A method for constructing an artificial intelligence chip access system, characterized in that: include: Create a unified interface for calling operators for different types of AI chips, and build a unified interface layer based on the unified interfaces corresponding to different operators; Extract the common logic operations of different types of AI chip call operators, and build a common processing layer based on the common logic operations corresponding to different operators; Based on the unique logical operations of different types of artificial intelligence chips calling operators, processing modules corresponding to different types of artificial intelligence chips are constructed, and chip processing layers are constructed based on the processing modules corresponding to different types of artificial intelligence chips; Among them, the processing modules corresponding to different types of artificial intelligence chips are constructed based on the unique logical operations of different types of artificial intelligence chips calling operators, including: Constructing conversion units corresponding to different types of artificial intelligence chips; wherein the conversion unit is used to convert the data input by the common processing layer into a data type supported by the corresponding type of artificial intelligence chip; Constructing logic processing units corresponding to different types of artificial intelligence chips; wherein the logic processing units are used to implement the unique logic operations of the corresponding type of artificial intelligence chips calling the operators based on the converted data; Construct processing modules corresponding to different types of artificial intelligence chips based on conversion units and logic processing units corresponding to different types of artificial intelligence chips; Among them, the data types of the input data and output data of the unified interface are general data types that are independent of the data types supported by different types of artificial intelligence chips, thereby realizing the decoupling of the back-end artificial intelligence chip and the front-end unified interface.

7. The method for constructing an artificial intelligence chip access system according to claim 6, characterized in that: Also includes: When there is an artificial intelligence chip newly connected to the artificial intelligence chip access system, determining the target type of the artificial intelligence chip; Constructing a processing module corresponding to the target type of artificial intelligence chip based on the unique logical operation of the artificial intelligence chip calling operator of the target type; Add the processing module corresponding to the artificial intelligence chip of the target type to the chip processing layer.

8. The method for constructing an artificial intelligence chip access system according to claim 7, characterized in that: The processing module corresponding to the artificial intelligence chip of the target type is constructed based on the unique logical operation of the artificial intelligence chip calling operator of the target type, including: Constructing a conversion unit corresponding to the target type of artificial intelligence chip; wherein the conversion unit is used to convert the data passed by the public processing layer into a data type supported by the target type of artificial intelligence chip; Construct a logic processing unit corresponding to the target type of artificial intelligence chip; wherein the logic processing unit is used to implement the unique logic operation of the target type of artificial intelligence chip calling the operator based on the converted data.

9. An operator calling method, characterized in that: Applicable to the artificial intelligence chip access system as claimed in any one of claims 1 to 5, comprising: When it is necessary to call the target operator of the target type of artificial intelligence chip, call the unified interface corresponding to the target operator in the unified interface layer; wherein the data types of the input data and output data of the unified interface are general data types that are independent of the data types supported by different types of artificial intelligence chips, thereby realizing the decoupling of the back-end artificial intelligence chip and the front-end unified interface; Executing the common logic operation of the target operator in the common processing layer; In the chip processing layer, the conversion unit in the processing module corresponding to the artificial intelligence chip of the target type is used to convert the data transmitted from the public processing layer into the data type supported by the artificial intelligence chip of the target type, and the logic processing unit in the processing module corresponding to the artificial intelligence chip of the target type is used to determine whether there is an application programming interface corresponding to the target operator in the artificial intelligence chip of the target type. If so, the application programming interface corresponding to the target operator is called based on the converted data. If not, the kernel function corresponding to the target operator is called based on the converted data; wherein the application programming interface or kernel function corresponding to the target operator is used to implement the unique logical operation of the artificial intelligence chip of the target type calling the target operator.

10. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, used to implement the steps of the method for constructing an artificial intelligence chip access system as described in any one of claims 6 to 8 or the operator calling method as described in claim 9 when executing the computer program.

11. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a computer program, which, when executed, implements the steps of the method for constructing an artificial intelligence chip access system as described in any one of claims 6 to 8 or the operator calling method as described in claim 9.

12. A computer program product, characterized in that It includes a computer program, which, when executed by a processor, implements the steps of the method for constructing an artificial intelligence chip access system as described in any one of claims 6 to 8 or the operator calling method as described in claim 9.

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